VLSI Design and Testing Lab

BECL606
6th SEMESTER, EVEN 2025

Prepared by
Dr. G Manjula, Associate Professor, Dept. of ECE,
Mr. Bore Gowda H B , Assistant Professor, Dept. of ECE,
Mrs. Padma R, Assistant Professor, Dept. of ECE,
GSSSIETW, Mysuru
 DEPARTMENT VISION & MISSION
VISION

"To foster professional level competence in all areas of Electronics and Communication
Engineering and to benchmark the Department as a centre for nurturing Women Engineers
in the Country"

MISSION
M1: To impart value based Technical education and training.

M2: To impart Theoretical Knowledge, Practical Knowledge and Entrepreneurship Skills.

M3: Fostering culture of innovation and research for development of society.

M4: To sensitize the Students regarding Social, Moral and Professional ethics.

M5: To provide industry standard certifications on skills to enhance students knowledge

make them prepared for placements

Program Educational Objective’s

PEO 1: To inculcate students to excel in professional career and/or higher education by

acquiring knowledge in the field of Electronics and Communication.

PEO 2: To make the students capable of managing their profession based on existing as well
as new emerging technologies in the area of Electronics and Communication
Engineering.

PEO 3: To Produce Technically competent graduates with Ability to analyse, design,

develop, optimise and implement Electronics and Communication systems.

PEO 4: To prepare the students to be able to exhibit professionalism, ethical attitude,

communication skills, team work in their profession and to adapt to current trends by
engaging in life-long learning
 INSTITUTION VISION & MISSION

Vision
"To become a recognized world class Women Educational Institution, by
imparting professional education to the students, creating technical
opportunities through academic excellence and technical achievements,with
ethical values"

Mission
 To support value based education with state of art infrastructure.
To empower women with the additional skill for professional future career.
 To enrich students with research blends in order to fulfill the International
Challenges.
To create multidisciplinary center of excellence.
 To achieve Accreditation standards towards International education
recognition.
To establish more Post Graduate & Research course.
 To increase Doctorates numbers towards the Research quality of academics.
 PROGRAM OUTCOMES

Engineering Graduates will be able to:

1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals, and an engineering specialization to the solution of complex engineering
problems.

2. Problem analysis: Identify, formulate, review research literature, and analyze complex
engineering problems reaching substantiated conclusions using first principles of mathematics,
natural sciences, and engineering sciences.

3. Design/development of solutions: Design solutions for complex engineering problems and

design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and environmental
considerations.

4. Conduct investigations of complex problems: Use research-based knowledge and research

methods including design of experiments, analysis and interpretation of data, and synthesis of the
information to provide valid conclusions.

5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modeling to complex engineering activities
with an understanding of the limitations.

6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to
the professional engineering practice.

7. Environment and sustainability: Understand the impact of the professional engineering

solutions in societal and environmental contexts, and demonstrate the knowledge of, and need
for sustainable development.

8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
norms of the engineering practice.
9. Individual and team work: Function effectively as an individual, and as a member or leader
in diverse teams, and in multidisciplinary settings.

10. Communication: Communicate effectively on complex engineering activities with the

engineering community and with society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective presentations, and give and receive
clear instructions.

11. Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member and
leader in a team, to manage projects and in multidisciplinary environments.

12. Life-long learning: Recognize the need for, and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change.

PROGRAM SPECIFIC OUTCOMES

PSO1. Graduates will have the ability to mould the technology in the areas of Analog and
Digital Scenario.
PSO2. Implementation of functional Blocks of hardware software co-design for signal
processing and communication application.
 COURSE OUTCOMES Year of Study: 2024-25

SEMESTER & YEAR: VI, EVEN SEM 2025 FACULTY NAME: Dr. G Manjula , Mr. Bore Gowda H B, Mrs. Padma R
COURSE NAME/CODE: VLSI Design and Testing Lab / BECL606(C316)

 Design and simulate combinational and sequential digital circuits using Verilog HDL
 Understand the synthesis process of digital circuits using EDA tool
 Perform ASIC design flow and understand the process of synthesis, synthesis
constraints and evaluating the synthesis reports to obtain optimum gate level netlist.
 Design and simulate basic CMOS circuits lie inverter, common source amplifier
differential amplifier, SRAM.
 Perform RTL_GDSII flow and understand the stages in ASIC design.
VLSI Design and Testing Lab/BECL606

Introduction to Cadence

Cadence Design Systems provides tools for different design styles. In this tutorial you will
learn to use three Cadence products: Composer Symbol, Composer Schematic and the
Virtuoso Layout Editor. This tutorial will help you to get started with Cadence and
successfully create symbol, schematic and layout views of an inverter. You will also learn
how to simulate your design using Hspice. The final check will be seeing if your layout
matches your schematic. Figure 1 shows the normal design sequence from design
specifications to final layout simulation. This tutorial will take you through all the steps
(except the last). In addition, there are chapters on Verilog, VHDL, bipolar current mode
logic (CML), standard cells, and auto placement and routing.

Figure 1: Design Process Flow Diagram

The Cadence Development System consists of a bundle of software packages such as

schematic editors, simulators, and layout editors. This software manages the development
process for analog, digital, and mixed-mode circuits. In this course, we will strictly use the tools
associated with analog circuit design. All the Cadence design tools are managed by a software
package called the Design Framework II. This program supervises a common database which
holds all circuit information including schematics, layouts, and simulation data. From the
Design Framework II also known as the "framework", we can invoke a program called the
Library Manager which governs the storage of circuit data. We can access libraries and the
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VLSI Design and Testing Lab/BECL606
components of the libraries called cells. Also, from the framework we can invoke the
schematic entry editor called "Composer". Composer is used to draw circuit diagrams and
draw circuit symbols. A program called "Virtuoso" is used for creating integrated circuit
layouts. The layout is used to create the masks which are used in the integrated circuit
fabrication process. Finally, circuit simulation is handled through an interface called "Analog
Artist." This interface can be used to invoke various simulators including HSPICE, Spectre,
and Verilog. We will be using the SpectreS simulator in this course.

Using the UNIX Operating System:

Using the UNIX operating system is similar to using other operating systems such as DOS.
UNIX commands are issued to the system by typing them in a “shell” or “xterm”. UNIX
commands are case sensitive so be careful when issuing a command, usually they are given in
lower-case. The following list summarizes all the basic commands required to manage the
data files you will be creating in this lab course. All UNIX commands are entered from the
shell or xterm window. Do not use UNIX commands for modifying, deleting, or moving any
Cadence data files.

Common UNIX Commands

ls [–la] Lists files in the current directory. ”l” lists with properties and “a”
also lists hidden files (ones beginning with a “.”).
cd XXXX Changes the current directory to XXXX.
cd .. Changes the current directory back one level.
cp XXXX YYYY Copies the file XXXX to YYYY.
mv XXXX YYYY Move file XXXX to YYYY. Also used for rename
rm XXXX Deletes the file XXXX
mkdir XXXX Creates the directory XXXX.
lp -dXXXX YYYY Prints the textfile or postscript file YYYY to the printer named
XXXX, where XXXX can be either “ipszac” or “hpszac”.
gedit XXXX& Starts the gedit text editor program and loads file XXXX.
top Check available processes and memory usage.
quota –v Check for disk space available

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Digital Design Flow

Procedure for Digital Design Flow

In Desktop Create a folder to do the digital design flow. Right click in the Desktop and select
Create Folder

It will create a folder like below

Name it for example : Asic_Counter

Note : Give folder name without any space

Inside Asic_Counter folder paste your HDL files or Right click in the desktop and select
create document -> empty file

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It will create a text file like below

Name the file Counter.v

Note : File name should be with HDL Extension

Double click the counter.v text file

Inside this text file you can type your HDL Coding

Do the same for the Counter test bench

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save it and it will look like below window

Right click in the same folder and give open in terminal

Invoke the cadence environment by type the below commands

csh
Source /install/cshrc (mention the path of the tools)

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Functional Simulation :
Use the following command to invoke user friendly GUI : nclaunch –new

It will invoke the nclaunch window for functional simulation we can compile, elaborate and
simulate it using Multistep

we can simulate a design using the Incisive simulator.

For that we have to Create the [Link] and [Link] files for to Compile, elaborate and simulate
the design and test bench.

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Click the [Link] file

save the file

choose any of the option listed above

After that give ok

You can see the below window after giving ok

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Left side you can see the HDL [Link] side of the window has worklib and snapshots
directories listed.
Worklib is the directory where all the compiled codes are stored while Snapshot will have
output of elaboration which in turn goes for simulation
Compilation:

left side select the file and in Tools : launch verilog compiler with current selection will get
enable. Click it to compile the code

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Select the test bench and compile it. It will come under worklib. Under Worklib you can see
the module and testbench. Next is to elaborate the design.
Elaboration:

select the file under worklib and in Tools : launch elaborator with current selection will get
enable. select the elaborator to elaborate the design.
Choose the module and test bench and elaborate the design.

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After elaboration the file will come under snapshot. Select the test bench and elaborate it.
Simulation:
Select the testbench file under snapshot and in Tools : Launch simulator with current
selection will get enable.

select simulator to simulate the design. After simulation you will get the two windows like
below image

you will get the two windows Design Browser and Simvision .In design browser you can see
the test bench in left side window.

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VLSI Design and Testing LAB Manual BECL606

select the test bench for the counter and Right click it. Select the send to waveform window
or select the waveform icon
you can see the waveform window after that click the run tool to see the functional simulation
for the counter

The equivalent command terminal output can be observed in the Simvision console window
and also in the nclaunch console terminal.

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 VLSI Design and Testing LAB Manual BECL606

Experiment 1 : 4-Bit Adder

Aim: To write a verilog code for 4bit adder and verify the functionality using Test bench.
• Synthesize, Analyse Reports and Netlist and Max Operating Frequency.
• From the report generated find the total number of cells, power requirement and total
area requirement.

Tool Required:
 Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
 Synthesis: Genus

Design Information and Bock Diagram:

A full adder is a combinational circuit that performs the arithmetic sum of three input bits Ai,
addend Bi and carry in C in from the previous adder. Its results contain the sum Si and the
carry out, C out to the next stage. So to design a 4-bit adder circuit we start by designing the 1
–bit full adder then connecting the four 1-bit full adders to get the 4-bit adder as shown in the
diagram below. For the 1-bit full adder, the design begins by drawing the Truth Table for the
three input and the corresponding output SUM and CARRY.

Fig: Diagram of 4 Bit Adder

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Source Code for full adder:-

module full_adder( A,B,CIN,S,COUT);
input A,B,CIN;
output S,COUT;
assign S = A^B^CIN;
assign COUT = (A&B) | (CIN&(A^B));
endmodule
Source Code – fa_4bit.v :-
module four_bit_adder(A,B,C0,S,C4);
input [3:0] A,[3:0] B,C0;
output [3:0] S,C4;
wire C1,C2,C3;
full_adder fa0 (A[0],B[0],C0,S[0],C1);
full_adder fa1 (A[1],B[1],C1,S[1],C2);
full_adder fa2 (A[2],B[2],C2,S[2],C3);
full_adder fa3 (A[3],B[3],C3,S[3],C4);
endmodule

Source Code for 4-bit full adder:-

module four_bit_adder(A,B,C0,S,C4);
input [3:0] A,[3:0] B,C0;
output [3:0] S,C4;
wire C1,C2,C3;
full_adder fa0 (A[0],B[0],C0,S[0],C1);
full_adder fa1 (A[1],B[1],C1,S[1],C2);
full_adder fa2 (A[2],B[2],C2,S[2],C3);
full_adder fa3 (A[3],B[3],C3,S[3],C4);
endmodule

Test Bench Code for 4-bit full adder:-

module test_4_bit;
reg [3:0] A;
reg [3:0] B;
reg C0;
wire [3:0] S;
wire C4;
four_bit_adder dut(A,B,C0,S,C4);
initial begin
A = 4'b0011;B=4'b0011;C0 = 1'b0; #10;
A = 4'b1011;B=4'b0111;C0 = 1'b1; #10;
A = 4'b1111;B=4'b1111;C0 = 1'b1; #10;
end
initial
#50 $finish;
endmodule

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 VLSI Design and Testing LAB Manual BECL606

Experiment 2: 4-bit Shift and Add Multiplier

Aim: To write a verilog code for 4-bit shift and add multiplier and verify the functionality using test bench
Synthesize, Analyse reports and netlist, critical path and max operating point.
From the generated report, find the total number of cells, power requirement and total area requirement.

Tools required:
 Functional Simulation: Incisive Simulator (ncvlog, nclab, ncsim)
 Synthesis: Genus

Design Information and Flowchart:

Binary multipliers are used for multiplication of 2 binary numbers and are used mainly in signal processing
and also in other computationally intensive applications. Shift and add multipliers is a type of sequential
multiplier. Sequential multipliers generate the partial products sequentially and add each newly generated
partial product to the previously accumulated sum, shift and add binary multiplerr is a type of sequential
multiplier.

Start

B=X; Q=Y; A=0;

N=n
NO B=Y Yes
Q0=1
B=Y
A=A+
B

Shift A Left

Shift B Right

N=N-1

No
N=0

Yes
Stop

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Source Code:
`timescale 1ns/1ps
module shift_and_add_binary_multiplier (clk, rst, A, B, C);
parameter m=4, n=4;
integer i;
input clk, rst;
input [m-1:0] A;
input [n-1:0] B;
output reg [m+n-1:0] c;
reg [m+n-1:0] A1;
reg [n-1:0] B1;
always@(posedge clk or posedge rst)
begin
if (rst)
begin
c=0;
end
else
begin
c=0;
A1[m-1:0]=A;
A1[m+n-1:m]=0;
B1=B;
for(i=0; i<n;i=i+1)
begin
If(B1[i]==1’b0)
begin
c=c+0;
end
else if (B1[i]==1’b1)
begin
c=c+(A1<<i);
end
end
end
end
endmodule

Testbenh

`timescale 1ns/1ps
module shift_and_add_binary_multiplier_tb;
parameter m=4, n=4;
reg clk, rst;
reg [m-1:0] A;
reg [n-1:0] B;
wire [m+n-1:0] c;
shift_and_add_binary_multiplier uut(clk, rst, A, B, C);
initial
begin
clk=1’b1;
forever #4 clk=~clk;
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end
initial
begin
rst=1;
#2 rst=0;
A=4b’1111;
B=4b’1111;
#20 rst 1;
#2 rst=0;
A=4b’0011;
B=4b’0011;
#20 rst 1;
#2 rst=0;
A=4b’1100;
B=4b’0010;
#20
end
Initial
begin
#100 $ finish;
end
endmodule

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 VLSI Design and Testing LAB Manual BECL606

Experiment 3: 32-bit ALU

Aim: Write a verilog code for 32 bit ALU supporting four logical and four arithmetic
operations, use case statement and if statement for ALU behavioral modeling.
• To Verify the Functionality using Test Bench
• Synthesize and compare the results using if and case statements
Tool Required:
 Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
 Synthesis: Genus
Design Information and Bock Diagram:

The ALU will take in two 32-bit values, and control line. An Arithmetic unit does the following task like
addition subtraction, multi-fiction and logical operations. As the input is given in 32 bit we get 32 bit output.
The arithmetic will show only one output at a time so a selector is necessary to select one of the operator.

Source Code – Using Case Statement :

module alu_32bit_case(y,a,b,f);
input [31:0]a;
input [31:0]b;
input [2:0]f;
output reg [31:0]y;
always@(*)
begin
case(f)
3'b000:y=a&b; //AND Operation
3'b001:y=a|b; //OR Operation
3'b010:y=~(a&b); //NAND Operation
3'b011:y=~(a|b); //NOR Operation
3'b010:y=a+b; //Addition
3'b011:y=a-b; //Subtraction
3'b100:y=a*b; //Multiply
default:y=32'bx;
endcase
end
endmodule
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Test Bench :

module alu_32bit_tb_case;
reg [31:0]a;
reg [31:0]b;
reg [2:0]f;
wire [31:0]y;
alu_32bit_case test2(.y(y),.a(a),.b(b),.f(f));
initial
begin
a=32'h00000000;
b=32'hFFFFFFFF;
#10 f=3'b000;
#10 f=3'b001;
#10 f=3'b010;
#10 f=3'b100;
end
initial
#50 $finish;
endmodule

Source Code - Using If Statement :

module alu_32bit_if(y,a,b,f);
input [31:0]a;
input [31:0]b;
input [2:0]f;
output reg [31:0]y;
always@(*)
begin
if(f==3'b000)
y=a&b; //AND Operation
else if (f==3'b001)
y=a|b; //OR Operation
else if (f==3'b010)
y=a+b; //Addition
else if (f==3'b011)
y=a-b; //Subtraction
else if (f==3'b100)
y=a*b; //Multiply
else
y=32'bx;
end
endmodule
Test bench :
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module alu_32bit_tb_if;
reg [31:0]a;
reg [31:0]b;
reg [2:0]f;
wire [31:0]y;
alu_32bit_if test(.y(y),.a(a),.b(b),.f(f));
initial
begin
a=32'h00000000;
b=32'hFFFFFFFF;
#10 f=3'b000;
#10 f=3'b001;
#10 f=3'b010;
#10 f=3'b100;
end
initial
#50 $finish;
endmodule

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 VLSI Design and Testing LAB Manual BECL606

Experiment 4 : Flip Flops

Aim : Write a verilog code for Flip-flops (D, SR, JK), Synthesize the design and compare the
synthesis report.

Tool Required:
 Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
 Synthesis: Genus

Design Information and Bock Diagram:

Latches and flip-flops are the basic elements for storing information. One latch or flip-
flop can store one bit of information. The main difference between latches and flip-flops is that
for latches, their outputs are constantly affected by their inputs as long as the enable signal is
asserted.
In other words, when they are enabled, their content changes immediately when their
inputs change. Flip-flops, on the other hand, have their content change only either at the rising
or falling edge of the enable signal. This enable signal is usually the controlling clock signal.
After the rising or falling edge of the clock, the flip-flop content remains constant even if the
input changes.
There are basically four main types of latches and flip-flops: SR, D, and JK. The major
differences in these flip-flop types are the number of inputs they have and how they change
state. For each type, there are also different variations that enhance their operations.
Example: D-Flip-flop

Fig: Block Diagram and truth table of D-Flip Flop

a) Verilog Codes for D-Flip Flop, JK-Flip Flop and SR-Flip Flop.

Source code for D-Flip Flop :

module DFF( Q, Qbar, D, Clk, Reset);

output reg Q;
output Qbar;
input D,Clk,Reset;

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always @(posedge Clk)

begin
if (Reset == 1'b1) //If at reset
Q <= 1'b0;
else
Q <= D;
end
assign Qbar = ~Q;
endmodule

Source code for SR Flip Flop :

module Main(S, R, clk, Q, Qbar);

input S, R, clk;
output Q, Qbar;
reg M,N;
always @(posedge clk)
begin
M = !(S & clk);
N = !(R & clk);
end

assign Q = !(M & Qbar);

assign Qbar = !(N & Q);
endmodule

Source Code for JK Flip Flop :

module jkff(J, K, clk, Q);

input J, K, clk;
output reg Q,Qm;
always @(posedge clk)
begin
if(J == 1 && K == 0)
Qm = 1;
else if(J == 0 && K == 1)
Qm = 0;
else if(J == 1 && K == 1)
Qm = ~Qm;
end
endmodule

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Experiment 5: Four bit Synchronous MOD-N counter with Asynchronous Reset

Aim: Write a verilog code for 4-bit synchronous MOD-N counter with asynchronous reset, verify the
functionality using test bench and synthesize the design and compare the synthesis report.

Tools Required:
 Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
 Synthesis: Genus

MOD-N Counter
Counters are sequential logic devices that follow a predetermined sequence of counting states triggered by
an external clock (CLK) signal. The number of states or counting or counting sequences through which a
particular counter advances before returning to its original first state is called modulus (MOD). In other
words, the modulus (or modulo) is the number of states the counter counts and is the dividing number of the
counter.
Modulus counters, or MOD counters, are defined based on the number of states that the counter will
sequence before returning to its original value.
The MOD-N counter will require N number of flip flops connected to count a single data bit while
providing 2n different output states.

Source code

module modN_ctr
# (parameter N=10, parameter WIDTH=4)
(input clk, input rstn, output reg [WIDTH-1:0] out);
always @ (posedge clk)
begin
if(!rst)
begin
out <=0;
end
else begin
if (out = = N-1)
out<=0;
else
out<=out +1;
end
end
endmodule

Test bench
module modN_ctr_tb;
parameter N=10;
parameter WIDTH =4;
reg clk;
reg rstn;
wire [WIDTH-1:0] out;
modN_ctr uut (.clk(clk), .rstn(rstn), .out(out));
always #10 clk=~clk;
initial begin
{clk, rstn}<= 0;
$monitor (“T = %0t rstn = %0b out = 0x%0h” =$ time, rstn, out);
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repeat (2) @ (posedge clk);

$finish;
end
endmodule

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Analog Design

General Procedure for Analog Design

1. Initialize the cadence tools:
a. Login as ‘root’.
b. Open a terminal.
c. Navigate to the folder ‘cadence_db’
d. Run commands:
i. csh
ii. source cshrc

2. Change to the course directory by entering this command:

> cd cadence_ms_labs_614
[Note: You will start the Cadence Design Framework II environment from this
directory because it contains [Link], which is the local initialization file. The library
search paths are defined in this file.]

Lab directory details:

. /[Link] Contains a technology library for the design (gpdk 180 nm).

. /models Contains spectre models of components for simulation in gpdk

180nm technology.

. /stream Contains layer map file for GDSII format

. /pv Containing the Assura and Diva verification files

. /techfiles Contains ASCII versions of the oa22 techfiles

. /dig_source Contains verilog codes for SAR register and clock

. /[Link] File containing pointer to the Cadence OA22 initialization file.

. /[Link] File defines the work library for AMS simulation

. /docs Reference manual and user manual for gpdk180nm technology.

3. In the same terminal window, enter:

> virtuoso &

The virtuoso or Command Interpreter Window (CIW) appears at the bottom of the
screen.

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Note: If the “What’s New ...” window appears, close it.

. Keep opened CIW window for the labs.

4. Create a new library
a. In the Library Manager, execute File - New – Library. The new library
form appears.
b. In the “New Library” form, type your .library name in the Name section. In the
field of Directory section, verify that the path to the library is set to
~/cadence_analog_labs_613 and click OK.
Note: A technology file is not required if you are not interested to do the layouts for the design
c. In the next “Technology File for New library” form, select option Attach to
an existing techfile and click OK.

d. In the “Attach Design Library to Technology File” form, select gpdk180

from the cyclic field and click OK.

Note: If the “What’s New ...” window appears, close it.

. Keep opened CIW window for the labs.

5. Create a new library
a. In the Library Manager, execute File - New – Library. The new library

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form appears.
b. In the “New Library” form, type your .library name in the Name section. In the
field of Directory section, verify that the path to the library is set to
~/cadence_analog_labs_613 and click OK.
Note: A technology file is not required if you are not interested to do the layouts for the design
c. In the next “Technology File for New library” form, select option Attach to
an existing techfile and click OK.

d. In the “Attach Design Library to Technology File” form, select gpdk180

from the cyclic field and click OK.

e. Do not edit the Library path file and the one above might be different from
the path shown in your form.
f. Click OK when done the above settings. A blank schematic window for the
Inverter design appears.
6. Add components for the design in concern from libraries available. Edit component
parameters to those specified. Complete the wiring and verify the design connection.
7. Click the Check and Save icon in the schematic editor window.

8. Observe the CIW output area for any errors. If any errors are found make suitable
corrections.
9. Create Symbol for the schematic created and saved. In the created designs schematic
window execute Create — Cellview— From Cellview.
a. The Cellview From Cellview form appears. With the Edit Options
function active, you can control the appearance of the symbol to generate.
b. Verify that the From View Name field is set to schematic, and the
c. To View Name field is set to symbol, with the Tool/Data Type set as

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Schematic Symbol.

d. Click OK in the Cellview From Cellview [Link] Symbol Generation

Form appears.
e. Modify the Pin Specifications as follows:

f. Click OK in the Symbol Generation Options form.

g. A new window displays an automatically created Inverter symbol as shown
here

h. Edit the symbol if required. Save the symbol. After creating symbol, click on
the save icon in the symbol editor window to save the symbol. In the symbol
editor, execute File — Close to close the symbol view window.

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10. Create Test Bench. .

a. In the CIW or Library Manager, execute File— New— Cellview.
b. Set up the New File form as follows:

c. Click OK when done. A blank schematic window for the new design appears.
d. Using the component list and Properties for the simulation given, build the test
bench schematic.
11. Perform Simulation with Spectre. Start the Simulation Environment to run a
simulation.
a. In the schematic window, execute
Launch – ADE L
The Virtuoso Analog Design Environment (ADE) simulation window appears.
b. Choose a [Link] the environment to use the Spectre® tool, a high
speed, highly accurate analog simulator. Use this simulator with the
Inverter_Test design, which is made-up of analog components.
c. In the simulation window (ADE), execute
Setup— Simulator/Directory/Host.
d. In the Choosing Simulator form, set the Simulator field to spectre (Not
spectreS) and click OK.
e. The Model Library file contains the model files that describe the nmos and
pmos devices during simulation. Set the Model Libraries.
In the simulation window (ADE), execute
Setup - Model Libraries.
The Model Library Setup form appears. Click the browse button
to add [Link] if not added by default as shown in the Model Library
Setup form.
Remember to select the section type as stat in front of the [Link] file.
Your Model Library Setup window should now looks like the below figure.

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f. To complete the Model Library Setup, move the cursor and click OK.
The Model Library Setup allows you to include multiple model [Link] also
allows you to use the Edit button to view the model file.
g. Choose the Analyses required for the simulation. In the Simulation window
(ADE), click the Choose - Analyses icon.

[You can also execute Analyses -

Choose]
The Choosing Analysis form appears. This is a dynamic form, the bottom of
the form changes based on the selection above.
h. After setting each analysis Click [Link] all analysis have been set click OK
in the Choosing Analyses Form.
i. Set Design Variables. Set the values of any design variables in the circuit
before simulating. Otherwise, the simulation will not run.

i. In the Simulation window, click the Edit Variables icon. .

[Link] Editing Design Variables form appears.
[Link] Copy From at the bottom of the form.
iv. The design is scanned and all variables found in the design are listed.
v. If any design variable exist they appear in the Table of Design
variables section.
vi. Set the value of the design variable
vii. Click Change and notice the update in the Table of Design Variables.
viii. Click OK or Cancel in the Editing Design Variables window.
j. Select outputs for plotting. Execute Outputs – To be plotted – Select
on Schematic in the simulation window.
k. Select the nets of the voltages to be plotted. If currrents are to be plotte d click
on the Pins where the currets where the currents flow.

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l. The simulation window will look like this.

m. Run the Simulation. Execute Simulation – Netlist and Run in the

simulation window to start the simulation or the icon

This will create the netlist as well as run the simulation.

n. When simulation finishes, the Transient, DC plots automatically will be popped
up along with log file.

12. Create Layout View of the design. From schematic window menu execute Launch
– Layout XL. A Startup Option form appears.
a. Select Create New option. This gives a New Cell View Form
b. Check the Cellname, Viewname (layout). Click OK from the New Cellview
form. LSW and a blank layout window appear along with schematic window.
c. Add components to layout. Execute Connectivity – Generate – All
from Source or click the icon

in the layout editor window, Generate Layout form appears. Click OK which
imports the schematic components in to the Layout window automatically.
d. Re arrange the components within PR-Boundary.
e. Select the design. Activate the connectivity view under
Connectivity-Nets-Show/Hide all incomplete nets
f. Make connections to clear all incomplete nets.
g. Save the design.

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13. Check the Layout using DRC. Execute

Assura-Run DRC
The DRC form appears. The Library and Cellname are taken from the current design
window, but rule file may be missing. Select the Technology as gpdk180. This
automatically loads the rule file.

Your DRC form should appear like this

Click OK to start DRC.

14. A Progress form will appears. You can click on the watch log file to see the log file.
When DRC finishes, a dialog box appears asking you if you want to view your DRC
results, and then click Yes to view the results of this run.
15. If there any DRC error exists in the design View Layer Window (VLW) and Error
Layer Window (ELW) appears. Also the errors highlight in the design itself.
Click View – Summary in the ELW to find the details of errors.
16. If there are no errors in the layout then a dialog box appears with No DRC errors
found written in it, click on close to terminate the DRC run.
17. LVS will perform the check to compare the schematic netlist and the layout netlist. To
Run LVS select Assura – Run LVS from the layout window.
The Assura Run LVS form appears. It will automatically load both the schematic and
layout view of the cell.

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18. Change the following in the form and click OK

19. The LVS begins and a Progress form appears. If the schematic and layout matches
completely, you will get the form displaying Schematic and Layout Match.
20. If the schematic and layout do not matches, a form informs that the LVS completed
successfully and asks if you want to see the results of this run.
Click Yes in the form. LVS debug form appears, and you are directed into LVS
debug environment.
21. In the LVS debug form you can find the details of mismatches and you need to
correct all those mismatches and Re – run the LVS till you will be able to match the
schematic with layout.
22. Assura RCX will extract the RC values from the layout and perform analog circuit
simulation on the designs extracted with RCX.
Before using RCX to extract parasitic devices for simulation, the layout should
match with schematic completely to ensure that all parasites will be backannoted to
the correct schematic nets.
23. To Run RCX , from the layout window execute Assura – Run RCX.
24. Change the following in the Assura parasitic extraction form. Select output type under
Setup tab of the form.
25. In the Extraction tab of the form, choose Extraction type, Cap Coupling Mode and

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specify the Reference node for extraction.

26. In the Filtering tab of the form, Enter Power Nets as vdd!, vss! and Enter
Ground Nets as gnd!

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27. Click OK in the Assura parasitic extraction form when done. The RCX progress
form appears, in the progress form click Watch log file to see the output log file.
28. When RCX completes, a dialog box appears, informs you that Assura RCX
run Completed successfully.
29. You can open the av_extracted view from the library manager and view the parasitic.

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Experiment 6: INVERTER
Objective To implement an inverter schematic, verify its design with a suitable test bench
and generate the layout of the same.

Design

Device Cutoff Non saturation Saturation

Vgsp>Vtp Vgsp<Vtp Vgsp<Vtp
Vin < Vtp+Vdd Vin<Vtp+Vdd
P device
Vin > Vtp+Vdd Vdsp>Vgsp-Vtp Vout> Vdsp<Vgsp-Vtp
Vin-Vtp Vout<Vin-Vtp
Vgsn<Vtn Vgsn>Vtn Vin> Vgsn>Vtn
Vtn Vin>Vtn
N device
Vin<Vtn Vdsn<Vgs-Vtn Vdsn>Vgs-Vtn
Vout<Vin-Vtn Vout>Vin-Vtn

Region Condition P device n device

A 0≤Vin< Vtn Nonsaturation Cutoff

B Vtn≤ Vin<Vdd/2 Nonsaturation Saturation

C Vin=Vdd/2 Saturation Saturation

D Vdd/2<Vin≤Vdd - Vtp| Saturation Non saturation

E Vin>Vdd-|Vtp| Cutoff Non saturation

Fig 1.1 Schematic

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Table 1.1 Symbol Pin Configuration

Pin Names Direction

Vin vdd vss Input

vout Output

Fig 1.2 Sample Symbol

Table 1.2 Test Bench Design Parameters

Library Cellview
Properties/Comment
name name s
USN Inverter Symbol
analogLib Vpulse v1=0, v2=1.8,td=0
tr=tf=1ns, ton=10n,
T=20n
analogLib vdc, gnd vdc=1.8

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Fig 1.3 Test Bench Schematic

Fig 1.4 Analog Simulation with Spectre

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Fig 1.5 Expected Test bench Waveform

Fig 1.6 Expected Layout View

Outcome Student will be able to create the schematic, verify schematic functionality and
device regions of operation by simulation and build the layout for the same in Cadence
Virtuoso.

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Experiment 9: COMMON SOURCE AMPLIFIER

Objective To implement a Common Source amplifier schematic, verify its design with a
suitable test bench and generate the layout of the same.

Design

Fig 3.1a. rc equivent model for Common Source amplifier

Fig 3.1b. Common Source Schematic

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Table 3.1 Common Source Amplifier Device Specifications

Library name Cell Name Properties/Comments

gpdk180 Pmos Model Name = pmos1; W= 50u ; L= 1u

gpdk180 Nmos Model Name =nmos1; W= 10u ; L= 1u

Table 3.2 Pin Direction

Pin Names Direction

vin vbias Input

vout Output

vdd vss Input

Fig 3.2 Common Source Amplifier Test bench design

Table 3.3 Test bench specifications

Library name Cellview name Properties/Comments

USN cs_amplifier Symbol
Define pulse specification as
AC Magnitude= 1; DC
analogLib vsin Voltage= 0; Offset Voltage= 0;
Amplitude= 5m;
Frequency= 1K
analogLib Vdc ( vdd,vss,vbias),gnd vdd=2.5 ; vss= -2.5 vbias= -2.5

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Fig 3.3 Test Bench Schematic for Common Source Amplifier

Fig 3.4 Specifications for Analog Simulation with Spectre

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Fig 3.5 Expected Waveform for Common Source Amplifier

Fig 3.6 Layout view of Common Source Amplifier

Outcome Student will be able to create the schematic, verify schematic functionality and
device regions of operation by simulation and build the layout for the same in Cadence
Virtuoso.

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Experiment 10: OPERATIONAL AMPLIFIER

Objective: To implement an operational amplifier schematic, verify its design with a suitable
testbench and generate the layout of the same.

Design:

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Fig 5.1 Schematic

Table 5.1 Pin Configuration

Pin Names Direction

Idc,Vinv,Vnoninv Input

Vo Output

vdd, vss Input

Fig 5.2 OPAMP Symbol

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Table 5.2 Test Bench Design Parameters

Library name Cellview name Properties/Comments

myDesignLib op-amp Symbol

Define pulse specification as

analogLib vsin AC Magnitude= 1; DC

Voltage= 0; Offset Voltage= 0;
Amplitude= 5m; Frequency=
1K
analogLib vdc, gnd vdd=2.5 ; vss= -2.5

analogLib Idc Dc current = 30u

Figure 5.3 Test Bench Schematic

Fig 5.4 Analog Simulation with Spectre

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Fig 5.5 Expected Test bench Waveform

Fig 5.6 Expected Layout View

Outcome Student will be able to create the schematic, verify schematic functionality and
device regions of operation by simulation and build the layout for the same in Cadence
Virtuoso.

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Demonstration Experiment: UART

Aim: Write a verilog code for UART and carry out the following:
• To Verify the Functionality using test Bench
• Synthesize Design using constraints
• Tabulate Reports using various Constraints
• calculate Max Operating Frequency

Tool Required:
 Functional Simulation: Incisive Simulator (ncvlog, ncelab, ncsim)
 Synthesis: Genus

Design Information and Bock Diagram:

The UART is “Universal Asynchronous Receiver/Transmitter”, and it is an inbuilt IC

within a micro-controller but not like a communication protocol (I2C & SPI). The main
function of UART is to serial data communication. In UART, the communication between two
devices can be done in two ways namely serial data communication and parallel data
communication.
The transmitter section includes three blocks namely transmit hold register, shift register
and also control logic. Likewise, the receiver section includes a receive hold register, shift
register, and control logic. These two sections are commonly provided by a baud-rate-
generator. This generator is used for generating the speed when the transmitter section &
receiver section has to transmit or receive the data.

Fig: UART

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a) Functional Verification using Test Bench

Source Code – Transmitter :
// This code contains the UART Transmitter. This transmitter is able
// to transmit 8 bits of serial data, one start bit, one stop bit,
// and no parity bit. When transmit is complete o_Tx_done will be
// driven high for one clock cycle.
// Set Parameter CLKS_PER_BIT as follows:
// CLKS_PER_BIT = (Frequency of i_Clock)/(Frequency of UART)
// Example: 25 MHz Clock, 115200 baud UART
// (25000000)/(115200) = 217

module UART_TX
#(parameter CLKS_PER_BIT = 217)
(
input i_Clock,
input i_TX_DV,
input [7:0] i_TX_Byte,
output o_TX_Active,
output reg o_TX_Serial,
output o_TX_Done
);
parameter IDLE = 3'b000;
parameter TX_START_BIT = 3'b001;
parameter TX_DATA_BITS = 3'b010;
parameter TX_STOP_BIT = 3'b011;
parameter CLEANUP = 3'b100;
reg [2:0] r_SM_Main = 0;
reg [7:0] r_Clock_Count = 0;
reg [2:0] r_Bit_Index = 0;
reg [7:0] r_TX_Data = 0;
reg r_TX_Done = 0;
reg r_TX_Active = 0;
always @(posedge i_Clock)
begin
case (r_SM_Main)
IDLE :
begin
o_TX_Serial <= 1'b1; // Drive Line High for Idle
r_TX_Done <= 1'b0;
r_Clock_Count <= 0;
r_Bit_Index <= 0;
if (i_TX_DV == 1'b1)
begin
r_TX_Active <= 1'b1;
r_TX_Data <= i_TX_Byte;

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r_SM_Main <= TX_START_BIT;

end
else
r_SM_Main <= IDLE;
end // case: IDLE

// Send out Start Bit. Start bit = 0

TX_START_BIT :
begin
o_TX_Serial <= 1'b0;
// Wait CLKS_PER_BIT-1 clock cycles for start bit to finish
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= TX_START_BIT;
end
else
begin
r_Clock_Count <= 0;
r_SM_Main <= TX_DATA_BITS;
end
end // case: TX_START_BIT

// Wait CLKS_PER_BIT-1 clock cycles for data bits to finish

TX_DATA_BITS :
begin
o_TX_Serial <= r_TX_Data[r_Bit_Index];
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= TX_DATA_BITS;
end
else
begin
r_Clock_Count <= 0;

// Check if we have sent out all bits

if (r_Bit_Index < 7)
begin
r_Bit_Index <= r_Bit_Index + 1;
r_SM_Main <= TX_DATA_BITS;
end
else
begin
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r_Bit_Index <= 0;
r_SM_Main <= TX_STOP_BIT;
end
end
end // case: TX_DATA_BITS

// Send out Stop bit. Stop bit = 1

TX_STOP_BIT :
begin
o_TX_Serial <= 1'b1;
// Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= TX_STOP_BIT;
end
else
begin
r_TX_Done <= 1'b1;
r_Clock_Count <= 0;
r_SM_Main <= CLEANUP;
r_TX_Active <= 1'b0;
end
end // case: TX_STOP_BIT
// Stay here 1 clock
CLEANUP :
begin
r_TX_Done <= 1'b1;
r_SM_Main <= IDLE;
end
default :
r_SM_Main <= IDLE;
endcase
end
assign o_TX_Active = r_TX_Active;
assign o_TX_Done = r_TX_Done;
endmodule

Source Code – Receiver :

// This file contains the UART Receiver. This receiver is able to
// receive 8 bits of serial data, one start bit, one stop bit,
// and no parity bit. When receive is complete o_rx_dv will be
// driven high for one clock cycle.

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// Set Parameter CLKS_PER_BIT as follows:

// CLKS_PER_BIT = (Frequency of i_Clock)/(Frequency of UART)
// Example: 25 MHz Clock, 115200 baud UART
// (25000000)/(115200) = 217
module UART_RX
#(parameter CLKS_PER_BIT = 217)
(
input i_Clock,
input i_RX_Serial,
output o_RX_DV,
output [7:0] o_RX_Byte
);
parameter IDLE = 3'b000;
parameter RX_START_BIT = 3'b001;
parameter RX_DATA_BITS = 3'b010;
parameter RX_STOP_BIT = 3'b011;
parameter CLEANUP = 3'b100;
reg [7:0] r_Clock_Count = 0;
reg [2:0] r_Bit_Index = 0; //8 bits total
reg [7:0] r_RX_Byte = 0;
reg r_RX_DV = 0;
reg [2:0] r_SM_Main = 0;

// Purpose: Control RX state machine

always @(posedge i_Clock)
begin
case (r_SM_Main)
IDLE :
begin
r_RX_DV <= 1'b0;
r_Clock_Count <= 0;
r_Bit_Index <= 0;
if (i_RX_Serial == 1'b0) // Start bit detected
r_SM_Main <= RX_START_BIT;
else
r_SM_Main <= IDLE;
end
// Check middle of start bit to make sure it's still low
RX_START_BIT :
begin
if (r_Clock_Count == (CLKS_PER_BIT-1)/2)
begin
if (i_RX_Serial == 1'b0)
begin
r_Clock_Count <= 0; // reset counter, found the middle
r_SM_Main <= RX_DATA_BITS;
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end
else
r_SM_Main <= IDLE;
end
else
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= RX_START_BIT;
end
end // case: RX_START_BIT
// Wait CLKS_PER_BIT-1 clock cycles to sample serial data
RX_DATA_BITS :
begin
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= RX_DATA_BITS;
end
else
begin
r_Clock_Count <= 0;
r_RX_Byte[r_Bit_Index] <= i_RX_Serial;
// Check if we have received all bits
if (r_Bit_Index < 7)
begin
r_Bit_Index <= r_Bit_Index + 1;
r_SM_Main <= RX_DATA_BITS;
end
else
begin
r_Bit_Index <= 0;
r_SM_Main <= RX_STOP_BIT;
end
end
end // case: RX_DATA_BITS

// Receive Stop bit. Stop bit = 1

RX_STOP_BIT :
begin
// Wait CLKS_PER_BIT-1 clock cycles for Stop bit to finish
if (r_Clock_Count < CLKS_PER_BIT-1)
begin
r_Clock_Count <= r_Clock_Count + 1;
r_SM_Main <= RX_STOP_BIT;
end
else
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begin
r_RX_DV <= 1'b1;
r_Clock_Count <= 0;
r_SM_Main <= CLEANUP;
end
end // case: RX_STOP_BIT
// Stay here 1 clock
CLEANUP :
begin
r_SM_Main <= IDLE;
r_RX_DV <= 1'b0;
end
default :
r_SM_Main <= IDLE;
endcase
end
assign o_RX_DV = r_RX_DV;
assign o_RX_Byte = r_RX_Byte;
endmodule // UART_RX

Test bench :
// This testbench will exercise the UART RX.
// It sends out byte 0x37, and ensures the RX receives it correctly.
`timescale 1ns/10ps
`include "uart_tx.v"
`include "uart_rx.v"
module UART_TB ();
// Testbench uses a 25 MHz clock
// Want to interface to 115200 baud UART
// 25000000 / 115200 = 217 Clocks Per Bit.
parameter c_CLOCK_PERIOD_NS = 40;
parameter c_CLKS_PER_BIT = 217;
parameter c_BIT_PERIOD = 8600;
reg r_Clock = 0;
reg r_TX_DV = 0;
wire w_TX_Active, w_UART_Line;
wire w_TX_Serial;
reg [7:0] r_TX_Byte = 0;
wire [7:0] w_RX_Byte;
UART_RX #(.CLKS_PER_BIT(c_CLKS_PER_BIT)) UART_RX_Inst
(.i_Clock(r_Clock),
.i_RX_Serial(w_UART_Line),
.o_RX_DV(w_RX_DV),
.o_RX_Byte(w_RX_Byte)
);

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UART_TX #(.CLKS_PER_BIT(c_CLKS_PER_BIT)) UART_TX_Inst

(.i_Clock(r_Clock),
.i_TX_DV(r_TX_DV),
.i_TX_Byte(r_TX_Byte),
.o_TX_Active(w_TX_Active),
.o_TX_Serial(w_TX_Serial),
.o_TX_Done()
);
// Keeps the UART Receive input high (default) when
// UART transmitter is not active
assign w_UART_Line = w_TX_Active ? w_TX_Serial : 1'b1;
always
#(c_CLOCK_PERIOD_NS/2) r_Clock <= !r_Clock;
// Main Testing:
initial
begin
// Tell UART to send a command (exercise TX)
@(posedge r_Clock);
@(posedge r_Clock);
r_TX_DV <= 1'b1;
r_TX_Byte <= 8'h3F;
@(posedge r_Clock);
r_TX_DV <= 1'b0;
end
endmodule

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