Department of Electrical Engineering Document Number: Version: 2.
0
SNU/MAN/EHS/EL/003 Effective Date:
12/08/2024
Title: Digital Electronics Lab Manuals (ECE 103) Pages 2
Instructors: Dr. Rakesh Palisetty
Dr. Upendra Kumar Pandey
Dr. Amitabh Chatterjee
Experiment No 6 Combinational Design using Multiplexers and Gates
In this experiment, we will study the design and implementation of two combinational circuits with
incompletely specified functions, using Multiplexers and Gates.
You will use the following ICs for this experiment:
74LS153 Dual 4-input Multiplexer, belonging to the TTL family, and
CD4001 Quad 2-input NOR gate, belonging to the CMOS family.
The pin connections of the 74LS153 IC are given in Fig. 7.1 below. For the Dual 4-input Multiplexer chip,
X0, X1, X2, X3 denote the four data inputs and Q denotes the data output for each multiplexer, the pins
corresponding to the two multiplexers in the same chip being distinguished by a prefix (1 or 2), as
indicated in Fig. 7.1. S1 S0 are the common Select inputs for the two multiplexers, and 1EN’ and 2EN’
are the (negative-logic) output enable inputs for the two multiplexers respectively. The outputs 1Q and
2Q of the two multiplexers are given by the expressions
1Q = 1X0 / 1X1 / 1X2 / 1X3 accordingly as S1 S0 = 00 / 01 / 10 / 11, provided 1EN’ = 0; and
2Q = 2X0 / 2X1 / 2X2 / 2X3 accordingly as S1 S0 = 00 / 01 / 10 / 11, provided 2EN’ = 0.
1Q = 0 if 1EN’ = 1 and 2Q = 0 if 2EN’ = 1, irrespective of the Select and Data inputs.
16 15 14 13 12 11 10 9
VCC 2En’ s0 2X3 2X2 2X1 2X0
2Q
1Q
1En’ s1 1X3 1X2 1X1 1X0 Gnd
1 2 3 4 5 6 7 8
Fig. 7.1 Pin Connections of 74LS153 Dual 4-input Multiplexer
A. Decoder for Encrypted Decimal Digits
Consider a 4-bit code P Q R S to represent decimal digits (value = N) as follows.
For 4 N 0, P Q R S = 13 – N (in decimal), e.g. if N = 2, P Q R S = 1011 and
for 9 N 5, P Q R S = N – 3 (in decimal), e.g. if N = 6, P Q R S = 0011.
A Decoder circuit has to be designed to decode the P Q R S code for decimal digits and generate their
normal BCD (Binary-Coded-Decimal) code. The schematic diagram of the circuit, using four 4-input
multiplexers, is given in Fig. 7.2. P and Q bits will be applied as the common Select bits S1 S0 of the
multiplexers, and the Data inputs of the multiplexers generated out of the remaining two bits R and S
using NOR gates. The decoded output bits D C B A are given by the four multiplexer outputs.
0 X3 0 X3 0 X3 S’ X3
0 X2 R’ X2 R X2 S’ X2
R+S X1 Q D R’S’ X1 Q C R’S’ X1 Q B S’ X1 Q A
0 X0 1 X0 S X0 S’ X0
S1 S0 S1 S0 S1 S0 S1 S0
P
Q
Fig. 7.2 Schematic Diagram for the Decoder for Encrypted Decimal Digit
1. Before coming for the practical class,
(i) Draw the actual circuit diagrams corresponding to Fig. 7.2 in your note-book, including the NOR
gates required for generating the Data inputs of the multiplexers.
(ii) Draw the K-maps for the two problems in your note-book and verify theoretically that the circuits
given in Fig. 7.2 do generate the required outputs as required for the given problems, taking care
of the “don’t care” combinations for the two problems appropriately.
2. Test one of the four 4-input multiplexers out of the two 74LS153 chips by proceeding as follows:
(i) Connect the VCC, Gnd and EN’ pins of the chip to VDC, Gnd and Gnd respectively.
(ii) Apply the 4 possible values of the 2-bit Select input S1 S0 one by one in the binary number
sequence and verify the working the multiplexer as defined in the previous page.
3. Use the four gates in the NOR chip to generate the four different functions of R and S needed as Data
inputs in Fig. 7.2 and assemble the complete circuit given in Fig. 7.2 by connecting these NOR gate
outputs to the multiplexers in the two 74LS153 chips. Connect the inputs P and Q to the common
Select inputs S1 S0 of both the multiplexer chips, and keep all four En’ inputs connected to Gnd.
4. Apply the P Q R S inputs through Input Switches and tabulate the observed output D C B A for all
combinations of P Q R S. Verify that the tabulated results conform to the specified requirements of
the Decoder.
B. Divider for 2-bit Numbers
This circuit is required to perform the division of a 2-bit number N1 N0 by another 2-bit number D1 D0 to
generate a 2-bit Quotient Q1 Q0 and a 2-bit Remainder R1 R0.
The schematic diagram of the circuit, using four 4-input multiplexers, is given in Fig. 7.3. The Dividend
bits N1 and N0 are applied as the common Select bits S1 S0 of the multiplexers, and the Data Inputs of
the four multiplexers are generated out of the Divisor bits D1 and D0 as indicated in Fig. 7.3. The 2-bit
Quotient Q1 Q0 and the 2-bit Remainder R1 R0 are given by the four multiplexer outputs.
1. Before coming for the practical class, repeat step A.1 with reference to Fig. 7.3.
2. Use three gates in the NOR chip to generate the three different functions of D1 and D0 needed as
Data inputs in Fig. 7.3 and assemble the complete circuit given in Fig. 7.3 by connecting these NOR
gate outputs to the multiplexers in the two 74LS153 chips. Connect the inputs N1 and N0 to the
common Select inputs S1 S0 of both the multiplexer chips, and keep all four En’ inputs connected to
Gnd.
3. Apply the N1 N0 D1 D0 inputs through Input Switches and tabulate the observed output Q1 Q0 R1 R0 for
all permissible combinations of N1 N0 D1 D0. Verify that the tabulated results conform to the specified
requirements of the Divider.