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Q1. Write a short note on:
A) Combinational Circuit
A Combinational Circuit is a type of digital logic circuit whose output is solely a function of the
current state of its inputs. It doesn't use any memory element, meaning the output generated at
any instant depends only on the input signals present at that same instant. They don't have
feedback loops, and their operation can be described by Boolean algebra expressions, truth
tables, and logic diagrams.
● Examples include adders (like half and full adders), subtractors, multiplexers,
demultiplexers, encoders, and decoders.
B) Sequential Circuit
A Sequential Circuit is a type of digital logic circuit whose output depends not only on the
present input signals but also on the past sequence of inputs, as its design includes memory
elements. These memory elements (like latches or flip-flops) store the circuit's previous state,
which influences the current output. Sequential circuits require a clock signal for
synchronization in most cases (synchronous circuits).
● Examples include flip-flops, registers, counters, and memory units.
C) Multiplexer
A Multiplexer (MUX), often called a Data Selector, is a combinational circuit that selects one of
many input data lines and directs it to a single output line. The selection is controlled by a set of
select lines (or control inputs). An n-to-1 MUX has n input lines, 1 output line, and \log_2(n)
select lines. It essentially acts like a digitally controlled switch.
● Application: Routing data from multiple sources over a single line, data conversion, and
implementing Boolean functions.
Q2. Half Adder
A Half Adder is a combinational arithmetic circuit that performs the addition of two single-bit
binary numbers (A and B). It has two inputs and two outputs: Sum (S) and Carry-out (C_{out}).
Inputs Outputs
A B
0 0
0 1
1 0
1 1
Logical Expression
From the truth table:
● Sum (S): The output is 1 when inputs are different (like an XOR gate). S = A \oplus B
● Carry (C_{out}): The output is 1 only when both inputs are 1 (like an AND gate). C_{out}
= A \cdot B
Logic Diagram
The Half Adder can be implemented using one XOR gate and one AND gate.
Q3. Full Adder
A Full Adder is a combinational arithmetic circuit that performs the addition of three single-bit
binary numbers: two data bits (\mathbf{A} and \mathbf{B}) and a Carry-in (C_{in}) from a
previous stage. It has two outputs: Sum (S) and Carry-out (C_{out}).
Inputs Outputs
A B C_{in}
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Logical Expression
● Sum (S): The Sum is 1 if an odd number of inputs are 1 (three-input XOR). S = A \oplus B
\oplus C_{in}
● Carry (C_{out}): The Carry is 1 if any two or all three inputs are 1. C_{out} = AB +
AC_{in} + BC_{in}
Logic Diagram
A Full Adder can be constructed by cascading two Half Adders and one OR gate.
Q4. 4-bit Parallel Binary Adder
A 4-bit Parallel Binary Adder is a combinational circuit designed to add two 4-bit binary
numbers simultaneously (in parallel). It is constructed by connecting four Full Adder (FA)
circuits in series, where the carry-out (C_{out}) of each stage is connected to the carry-in
(C_{in}) of the next most significant stage.
● Let the two 4-bit numbers be A = A_3A_2A_1A_0 and B = B_3B_2B_1B_0.
● The circuit produces a 4-bit Sum S = S_3S_2S_1S_0 and a final Carry-out C_{out}.
● The least significant bits (A_0 and B_0) are fed into the first FA, along with an initial
C_{in} (usually 0).
● This structure is called a Ripple-Carry Adder because the carry signal "ripples" from the
least significant bit (LSB) stage to the most significant bit (MSB) stage.
Diagram
The circuit uses four FAs.
Q5. 16:1 MUX
A 16-to-1 Multiplexer (MUX) is a combinational circuit that selects one out of sixteen (2^4)
input data lines and routes it to a single output line.
Block Diagram
● Data Inputs (D_0 to D_{15}): 16 lines carrying the data to be selected.
● Select Lines (S_3, S_2, S_1, S_0): \log_2(16) = 4 control lines that determine which
input is selected.
● Output (Y): The single output line.
Truth Table (Partial)
The output Y is equal to the selected input data line determined by the select lines
S_3S_2S_1S_0.
Select Inputs (S_3S_2S_1S_0) Decimal Equivalent Output (Y)
0000 0 D_0
0001 1 D_1
... ... ...
1110 14 D_{14}
1111 15 D_{15}
Boolean Expression
The output Y is the logical OR of all the input data lines, each ANDed with its corresponding
minterm (the combination of select lines that chooses it).
Logic Circuit Diagram (Conceptual)
The circuit consists of:
1. NOT gates to get the complements of the select lines (\overline{S_3}, \overline{S_2},
\overline{S_1}, \overline{S_0}).
2. Sixteen 5-input AND gates: Each AND gate combines the four select lines (or their
complements, forming a minterm) with one data input line.
3. A single 16-input OR gate: The outputs of all sixteen AND gates are fed into this final OR
gate to produce the single output Y.
Q6. DE-MUX (Demultiplexer)
A Demultiplexer (DE-MUX), often called a Data Distributor, is a combinational circuit that
performs the reverse operation of a multiplexer. It takes a single input data line and switches it
to one of multiple output data lines.
● The selection of the specific output line is controlled by a set of select lines (or control
inputs).
● An 1-to-n DE-MUX has 1 input line, n output lines, and \log_2(n) select lines.
Explanation of 1:8 DE-MUX
A 1-to-8 DE-MUX has:
● 1 Data Input (D).
● 3 Select Lines (S_2, S_1, S_0), since 2^3 = 8.
● 8 Outputs (Y_0 to Y_7).
Block Diagram
Truth Table
The input data \mathbf{D} is routed to the output line Y_i corresponding to the binary value of
the select lines S_2S_1S_0. All other output lines are held at 0.
Select Inputs (S_2S_1S_0) Output Selected
000 Y_0 = D
001 Y_1 = D
010 Y_2 = D
011 Y_3 = D
100 Y_4 = D
101 Y_5 = D
110 Y_6 = D
111 Y_7 = D
Note: Unselected outputs are 0.
Boolean Expression
The output expressions are the product of the data input (D) and the minterm corresponding to
the select lines:
● Y_0 = \overline{S_2}\overline{S_1}\overline{S_0} \cdot D
● Y_1 = \overline{S_2}\overline{S_1}S_0 \cdot D
● ...
● Y_7 = S_2S_1S_0 \cdot D
Logic Circuit Diagram
The circuit uses eight 4-input AND gates. The inputs to each AND gate are the Data Input (D)
and one unique combination of the three select lines (S_2, S_1, S_0) or their complements.
Q7. 7-Segment Decoder with K-Map
A 7-Segment Decoder is a combinational circuit that converts a 4-bit Binary Coded Decimal
(BCD) input (representing the digits 0 through 9) into the appropriate segment drive signals
(\mathbf{a, b, c, d, e, f, g}) for a 7-segment display.
K-Map Derivation (for one segment, e.g., segment 'a')
Let the 4-bit BCD input be \mathbf{I_3I_2I_1I_0}. We want to find the expression for segment
'a', which is ON (logic 1) for the digits 0, 2, 3, 5, 6, 7, 8, 9, and OFF (logic 0) for the digit 1 and
all invalid BCD codes (10 to 15, which are treated as Don't Cares (X)).
Truth Table (for segment 'a')
I_3I_2I_1I_0 Decimal Segment 'a'
0000 0 1
0001 1 0
0010 2 1
0011 3 1
0100 4 0
0101 5 1
0110 6 1
0111 7 1
1000 8 1
1001 9 1
1010-1111 10-15 X (Don't Care)
K-Map for segment 'a'
The 4-variable K-map is filled with 1s, 0s, and Don't Cares (X) according to the table above. By
grouping the largest possible adjacent 1s and Xs, we can derive the minimal SOP expression.
Final Expression for segment 'a'
By simplifying the groups on the K-map, the expression for segment 'a' is:
You would follow a similar process for segments b, c, d, e, f, and g.
Q8. Encoder and Decimal to BCD Encoder
What is an Encoder?
An Encoder is a combinational circuit that converts an active input signal into a coded output
signal, typically in a binary or BCD format.
● It has 2^n (or fewer) input lines and n output lines.
● Only one input line is generally active (high) at any given time.
● The output generates the binary code corresponding to the active input line.
● Limitation: Standard encoders have an issue if two inputs are active simultaneously, or if
the input for code 0 is active (since an output of 00...0 can mean input 0 is active or no
input is active). This leads to the use of Priority Encoders to handle simultaneous inputs.
Decimal to BCD Encoder
A Decimal to BCD (Binary Coded Decimal) Encoder converts a decimal digit input (0 through
9) into its equivalent 4-bit BCD code.
● Inputs: 10 input lines, D_0 through D_9, where only one is active (high) at a time.
● Outputs: 4 output lines, B_3 (MSB), B_2, B_1, B_0 (LSB).
Truth Table (Input D_i is 1, all others are 0)
Input Lines Output BCD (B_3B_2B_1B_0)
D_0 0000
D_1 0001
D_2 0010
D_3 0011
D_4 0100
D_5 0101
D_6 0110
D_7 0111
D_8 1000
D_9 1001
Logical Expressions
The output is formed by ORing the input lines that result in a '1' for that output bit.
● \mathbf{B_0} = D_1 + D_3 + D_5 + D_7 + D_9
○ (LSB is 1 for odd digits)
●
●
●
Q9. Difference between a Latch and a Flip-Flop
Both Latches and Flip-flops are fundamental building blocks of sequential circuits, used to
store a single bit of information (memory). The main difference lies in their method of
synchronization and control.
Feature Latch Flip-Flop
Control/Trigger Level-triggered (Transparent) Edge-triggered
Operation Changes state whenever the Changes state only at the
Enable input is high (or low), rising or falling edge of the
making it asynchronous to a Clock signal, making it
clock edge. synchronous.
Timing/Speed Faster, but prone to timing Slower than latches, but
issues (like race conditions or provides better control and
unwanted state changes). stability for synchronized
systems.
Transparency Transparent—data on the Opaque—data is transferred
Feature Latch Flip-Flop
input is immediately passed to only on the clock edge,
the output when the enable is isolating input from output
active. between edges.
Typical Use As temporary storage As fundamental memory
(registers) or in asynchronous elements in synchronous
circuits (less common in systems (registers, counters,
modern designs). etc.).
Memory Element Can be constructed from basic Is often constructed from two or
gates (e.g., SR Latch). more latches (Master-Slave or
Edge-Triggered).