Democratic and Popular Algerian Republic

Ministry of Higher Education and Scientific Research

Frères Mentouri University - Constantine 1

Faculty of Science and Technology
Department of Electronics

COURS
MASTER 1, Automation and Industrial Computing

Applied Electronics

Produced and presented by:

Dr. Salah ABADLI

Academic Year: 2019 / 2020 (Semester 2)

Academic Year: 2019/2020 Course, Applied Electronics. Presented by Dr. S. ABADLI

Frères Mentouri University - CONSTANTINE 1

Faculty ST Department of Electronics
1
Reminders: the capacitor and the transistor in switching

In general, this course 'applied electronics' will allow the student to discover other
necessary functions of electronics. We are much more interested, in this course, in
the identification of the type and function of such an electronic component in a global system.
The main chapters of this module are:

Reminder on the charging and discharging of a capacitor and the transistor in switching.
The operational amplifier (OA) and circuits based on the OA.
Generation of pulses or signals.
CAN and CNA converters.
Study of active filters.
Introduction to the principles of PCB (Printed Circuit Board) design.

Indeed, the weekly hourly volume of the module is: 1h30 of Lectures, 1h30 of Tutorials.
is a coefficient of 2 (4 credits). The evaluation mode: Continuous Assessment (40%) + Exam (60%).

Charging and discharging of a capacitor

In general, a capacitor consists of two conductive plates, called terminals,
separated by an insulator called dielectric. A capacitor accumulates charges +Q and -Q on
its frames.

Let C be the capacitance of the capacitor to accumulate charges. It depends on the size of the
capacitors, their shape, the thickness of the dielectric,...etc. It is measured in farads (F). The
the relationship between the accumulated charge Q and the voltage across a capacitor is: UC = Q / C.
When the capacitor is charged, the voltage across its terminals is that of the generator which has
allowed to load it.

I-1- Charging a capacitor through a resistor

It is a transitional regime, that is to say a regime that lasts only a short moment.
direct current cannot be established in such a circuit, because the chain of conductors is
interrupted by the dielectric of the capacitor. i
dQ
Knowing that:E U C  U R okay
dt E UC C
UR
dQ Q dQ dU C
UR Ri R and youC C
dt C dt dt R

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dQ dU C dU C
So: UR R RC from where E U C RC
dt dt dt
t

The solution to this equation is:U C E(1 e RC
)
UC(V)

E The charge begin enough

quickly then slows down even more
in addition.

UC= f(t) Note that the product RC =τ. On

generally admits that at the end of
5τ the capacitor is charged.

t (ms)
τ 3τ 5τ
The variation in the intensity of the current flowing through the circuit as a function of time is given by:
t
dQ dU C E 
i C e RC
dt dt R
i(mA)
E/R

i = f(t)

t (ms)
τ 3τ 5τ
The energy stored in the capacitor in the form of electrostatic energy
in the capacitor) depends on its charge (P = UCThe energy stored at the end of a
tempstest :Energie = 0,5 C (UC)2.

I-2- Discharge of a capacitor through a resistor

i
dU C
In this case:0 U C U Rand therefore:0 U C RC
dt UC C
t UR

The solution to this equation is: U C Itsi RC
R

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UC(V)
E

One can notice that the discharge

is practically finished at the end
UC= f(t) of some time constantsτ.

t (ms)
τ 3t 5τ
t
dQ dU C E 
In this situation:i C  e RC
dt dt R
i(mA)

The variation of the current is the same.

shape that for the charge, but it is

negative. In the dump the current
i = f(t)
is contrary to that of the charge.

t (ms)
τ 3 tau 5τ

I-3- Some practical examples of capacitors

In short, capacitors are used in all kinds of electronic circuits. They play a
important role in electronic synchronization circuits, in electronic filters of
frequencies and in signal transmission circuits,...etc.
Filtering: The voltage produced by the full-wave rectification, for example, being quite
away from a smooth direct current. Filtering is used to smooth the rectified current provided by the
rectifier (polarized capacitors are used). These filters serve as storage for
pulses delivered by the rectifier.

470µF / 10 V
Filtering
Straightening

1N4007 +

1N4007

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The upper and lower parts of the output voltage waveform are called the residual voltage; it must be
as low as possible. High-capacity capacitors are used to reduce it.

Capacitive power supply: The capacitance C1,

called "silencer" capacity, plays the role of a

resistance in alternating current. It must be ensured that it

charge and discharge function in each period

sector, hence the interest in the Zener which leads
in both directions. Its advantage is not to
dissipate no heat.
The voltage is quite stable until the maximum current is reached. Then, the power supply
Capacitive works as a "current source," meaning it acts as a current limiter.

Decoupling on a power line: In reality,

the continuous supply voltage is not
rigorously constant due to parasites and
voltage drops created by the consumed currents
through the circuits. By connecting a capacitor between the
power line and the ground, we eliminate these
voltage variations that could disturb the
operation of the assembly.
Depending on the nature of the signals to be eliminated, the appropriate technology will be used for the

capacitor. The variations are often rapid (switching noise for example), one
often calls upon ceramic capacitors. If slow variations are to be stopped (residue
for example, in the case of sector undulation, a higher capacity is required, and then one uses
chemical capacitors. If one wants to eliminate slow or fast variations, one uses a
association formed by a ceramic capacitor and a chemical one as already indicated.

Connection at the entrance of a circuit: It is very often necessary

separate the continuous components that make up the

polarization and the alternative components that
form the useful signal. For the generator that supplies
the useful signal does not change the polarization point, we
placed a coupling capacitor C1at the entrance. The

Direct current cannot pass through a capacitor.

The voltage drop in C1is negligible if:

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II- The switching transistor

II-1- Principle
A transistor is used in switching when its mode of operation is similar to
a switch. In reality, its polarization only allows for two modes of operation by
opposition to operation in linear mode (amplification): blocked or saturated.

Transistor passing: IC 0.
Blocked transistor :IC= 0.
Saturated transistor: VCE 0.

We consider a transistor connected in common emitter configuration, with a biasing through resistance of
base RBA switch can connect the resistance [Link] at the generator E or to the ground.

The equations of the attack and load lines are:

VBE= E [Link]( 0.6 V IB= VBE) / RBand
also VCE E [Link]
We can deduce the position of the point of
operation of the assembly according to the intensity
of direct current. The output voltage is VCE= VS.

In amplifier mode, the operating point is placed in the middle of the line.
charge (point C). The relation IC IBallows to deduce the collector current from the value of the
base current and 0 < VSE.
If the base current is zero, the collector current is zero (IC IB) and VSE (point A). The
transistor is stuck.
If the base current is very high, the collector current is high, but it cannot exceed
the valueICmax= E / RCwhen we grow IBbeyond the valueBmax= E / IB, the
tension VCEbecomes very weak (point B). The base is then saturated (VBC= VBE+ VEC) and the
the transistor is saturated.

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A transistor operates in switching mode when its base current is either very low.
(stuck transistor) can be very intense (saturated transistor). In relation to the generator and the resistor
RCthe saturated transistor behaves like a closed switch and the blocked transistor like a
open switch. In this operation, the power dissipated in the transistor P = [Link]
always weak.
The transistors used in switching are designed so that the switching duration is the
as low as possible.
If the input of the circuit (resistance RB) is connected to E, the output voltage VSis null. If

the input is connected to the mass, VSE.

If we agree to designate by '0' a zero voltage and by '1' a voltage equal to E, we
constate que le montage étudié constitue un inverseur logique.

Note: There are several basic functions of electronics, performed using transistors.
operating in switching mode.

The switching transistor is controlled

by a base current impulse. It shifts from
the blocked state to the saturated state by applying it

a positive current impulse.

II-2- Practical application

The switching transistor will perform the same function as the relay but in a static way.
A weak control energy leads to the transition of a more significant energy.

Circuit
switch
Circuit of
order

Bipolar transistor
MOSFET Transistor

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In short, the switching arrangement of a transistor can be broken down into two circuits:
control circuit (input circuit) and switched or controlled circuit (output circuit).

The switching transistor is used to open or close a circuit. Thus, it can

to command a relay, a motor, etc. The output circuit of the transistor is generally assimilated.
to a switch that is operated either by a voltage or by a current, depending on the type of
chosen transistor.

The relay often allows the power stage to be turned on or off.

higher than the rest of the control electronics. It is therefore preferable to isolate these 2 as much as possible.

floors that coexist just at this level. For this, we will think of components that
isolating the fragile electronic control circuits of the relay (this task is often left to
of opto-couplers).

Switching on inductive load (importance of the freewheeling diode)

We know that inductance opposes a sudden change in current. It is capable of
to store electric charges, which it returns if no source imposes a current on it.
Assuming the switching on an inductive load. When the transistor is turned off, the voltage VL across the

inductance terminals take the value VL = L dI/dt.

Or, d’après la loi des mailles : Vce = Vcc – VL soit Vce = Vcc + [Link]/dt.
As dt is weak, an important surge voltage (several tens of Volts) appears across the terminals.
the transistor. This can lead to its destruction. If nothing is done, the transistor is destroyed, because the
VL is found at the terminals of the transistor (Vce).
To avoid this degradation, resistors are usually placed at the terminals of the load or the transistor.
a protection diode (in reverse and in parallel), known as a freewheeling diode.
When the transistor is saturated: the diode is connected in reverse and does not disturb the
montage.
Lorsque le transistor se bloque : la tension négative en VL rend la diode passante, permettant
thus the evacuation of stored charges in the present resistance (wire of the coil or
of the engine). In fact, the current created by the coil flows in the loop until it disappears. VL
is limited to the threshold voltage of the diode and therefore Vce is limited to Vcc + 0.7 V.

VL VL

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Important note: Each time we order an inductive circuit (inductance, relay,

transformer, motor, etc.) with a switching transistor, it is necessary to place in
in parallel with this one, a diode called a freewheeling diode; allowing the flow of stored charges.
in the inductance during the transistor blocking.

Calculation of the biasing of a switching transistor

The switching transistor is used to solve a problem (therefore it must be
perfectly established). The choice of the type of transistor is made according to the load and the
order. The diagrams that follow are some simple examples of what one can
to do

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The value of the control voltage (Ve), relative to the mass, can be between 1.5
and some 10 V, provided that the value of R2 is adjusted. Assuming that we wish to control
a LED according to the following schematic:

VCC= 12 V, VLED= 1.5 V and ILED= 20 mA, = 100 (hfe)

choose a transistor capable of supporting V and necessary In
Go >
(12 V and 20 mA, which is the transistor 2N2222,…etc.).
We polarize the other components: R1 = (12 - Vce - VLED) /ILED
We calculateBnecessaryBIC/ so: IB= 200 µA
A supersaturation coefficient is applied: IB_Sat=IB0.5 = 1 mA
We calculate the bias resistance of the transistor:
R2 = (12 - VBE) /IB_Sat= 11300
We take a normalized value of the lower resistance to ensure saturation: R2 =
10 k

Control of a relay from a logic signal: This is to control a relay using a

output of a logic circuit (control circuit). The relay cannot be connected directly to
this output, as it consumes too much current. Therefore, a transistor must be used that will serve
of the electrically controlled switch between the control level and the relay.

With classic transistor type 2N2222 With BC517 type Darlington transistor

Darlington Montage
Cde >

With 2 transistors of type 2N2222 and Darlington type TIP122

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The control voltage, coming from an output of a CMOS, TTL, or PIC logic circuit, is
applied to the input Cde. The value of the bias resistor R1 must be adjusted to
to have a base current that is sufficient to properly saturate the
transistor, while not risking burning it out. To calculate the value of R1, it is necessary to know the
gain The transistor used. The freewheeling diode D1 is essential.
If the available control current is less than 1 mA, it is advisable to use a circuit.
Darlington type allowing current amplification. For example, the small Darlington of
BC517 type or the TIP122 Darlington if you need more power.
Indeed, it is still possible to ensure a more effective decoupling (isolation between 2 floors).
by using an opto-isolator for example. It is not uncommon to use a transistor
MOSFET as a switching power element.

Some examples of power MOSFET transistor references.

Exemple:

Data: VCC+12 V and Ve= 0 or 5 V.

Transistor BC547B (NPN) = 200, VCE_sat= 0.2 V ,

VBE_sat= 0.7 V, VCE_max= 45 V.
Relay where Rrel = 310 12 V power supply.
Freewheeling diode 1N4004. This diode is used
only to protect the transistor when it is blocked
(removes the voltage spike caused by the relay).
When Ve= 0, we want the relay not to be
powered, and when Ve = 5 V, we want the relay to be
feed. Determine the theoretical value of R?

When Ve = 0, then VBE= 0 andIB= 0 : the transistor is blocked (ICIE= 0). So the relay is
in open circuit (Urel = Rrel . IC= 0).
When Ve = 5 V, we have VCC= VCEUrel. However, the transistor must be saturated.
So VCE= VCE_satand then VCC= VCE_sat+ Rrel xIC IC= (VCC= VCE_sat) / Rrel
IC(12-0.2)/310 = 0.038 A = 38 mA.
IB_minIC/ = 0.038 / 200 = 0.19 mA. We take a safety factor of 1.5 to be sure.
that the transistor will be well saturated. So: IB_satIB_minx 1.5 = 0.28 mA.

On a: Ve = VBE_sat+ Ur = VBE_sat+ RIB_sat R = (Ve – VBE_sat) /IB_sat=15062Ω= 15 kΩ.

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Frères Mentouri University - CONSTANTINE 1

Faculty ST Department of Electronics
2
The operational amplifier "OPAMP" and circuits based on the OPAMP

In practice, an Operational Amplifier (Op-Amp) is an integrated circuit that allows

to amplify the electric potential difference "e" between the two input voltages Ve+ and Ve-.
It is a differential electronic amplifier. It was initially designed to perform some tasks.
mathematical operations in analog calculators (addition, subtraction, integration,
derivation,...etc.). Subsequently, the AOP is used in many other applications such as the
motor commands, voltage regulation, current sources, oscillators, etc.
Physically, an AOP is made up of transistors or any other components.
amplifiers. The very high voltage gain of an operational amplifier makes it a component used in
wide variety of applications. Indeed, some PDOs are specialized in amplification of
certain types of signals like audio or video signals; due to their characteristics
(rise time and low distortion).

Examples of references: LM741, µA741, TL061, TL071, TL081, TLC271,...etc.

1 : Offset Adjustment
2: Reverse entry
3: Non-inverting input
4: Food (-)
5: Offset Adjustment
6 : Exit
7: Nutrition (+)
8: Not Connected

LM 741

Indeed, the µA741 circuit contains 24 transistors, 11 resistors, and one capacitor.

Practically, all operational amplifiers have the same internal structure. With
some external components, they can perform a wide variety of useful functionalities in
signal processing and signal generation.
An AOP has at least 2 inputs, 2 power pins, and 1 output. The input
The input Ve+ is called non-inverting while the input Ve- is called inverting; due to their
role in the input/output relationships of the amplifier. The potential difference between these two
input is called input differential voltage.

Perfect or ideal AOP:

For a perfect AOP, we adopt:

e
RE , Ie+ Ie- 0 , e = REIe 0
RS 0 , RSIS 0 so VS= A0. e
A0the open loop gain of the AOP.

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Real AOP: Real AOPs have a number of limitations. The real AOP has flaws.

following: non-zero output impedance, non-infinite input impedance, frequency variation

of gain, presence of an offset (shift of the output). In addition, the output voltage can be
influenced by variations in supply voltages and has a fine sweep speed.

The open loop transfer characteristic VS= f(e) :

VS=A0 . e = A0( Ve+ - Ve- )

Zone AB: linear operating domain

VS 15
For example, for VCC+/- 15 V and A0= 200,000 : e 75 µV
A0 200,000
The presence of an infinite differential gain implies that even the slightest difference in potential between the
two entries of the AOP will lead it to saturate.

Conclusion:
Such an assembly is often uncontrollable; because it is too sensitive (very small linear area).
The AOP will almost always be used with a feedback, thus in a closed loop.

A feedback is created by bringing the output to an input. Thus, we work in a loop.

closed. The equivalent circuit diagram of the setup with feedback is as follows:

e = Ve [Link]
VSA0.e
VS= A0( And [Link]) Equivalent of a comparator in
a feedback loop
VS A0
Ve 1 A 0 K

VS
We ask:A V
Ve

AVthe voltage gain of the circuit

Conclusion: SiA0.K >> 1le gain AVno longer depends on A0, but only from the factor K which is
often a report of resistances and therefore perfectly controllable.

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In short, the AOP can work in linear mode (amplifiers, filters, etc.).
in switching mode (comparators, triggers, astables, etc.). To achieve a mode
linear, it is necessary for the circuit to have negative feedback, that is to say a connection between
the output and the input "–" of the AOP. The operation is, however, in switching if the assembly
has a positive feedback, that is to say a connection between the output and the '+' input of the operational amplifier

or if the component is in open loop (neither reaction nor counter-reaction).

For the linear regime, the voltages present at the two inputs of the operational amplifier are

practically equal and we write for the calculations: V+ = V .

For the switching regime, the output voltage can only take two values,
sensibly symmetrical,U ( VSat+)et+U ( VSat), what are the saturation tensions (U
is slightly lower than the supply voltage of the integrated circuit).

Important remarks:
Offset voltage: output offset voltage, due to the internal constitution of the operational amplifier.
Offset voltage adjustment: the adjustment is possible using a mounted potentiometer.
as below.

Connection to the VCC

The currents in the inputs of the op-amp circuit are very low. It is accepted for the calculations.

how useless they are+ =i = 0 ).

I- Different operating setups in linear mode

In general, the basic function (amplifier) and the characteristics of the operational amplifier provide the

possibility to create various important functions, necessary for applied electronics.

Inverting amplifier

One admits the ideal AOP: RE , Ie+ Ie- 0 R2

and e 0
Input mesh: Ve - R1.I1 + e - [Link] = 0 R1

like and 0 andIe+ 0 Ve = R1.I1

Mail out: VS+ R2.I2 + e [Link] = 0
like e 0 andIe+ 0 VS -R2.I2

VS
AV
Ve
 R2 I2  R2  R2
So: AV (car I1 = I2) VS And
R1 I1 R1 R1
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Non-inverting amplifier

We assume the ideal AOP: RE , Ie+ Ie- 0

e 0 andI1 = I2
Input mesh: Ve - [Link] e - R1.I1 = 0
like e 0 andIe+ 0 Ve = R1.I1
Exit email: VS R2.I2 R1.I1 = 0
VS(R1 + R2).I1 = (R1 + R2).I2

VS
AV
Ve
R1 R2
So: AV
R1 R2 AV
R1 R1

If R2 = 0 on a VS= Ve (it is a voltage follower circuit).

Voltage follower

The input resistance of the circuit is infinite.

The voltage follower allows for taking a
e
tension without disturbing it, because it has
a null input current.
We therefore meet him regularly during the
presence of a probe or between two portions of VS= Ve
circuit in such a way as to isolate them from each other.

Non-inverting amplifier: Inverting amplifier:

The amplitude of Vsis greater than that of Vsmaybe it should be:
Vethis is why it is "non-inverting". Amplified: when R1R2
The input resistance of the circuit is infinite. Attenuated: when R1< R2
So the input current is null. The input resistance of the circuit is R1, so
this resistance cannot be very high
report aux others montages you

e previously.

Vs = Ve ( 1 + R2 / R1 ) Vs = Ve (-R2 / R1)

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Differential amplifier

Vs = ( Vp - Vn ) × ( R2 / R1 )

The assembly only performs its function if the resistors indicated in the diagram are
respected. The resistance of each of the two inputs is at least R1(it is not constant).

Summing amplifier or adder

We often need to mix several signals together; the difficulty lies in the fact
that any adjustment interaction of the gains assigned to the different inputs should be avoided.

Vs = V1(-R3 / R1) - V2( R3 / R2 )

If R1 = R2 = R3 then: Vs = - (V+ e
1 V2)

Non-inverting adder with n inputs

Vs = ((R2 + R1) / (n × R1)) × (V1+ V2+ ... + Vn)

From this diagram, we can add as many input voltages as necessary (to
condition to add as many resistors R0. The resistance of each input is at least R.1.

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Inverter integrator

A high-value resistor can

to be placed in parallel with C for e

continuously stabilize the resting point

avoid as well as Vssaturates when Vand=
Ie = 0). We find at the output the integral of the
input signal.
Vs = -1 / (RC) ∫Ve dt

Inverse derivative

The assembly is similar to the previous one and

e
is treated the same way.
La sortie est proportionnelle à la dérivée
from the entrance.

Vs = -RC dVe / dt

Logarithmic and exponential montages

Logarithmic montage Exponential montage

II- Different operating setups in non-linear mode (commutation)

In this case, the AOP is considered perfect, but the output voltage will not be able to take
that two values: Vsat_P(+VSat) and Vsat_N(VSaturday).
Voltage comparator (with a voltage threshold)

In general, it has an output at

open collector, which allows him to
solve the adaptation problem
logical level situated after the
montage.
VEP> VENVs = +VSat
+VsatandVsatare the saturation voltages.
VEP< VENVs = -VSat

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For example: V
VEP

VEN
Weather

VS
+Vsat

Time

Vsat

Non-inverting hysteresis comparator (hysteresis flip-flop or 'Schmitt trigger')

VS
+VSat

V+
V
Ve

According to the mesh 1 :V0+ R1 I = Ve & the mesh 2: Vs = V0–R2 I

VSat
V+ > V Vs = +VSat & V+ < VVs
 = -VSat

If Vs = +VSattipping to–VsatVe ( R1 / R2 ) (VSat) + ( (R1 + R2 ) / R2) V0= VP

If Vs = -VSatbasculement à +VsatVe ( R1 / R2 ) (+VSat) + ( ( R1 + R2 ) / R2) V0= VN
This circuit is called a "Schmitt Trigger." It is a voltage comparator that has two thresholds.
different switching. The voltage on V+ can therefore only be equal to the values: VNand VP.
VHcorresponds to the value of the hysteresis. It corresponds to :VH= VPVN= +2VSat(R1/R2)

V0= 0 → VP= VSat (R1 / R2)

Threshold 1(VP)
V0= 0 → VN=−V Sat (R1 / R2

Example: Threshold 2(VN)

V0 = 0 (GND) & ± VCC+/- 15 V

R1 = 10 k Ω
+ VSat
R2 = 100 k Ω
±VSat± 14 V
VP= + 1.4 V
VN =  1.4 V
 VSat
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Inverter hysteresis comparator (with two voltage thresholds)

VS
+VSat

Ve

V+ V Vs = +VSat
VSat
V+ < VVs
 =VSat

VP = R1/( R1 + R2 ) (+VSat) + R2 / (R1 + R2) V0 VP= VSat R1 / (R1 + R2) siV0= 0

VN= R1 / (R1 + R2 ) (VSat) + R2 / (R1 + R2) V0 VN= VSat R1 / (R1 + R2) siV0= 0

This circuit is also called a 'Schmitt Trigger'. It is a voltage comparator that has
two different tipping thresholds. VHcorresponds to the value of hysteresis. Its value
corresponds to:VH= VPVN= ( R1 / (R1+R2) )×(+VSat(−VSat))

Active low-pass and high-pass filters

III- Notion of gain and bandwidth

Av is the amplification coefficient.
The gain is defined by the formula:

If Av = 100 then: G (dB) = 20 Log 100 = 20 x 2 = 40 dB

The bandwidth is defined by the

frequency at which the gain is reduced
of 3 dB. This frequency Fc is called
cutoff frequency.
The higher the gain, the lower Fc is.

Fc

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Frères Mentouri University - CONSTANTINE 1

Faculty of ST - Department of Electronics
3
Generation of pulses or signals

An astable circuit is an electronic circuit that autonomously generates a signal.

A periodic signal evolving between two stable states. Such a setup is called an astable multivibrator.
An astable circuit can be made in different ways:
Based on an operational amplifier,
Using a NE555 type multivibrator circuit,
Using logic gates associated with passive components.

I- Astable multivibrator with operational amplifier

The astable circuit is implemented using an op-amp wired as a hysteresis comparator (trigger of
Schmitt) associated with an RC cell. The AOP then operates in switching mode (saturated state).
the functional diagram is as follows: R1

Schmitt trigger
We are going to demonstrate that this circuit + Vcc
I
generate a rectangular periodic signal. 
i+
We are going to calculate the frequency of the C +
-Vcc
output signal Vs as a function of R1, R2,
You Vs
R3and C. R2
V3 R3

This circuit has two feedback loops: one negative through the resistor R.1and the
capacitor C, as well as a positive one via a voltage divider. If we only consider the
positive reaction, one can easily recognize an inverter Schmitt trigger. We compare the
tension V+ At the voltage across the capacitor C, there will therefore be a notion of time to take into account.
in account (charging/discharging of C).
The input voltage equations of the operational amplifier are:

R3
V V3 VS
R 2R3

dVc d V
I = -C -C
dt dt
d V
V VS RI
1 = -R1C
dt
d V
VSV R1C
dt

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The voltage V+ is thus produced through the divider bridge, while the voltage V respond to a
first order differential equation (that of a R circuit)1C of 1erorder).

Study of the output signal Vs of the circuit

We remind, first of all, that:

As the AOP operates in switching mode, the output voltage Vs can only take two
valeurs : +Vsatet−Vsat.
The AOP compares the tensions Vc and V.3(You being applied to the entry - of the AOP and V3à
the entry + of the AOP). So we have:
Vc > VVs
3 = -Vsat & Vc < VVs
3 = + Vsat
+
The intensity of the current i being practically zero, the resistances R2 and R3 form a voltage divider
of tension such that:
R3
V3 VS
R 2R3
Or Vs = ±Vsatand therefore the tension V3can take two values corresponding to the two points of
tipping up and down (noted VHand VBof the Schmitt trigger:
R3 R3
V3VH VSat or well V3VB  VSat
R 2 R3 R 2R3
VHand VBare the specific values of Vc for which the voltage Vs undergoes a transition
(bascule).

Charge of the capacitor

It is assumed that at t = 0 Vs = +Vsat
t

VCV VSat(1 - e R1C
) Charging the capacitor C through the resistor R1

Vs

The voltage Vc increases during the charging of the +Vsat

capacitor C.
VH
When Vc reaches and exceeds the value of the
tension VH, on a : Vc > VH, the AOP will shift. The
output voltage is: Vs = -Vsat.

The capacitor stops charging and we will have

so the discharge of the capacitor C. VB

Vsat

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Capacitor discharge
Since Vs = -Vsat the capacitor discharges through the resistor R1.
When it is fully discharged, we always have (Vc = 0) > (V3= VB), the capacitor is
negatively charged and therefore the voltage Vc becomes negative.
When Vc reaches and becomes less than the value VB on a Vc < (VB= V3) the AOP ceases its
discharge. It tilts again and the output voltage Vs is: Vs = +VSat.

The operation subsequently reproduces in a similar manner and the signal Vs is periodic.
The graphical representation of the variations of Vs and Vc over time is as follows:

VCVV SS

+VSat

VH

VB

VSat

Determination of the period T of the output signal

On a T = tC+ tD. Where are youCand tDcorresponding to the charging and discharging durations of the capacitor.
As we mentioned in the first chapter, the expression of the instantaneous value of the
The voltage across a capacitor is given by:
t t
 
VC(t) = Vf( VV
i f)e
R1C
VC(t) = A + B e R1C

With:Viis the initial voltage across the capacitor (at the beginning of the considered instant).
Vfis the final voltage across the capacitor (end of charging or discharging).

Charging time of the capacitor tC

At the beginning of the charging duration tC, the tension VCworth: VC= Vi= VB.
At the end of the charging time tC, the tension VCis worth: VC= Vf= VH.
If the capacitor were to charge completely, the voltage VCworth : VC= Vf= +VSat.

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at t = 0 to VC(0) = Vi VB

at t = ∞ →VC(∞) = VfVSat

At the moment of a full charge tCthe expression becomes:

tC

VC(tC)=VHVSat( VBVSaturday)e R1C

R3 R3
VH VSat and VB  VSaturday
R 2+R3 R 2R3
tC
R3 R3 
VSatVSat( VSatVSat)e R1C
R 2R 3 R 2R3
tC
R3 R3  R 2+2 R
1 + (− -1) e R1C
t CR1C ln 3
R 2R 3 R 2R3 R2

Discharge time of the capacitor tD

at t = 0 → VC(0) = ViVH

at t = ∞ VC(∞) = Vf VSat

At the moment of a complete discharge tDthe expression becomes:

tD

VC(tD)=VB  VSat( VHVSat)e R1C

tD
R3 R3 
 VSat- VSat( VSatVSat)e R1C
R 2R3 R 2R3
tD
R3 R3  R22 R
1 - ( e R1C
t DR1C ln 3
R 2R3 R 2R3 R2
In reality, yC= tDsince the time constant τ = R1It's the same.

Signal period T

R 2+2 R
T=tCtD2 R1C ln 3
R2
If R2= R3we obtain: T = 2 R1C ln 3

Cyclic report of the signal

The cyclic ratio of an astable signal is called the ratio of the duration of the high state of the signal.
over the period T.
In the particular case of R2= R3we obtain: α = ½ (50%).

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II- Astable multivibrator with NE555

The NE555 is a very well-known and very simple integrated circuit. It is a timer in a package.
DIL 8 et qui ne requiert que 3 composants complémentaires (2 résistances et condensateur).

Brooch Description
GND Mass
TRIG Trigger, start the timing. Detect when the voltage is below 1/3 of [Link]
OUT Output signal
RESET Reset, timer interruption
CONT Access to the internal reference (2/3 of VCC)
THRES Trigger the end of the timing when the voltage reaches 2/3 of VCCgoing up
DISCH Terminal for discharging the timing capacitor
VCC Supply voltage, generally between 5 and 15V

The NE555 also exists in a dual version called NE556. It can supply a current
up to 200 mA. Indeed, there are several versions of integrated circuit (bipolar versions:
NA555, SE555, SA555 & CMOS versions: LMC555, ICM7555, ...etc.).

Internal block diagram

The simplified block diagram of the NE555 is:

2 comparators
3 resistors (voltage divider 1/3
VCCand 2/3 VCCserve as references
to the comparators)
1 SET - RESET flip-flop
1 switch
1 timing transistor for
discharge the external capacitor.

Operating in astable mode

The astable configuration allows the NE555 to be used as an oscillator. Two resistors and one
Complementary capacitors allow for modifying the frequency of oscillations as well as
the cyclic report. The arrangement of the components is as shown in the diagram below.
In this configuration, the switch is automatically reset at each cycle, generating
a continuous impulse train as below.

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When powered on, the capacitor C charges through the two resistors Ra.
and Rb of 1/3 VCCat 2/3 VCCMeanwhile, TRIGGER activates the output to a high state.
The capacitor then discharges through the resistance Ra (via pin 7) of 2/3 of
VCCto 1/3 VCCMeanwhile, TRIGGER activates the output to a low state.
Indeed, the first oscillation upon power-up (high state output) is longer than
the following (transition of Vc from 0 V to 2/3 of VCCat the boundaries of C).

2 VCC
3

VCC
3

A complete oscillation occurs when the capacitor charges to 1/3 of [Link] to

2/3 of VCCDuring the charging of C, the resistances R1and R2are in series with the capacitor,
but the discharge occurs through R2only. This is how the cyclical report
may be modified.

The oscillation frequency as well as the duty cycle are determined as follows:
The oscillation period T depends on the charge time tc and the discharge time td:
T = tc + td = ( R1R2) C ln(2) + R2C ln(2) ( R1+2R2) C ln(2)

T ≈ 0.693 ( R1+2R2) C

The cyclic ratio α = tc / T:

R 1R2
R 1+2R2
Note:
It is desirable that R1must be greater than 5 kΩ to limit the current in the transistor
discharge.
1+ R2must be less than 4.3 MΩ so that the current supplied by the inputs is
R
negligible compared to the charge current.

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III- Astable multivibrator with logic gates

Constitution of a MOSFET inverter

A MOSFET inverter consists of two complementary MOS transistors, an N-channel and
a P channel, mounted in common source.

VCC
VCC

VCC/2

If Ve = 0 V → VG1S1= 0 V so T1 is blocked and VD1S1= VCC

VG2S2=−VCC so T2 is saturated and VD2S2= 0 V
therefore Vs = VCC
If Ve = VCC VG1S1= VCC so T1 is saturated and VD1S1= 0 V
VG2S2= 0 V so T2 is blocked and VD2S2=−VCC
therefore Vs = VCC

The function performed is therefore an inversion. If the transistors are strictly identical, we
obtains the transfer characteristic above. The switching occurs for Ve = VCC2.

For TTL logic circuits, the transfer characteristic is as follows:

VH

5V

Astable multivibrator with two inverting gates

G A B

iC

VC

F
The capacitor is initially discharged (Vc = 0) and no current is flowing through it (iC=0).
In this case: VF= VCC, VA= 0 and VB= VCC

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VBVA= VCC
The capacitor C tends to charge under the voltage VCCthrough the resistance R1; the
The potential at point F therefore decreases exponentially.
At the moment t1when VF< VCC/2, VAV-scale CCand VB At 0, this voltage variation of

 VCCis transmitted by the capacitor, so that VF pass to VCC/2-VCC=-VCC/2.

VB VA=  VCC

The capacitor C is tending to charge under the voltage VCCthrough the resistance R1the
The potential at point F therefore grows exponentially.
At the moment t2, when VFVCC/2, VAscale to 0 and VBto VCC, the tension front of VCCis
transmitted by the capacitor, VFpassing then to VCC/2 + VCC= 3 VCC/2.
The capacitor C now tends to charge under the voltage [Link].
VFdecreases until it reaches VCC/2 at the moment t3date of the new switch, start of
next cycle.
You
VCC
2

VCC
2

Vs
VCC

VF
3VCC
2
VCC
VCC
2

VCC
2

Determination of the period T of the output signal

from 0 to t1VBVA= VCC

 t/
Vc(t) = A0+ B0e with : = R1C

OrVc(0) = 0 = A0+ B0e 0/ so: A0=−B0etVc(∞) = VCC= A0B0= -VCC

So: Vc(t) = VCC(1−e t/ )

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of t1to you2VBVA=-VCC
Vc(t) = A1+ B1e (t-t1)/
OrVc(t1) = VCC/2 so: A1=-B1+ VCC/2 etVc(∞) = -VCC= A1→B1= 3VCC/2
So: Vc(t) = -VCC(1-3 e (t-t1)/ / 2)
of t2to you3: VBVA= VCC
Vc(t) = A2+ B2e (t-t2)/
OrVc(t2) = -VCC/2 so: A2-B2VCC/2 etVc(∞) = VCC= A2B2=-3VCC/2
So: Vc(t) = VCC (1 - 3 e (t-t2)/ / 2)

The cyclic ratio being equal to 1/2, t2t1represents a half-period. Let's continue
the expression of Vc(t) between the moments t1and t2and let's write that at the moment t2, Vc is worth : -VCC/2.
Vc(t) = -VCC(1-3 e (t2-t1)/ / 2) = -VCC/2.

So:T=t2t12 R1C ln(3)

Note:

the value of R2must be at least 10 times greater than that of R1Furthermore, the values
of C and of R1must not be too weak, as the inverter 2 cannot provide a current
at very high output.
It is always possible to put a resistance R1variable, which allows for adjustment of the
output frequency of the astable.
It is possible to vary the duty cycle α of the rectangular signal.
A multivibrator can be made using NAND or NOR gates.

Modification of the cyclic report

A potentiometer and two diodes allow for varying the duty cycle.

In this case, the capacitor C charges under the voltage [Link] P1and under-V CC, à
traverse (1-P1).

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3
VCC
2

Indeed, it is possible to improve this circuit by integrating a third logic gate.

T=

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Use of a Schmitt trigger inverter

The transfer characteristic of such a gate (4584, CD4093B,…) and the basic diagram
Here are the chronograms of the astable given below:

VCC

VP

VN

The capacitor, initially uncharged, tends to charge through R under the voltage
exit Vs = VCC, but as soon as Ve > VPat the moment t1, Vs drops to 0 V.
The capacitor discharges until the moment t.2, for which Vc = VN, Vs tilting at
VCCThe capacitor C is recharging again until time t.3where Ve = VP, …etc.

dVC
RC VCVS
dt
of t1to you2, Vs = 0 and therefore: Vc(t) = VPe (t-t1)/  VCC
of t2to you3, Vs = VCCand thus: Vc(t) = VCC+ ( VN– VCC) e (t-t1)/
 (t2-t1)/
The period T = (t3-t2) + (t2t1) with :Vc(t
2) = VPe = VNt2 - t1 = τLn(VP/VN)
Vc(t3VCC+ ( VN– VCC) e (t3-t2)/

VP V V
So:T = R C ln ( ) + R C ln( CC N )
VN (VCCVP)

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IV- Monostable assembly with operational amplifier

This is a setup that has 2 states (one stable state and one unstable state). This one being in the state
stable, a control or trigger pulse changes it from the stable state to the state
unstable. The duration of the unstable state is independent of the shape and intensity of the impulse of
command but depends more on an RC circuit.
The monostable performs a timing function, used whenever one wants to
trigger a device with a delay. Depending on the setups or the timing needs,
The timing can range from a few microseconds to several tens of minutes.

+ Vcc
i

e +
i
+
V0 -Vcc C
i
Vref R
And R2 Vs
R1
V+ VC
Vref

Study of the assembly

Study of the steady state:

At the moment t = t0; at a Ve = 0 → the current i = 0.

V+ = e+ = Vref, Vs = +VSatand Vc = +VSatVref

Study of the unstable state:
At the moment t = t1; Ve = V0(trigger voltage) ; VS=−VSatcar e = Vref−V0< 0

The initial charge of the capacitor is Vc(0) = VSatVref

VrefVCVSat
i=
R 1R2

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VrefVCVSat
V VrefR1i = VrefR1
R 1R2

VrefVSatVrefVSat 2R1VSat
V Vref-R1 Vref 
R 1R2 R 1R2

C
i
R2 Vs = -VSat
R1
V+ VC
Vref

The capacitor will discharge aiming for the value -[Link]. This discharge happens at
through the resistances (R1+ R2), as long as e+ < 0 ; Vs = -VSatla fin de l'état instable correspond
+
to e = 0 (at time t3At that moment:
VrefVCVSat
e  V 0 VrefR1 0
R 1 R2

Vref(RR
1 2)=R1( VrefVCVSat)

R2
VCVref VSat
R1

Study of the recovery phase:

At the moment t = t3, there is a shift and we have: Vs = +VSatThe capacitor C will charge

again to value VSatVref.

C
R2 i
VCVref VSat
R1 R2 Vs = + VSat
R1
VSatVCVref V+ VC
i=
R 1R2 Vref

V VrefR1i

R2
2VSat-Vref Vref
R1
V VrefR1
R 1R2

R2
2VSatVref(1+ )
R1 2R1VSat
V Vref R1
R 1R2 R 1R2

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V- Monostable assembly with NE555

The capacitor charges through R. +VCC

Assuming C is discharged at time t=0.
R
4 8
And 7 3
VCC NE555
6
2
1 5 Vs
C
t
You And
t0 t1t2 t3
GND

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Study of steady state:

At the moment t = t0= 0, the capacitor C is completely discharged, Vc = 0 and Ve = VCC.
Study of the unstable state:
A t = t1We apply a voltage pulse Ve = 0, the capacitor C charges through R.
After the disappearance of the impulse at the moment t = t2we will have Ve = VCCThe unstable state will
end when Vs = 2VCC/ 3.
2
VCVCC(1 -e
 t /RC
) VCC t = [Link](3) ≈ 1.1 R C
3
Thus, the duration of the unstable state is independent of the voltage [Link].
For example, for C = 100µF and R = 1 MΩ, we find t = 110 s.
Study of the recovery phase:
At time t = t3, Vc is slightly above [Link]/3, the capacitor C ends up
in short circuit and therefore discharges quickly and one finds oneself back in the initial state.

The circuit using NE555

is in monostable mode
non-retriggerable.

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VI- Monostable assembly with CMOS logic gates (NOR)

AND, OR, NOR logic gates can be used to create
monostables. Depending on the type of gates used, the wiring may differ slightly.

And
VCC VC
1 RP 1
3 + 3
t 2 2
i
C
And Vs1 R VR Vs

VCC

In the initial steady state, the capacitor C is completely discharged: the current i = 0, Vc = 0.
VR= VCC, Vs = 0 and VS1= VCC.
In the unstable state, at the moment t = t1a positive triggering voltage (VCC) :
Ve = VCC, VS1= 0 , Vc = 0 , VR= 0 , Vs = VCC. VC
3 +
The capacitor C charges, aiming for the value VCC,
with a time constant τ = RC. i
C
 t/ VS1 R
Vc(t) = VCC(1 e) (increasing function). VR

At the moment t≈t2, just before the switch:

VCC
Vc = VR= VCC/ 2.

At the recovery state, at the moment t = t2, there is a new shift:

VC
Vs = 0, VS1= VCC, VR= VCC+ Vc = 3 VCC/ 2.
3 +
The capacitor discharges through the resistor R
i
(with a time constant τ = RC). VCC C
VS1 R
VRdecreases by 3 VCC/ 2 to VCCand we return to the initial state. VR

VCC

If one assumes that the tipping threshold of the doors is close to VCC/ 2, the time required
for the switch can be calculated as follows:
Vc(t) = A+ B e t/
OrVc(0) = 0 so: A = -B and Vc(∞) = VCC= A → B = -VCC
So: Vc(t) = VCC(1 - e t/ )
Vc(t) = VCC(1 - e t/ ) = VCC/ 2.
So, the duration of the unstable state is:
t = [Link](2) ≈ 0.693 × R × C

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And triggering triggering

VCC

t
t1
VS1

stable unstable stable

t
t1 t2 t3 t4
VR
3 VCC
recovery
2
VCC
VCC
2
t
You
VCC
2 recovery

t
Vs
VCC

stable unstable stable

t

Monostable assembly with NAND logic gates

VC
1 1
3 + 3
2 2
C
And Vs1 R VR Vs

In the initial steady state, the capacitor C is completely discharged: Vc = 0, VR= 0 , Vs = VCC
and VS1= 0.
If a pulse arrives, causing level '0' to appear on the input Ve, the voltage at the output of
the first logic gate goes to VCCThis tension front Ve will be found entirely on

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the input of the second logic gate: VRpass to VCCand switches to 0 V, thus allowing
the output at the logical state "0". The output being connected to the first input of the first gate, this
Logical level '0' will generate a memory state, which will keep the output of the first gate at
the logical state '1' (even if Ve changes state).
The capacitor C is charged through the resistor R under the voltage [Link] decreases
until VR< VCC/2 and at that moment Vs switches to VCC(CMOS logic gates).
)  t/ R(t) = VCCe
Vc(t) = VCC(1 e etV t/
(decreasing function).
If we assume that the tipping point of the doors is close to VCC/2, the entrance of the
The second door will therefore show the state "1" as long as VR(t) > VCC/2.
The time required for this can be calculated as follows: VR(t) = VCCe = t/
VCC/ 2
So, the duration of the monostable pulse (the unstable state) is:
t = [Link](2) ≈ 0.693 × R × C

Some Circuits to simulate using PROTEUS ISIS

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Frères Mentouri University - CONSTANTINE 1

Faculty of Science - Department of Electronics
4
Analog/Digital Converter & Converter
Digital/Analog

An electrical signal is the physical representation of the information it carries from its source.
to its recipient. In electronics, a signal most often carries information or
of an order. We distinguish two domains of electrical signals:
domain of analog signals, whose representative magnitude is continuous over time
time can take on an infinite number of different values,
domain of digital signals, whose representative magnitude is a binary value
(0 and 1). Digital signals do not vary continuously.

The transition from one domain to another will be made through converters, mixed components that
will manipulate analog voltages at the input and logical signals at the output or vice versa
The major advantage brought by the digitization of signals is the possibility of storage,
of data transformation and restitution; without them being modified.

Indeed, the digital domain is now predominant. It has developed significantly thanks to
the progress made by microprocessors and programming. Therefore, the processing of
data by programming also introduces flexibility in the design of product-based
of electronics: the same electronic circuit based on a processor will be able to process signals
different; only the program will change. This allows for cost reduction through standardization, the
the same board being used for several different functions. The analog electronics
required at best a change of components, at worst the design of a new board.

But, fundamentally, signals always have an analog nature. They therefore need to be amplified and
eventually extract them from noise signals. The analog domain will therefore always exist
at least upstream of any processing chain. Sometimes, we also need a signal
analog output from this processing chain: it will then be necessary to reconvert the data
digital to analog signal.

There are two categories of converters:

Analog to Digital Converters (ADC or ADC in English, for Analog to Digital)
Converters), which will transform the analog voltages into logical signals suitable to be
processed by microprocessor (digitization of signals).
Digital to Analog Converters (DAC)
Converters) that will convert logical signals into analog voltage.

Note: Several types of converters are available in each category. These types
differ in their precision, their speed of information processing, their price,...etc.

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I- The Analog to Digital Converter (ADC)

The analog-to-digital converter (ADC) is an electronic device (integrated circuit)
allowing to obtain a numerical quantity coded in bits, whose value is
representative of the analog magnitude presented at the input.

VE the analog input voltage.

VRefthe reference voltage. D0
N: the binary numeric value. D1
bits
The sign indicates that the magnitude D2
the input is analog and the sign # D3
indicate that the output is digital.

In fact, when we want to digitize an analog signal (continuous signal), we will need to
discrétiser sur deux dimensions : le temps et l'amplitude. Il est impensable de décrire un signal
with an infinity of values; we will measure it at well-defined moments: that is what we
call the sampling.

As for the amplitude, within a voltage range of the input signal (between 0 V and VRef) on
to match a unique value: this is quantification. This value will then be encoded and
returned in binary form from the converter; to be processed by electronics
digital.

Resolution of a CAN
The term 'resolution' of a DAC or 'step size' or 'Quantum' refers to the smallest
variation in voltage applied at the input that causes a change of 1 LSB (Least Significant Bit)
Bit in English) on the output number N. Therefore, it is the width of a characteristic plateau of
transfer. The smaller the resolution, the more accurate the conversion.
In general, 'Q' is the resolution and 'n' is the number of bits of the converter. We
Express Q as follows: Q = VRef/ (2n The resolution is expressed in Volts.

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The output binary value as a function of the input voltage

The determination of the output binary value based on the input voltage VEtakes place in
three steps :
Voltage division to convert VEby the quantum Q : Nd= VE/ Q,
Elimination of the decimal part of the division result (Ndis a whole decimal number
Conversion of Ndin binary.

Example: A voltage V is applied at the input of an 8-bit ADC.E= 6,326 V ; the voltage of
reference VRef= 10 V. Calculer la résolution Q ? Déterminer en décimal, puis en binaire le résultat
N of the conversion?

A titre d’exemple, la figure suivante montre la fonction de transfert d’un CAN 3 bits. Le
converter issued a finite number of numeric codes, corresponding to a range of
bounded analog input voltage: it is the conversion range of the converter (0-5 V, etc.).
N
111

110

101

100

011

010

001

000

Analog Input Voltage

In this example, the conversion range is 8 V, divided by 23= 8 portions, corresponding

each with a LSB equal to 8V / 8 = 1V.
In fact, to digitize an analog signal, it is necessary to discretize it in both time and amplitude.
The quantification of analog-to-digital conversion results in a small loss of information.

Analog input

Digital release
CAN
VRef

Clock

Note: the dynamics of a signal is the ratio between the maximum voltage and the voltage
minimum that this signal can take.
For an 8-bit ADC, the dynamic range is 256, which can be expressed in dB (20 log(256) = 48 dB).

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Essential characteristics of CAN

In reality, we distinguish two types of DAC, depending on the sign of the input voltage V.E:
Unipolar CAN, when 0 ≤ VEVRef use of 0 V and VRef+
Bipolar CAN, when -VRefVEVRef use of VRef and VRef+

It is necessary to know the range

voltage converted to the input of the ADC.
This beach is defined by both CAN

tension references VRef+ and VRef VE

CAN unipolar CAN bipolar

Binary Excursion Binary Excursion

Decimal Decimal

The excursion (accuracy in English) is the difference between the extreme values of the voltage V.E.
The conversion time or the establishment time TCis the minimum time required to
the converter to stabilize a numerical output after applying a voltage
stable analog input.
The sampling of an analog signal consists of taking samples at regular time intervals.
value of the signal. Each sampling is called a sample and we denote Tethe period
sampling ( S(t) = S(nTeIt is then necessary to keep the sample for the duration of the conversion.
through a blocker.

S(t) : Analog S(nTeSampled SBBlocked

Note: To properly sample a signal, one must adhere to the 'Shannon' theorem.
who says that the sampling frequency of a signal must be greater than or equal to double the
maximum frequency contained in this signal (Fe≥2×FMax).

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Principle of the Sampler / Hold (Sample & Hold)

This circuit, placed at the input of an ADC, has a dual role:
It is a switch controlled by a digital signal of frequency [Link] time
during which this switch is closed, which corresponds to the duration of a sample, must be
negligible compared to the sampling period (Te= 1 / Fe).

E/B

S(t)
S(nTe)
Te #

When the switch K is closed at time t0, the capacitor memorizes 95% of the voltage
analog signal of the input S(t); after a response time [Link]
K, the value S(t0is maintained if the capacitor does not discharge through the circuit
use. For this, it is necessary to have a large follower stage at the output
input impedance.

The sampler / Blocker combines the two previous schemes. The voltage across
C acquires the value of the input analog voltage after a time ta(acquisition time) and
remains at this value for a time th(hold)
Indeed, it is possible to improve this setup to speed up the charging of the capacitor by
a feedback achieved using a second follower circuit.

VE E/B VE

VE You
Logic of VEB t t
order
E/B

The principle of operation is as follows:

Sampling phase: this operation is performed using an electronic switch.
K commanded at the rate of a clock signal with a sampling period of Te.
Maintenance phase: at instant kTethe capacitor C charges with the voltage VE(kTe).
Between the instantkTeand (k+1)T ethe capacitor does not discharge and keeps constant the
tension VEB(t) = VE(kTeThe V signalEB(t) is called a Sampled / Blocked signal.
Phase conversion: at the input of the ADC, the sampled voltage is kept constant.
during the sampling period Te.

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Analog/Digital Conversion Techniques

There are various analog-to-digital conversion techniques:
Simple conversion techniques: parallel ADC (flash), successive approximation ADC.
Integration converters: Single ramp ADC, double ramp ADC, delta-sigma ADC.
Counting converters: digital ramp ADC, tracking ADC, ADC
Tension / Frequency conversion.

The parallel CAN (or flash)

The voltage to measure VEis compared simultaneously to (2N-1) reference tensions; N being
the number of bits of the converter. The number (2N-1) is explained by the concept of full scale (0
is the additional logical state that makes 2Nstates in total for an N-bit converter.

This converter is made up of VRef

following elements:
A reference voltage VRef,
A network of 2Nmounted resistors
in series,
2N 1comparators
A logic decoder.
Decoder
D0
In practice, this arrangement has the disadvantage D1
N D2
of size: it is necessary to (2 -1) comparators for a
N-bit converter, i.e. 63 comparators
for a 6 bits and 255 for an 8 bits. The
The process quickly becomes limiting.

The conversion rate is significantly

higher than MHz, and can reach
hundreds of MHz. VE

The CAN with successive approximations

Ces convertisseurs sont très répondus car performants et bon marché. Le schéma de principe
is given in the figure below. It mainly contains a voltage reference, a
CNA, a comparator and a clock-driven logic sequencer.
The logic sequencer delivers a binary code to the input of the digital converter.
analog (DAC). The output voltage of this DAC is compared to the voltage to be measured VE, and in
Depending on the result, the binary code is modified to approximate the value to be found.
The simplest example of a logical sequencer is a binary counter that increments by one.
unit at each clock tick. All binary codes are successively compared to the
input voltage VE.

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VE

VRef

A more concrete example is given in the figure below (basic principle reduced to 4 bits) of the
ADC_800 and derivatives.

We find a network of resistances of a parallel converter almost similar to that of

the figure above, but each node of this network is connected not to a comparator, but
to a connection switching network (switching-tree).
The voltage V obtained at the summation point S depends on the position of the switches.
controlled by the D bits3D2D1D0of successive approximation records. We therefore have:

VRef VRef VRef VRef

V=VED3 D2 D1 D0
2 4 8 16
At the start of the conversion, only the most significant bit (D3the register of successive approximation is
to "1" and all the other bits being "0".

D3 D2 D1 D0

N bits result of the conversion

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VRef
Thus, at the summation point S, a voltage is obtained.V = VE The comparator
2
then compare the voltage V with 0 Volts:
If the voltage V > 0 ( E>VVRef/ 2 ), then the bit D3is kept at 1, otherwise this bit is discarded to 0.
Then, the successive approximation register sets bit D2 at level 1, the voltage
obtained at the summation point S is V = VE-D3VRef/ 2 -VRefAnd so on...

The CAN with single ramp (pulse counting)

It uses a counter that increments from 0. The outputs of the counter are converted by
a CNA. This internal tension (Vi) est comparée à la tension à convertir VE. As long as Vi< VEthe
the counter increments. It locks as soon as Vireached VE. The result is then available at the exit
of the meter. Indeed, the main advantage of this type of CAN is related to its simple structure.
Nevertheless, it is slow and inaccurate.
VE
The main elements that make it up are:
Ramp generator (integration
of a reference voltage),
2 comparators comparing the ramp
(one at 0 and the other at the voltage at
measure VE),
Various elements of logic (clock,
VRef
counter, door generator
display system.

When the logic commands the start of a measurement, the integrator is reset.
(ramp) and counters. Then, the ramp voltage increases linearly with time.
When the first comparator switches to t0The door allows for pulse counting
delivered by the clock.
When the second comparator toggles, it closes this door, and the value contained in the
counters are locked and transmitted to the displays.

The voltage to be measured is equal to:

VRef
VE (t 1t0)
RC VE

If N is the number of counted pulses, and

F is the clock frequency, we have:
VRef N
VE
RCF

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The dual-rail CAN (pulse counting)

A double ramp Analog-to-Digital converter has the following basic diagram:

VE

VRef

D3D2D1D0

The tension VE, to convert, is

applied to the input of a generator
of the ramp that integrates this tension

during a predetermined time T1.

A meter measures this time, either
N1impulses. Then circuits
of command switches the input
of the ramp generator on a
reference voltage (VRef) of
opposite polarity to the voltage at
convert VEThe voltage at the output of
decorative ramp generator up to
cancel itself. The counter measures the

duration of this decrease, namely N2

clock pulses. The result is
given by the value N2and for
relation :
VRef
N 2N1
VE

The displayed result is directly proportional to the counting, and it is independent of

ramp generator settings, and also the clock frequency. We could compare
this method with double weighing using a scale.

Note: VEand VRefmust be of opposite signs. The advantage of this setup is that it is very
precise, however, it is very slow.

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II- The Digital / Analog Converter (DAC)

The Digital to Analog Converter (DAC) is an electronic circuit that allows obtaining
an output voltage, the value of which is representative of the binary word presented at the input. So, at
for each numerical value, we will match it with an analog value (and only one). The voltage
the output analog will vary by 'jumps or steps' and no longer continuously like the signal
from original (the output voltage will therefore have a staircase shape). In practice, it is necessary to filter this

tension to smooth these discontinuities and try to get as close as possible to the original signal.

To operate, a CNA always requires

D0
a reference voltage VRef. D1
The output voltage Vs cannot be D2
greater in absolute value than VRef. D3

A bipolar CNA requires two voltages.

reference VRef(+)and VRef( ) .
In practice, there is a number
important from CNA, ranging from 4 bits to 64 bits. Example of a 4-bit CNA

Transfer characteristic
The transfer characteristic is the graphical representation of the links between [Link] N.

unipolar CNA bipolar CNA

Resolution of a CNA and conversion range

The resolution of a DAC is the change in output voltage corresponding to the change in a
unit of the binary number input (1 LSB; since it is the smallest possible increment). The
quantum Q, which is the theoretical increment of the analog output voltage VScorresponding to a
The deviation of ±1 LSB at the input is therefore: Q = VRef/ (2n1).

The digital conversion range goes from 0 to (2N-1) ; N being the number of bits of the
converter. Indeed, the term 'full-scale voltage' of a DAC refers to the maximum voltage that it can
take the output. This full-scale voltage is obtained by applying to the input of the DAC the
the highest numerical value (in theory it is equal to VRefbut in reality she is < Vref).

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For example, for a 3-bit CNA and VRef= 8 V : 000 001 010 011 100 101 110 111

D0
D1
D2

This example illustrates what was said earlier about the conversion range: the range
ranges from 0 to 7 V, and not 8 V (VRef), as for the CAN, since the last numerical state is 7.

CNA setting time

This is the time required for the converter, in the best case scenario, to establish the output at
a certain percentage of its final value. This limit restricts the maximum conversion frequency.

Digital/Analog Conversion Techniques

There are mainly two structures of CNA:
Weighted resistor network converters,
R-2R network converters (they are predominant).
The simplified generic architecture, highlighting the common points of all CNAs,
is shown in the figure below. There are 5 blocks:

A digital input buffer: responsible for keeping

in memory the digital data to be converted,
A voltage reference: for the determination
output tensions,
The switching tree: to determine the
resistances that will be powered by the reference,
The network of resistors: to generate
very precise currents based on the binary code,
The current/voltage converter: amplifier.

CNA to weighted resistance network

For this basic structure, weighted resistors are used according to powers of 2.
It is based on an operational amplifier set up as an inverting summation. The following diagram
represents a CNA with 4 inputs.

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Each bit of the binary word to be converted

current flowing through a resistor D3

of weight inversely proportional to

D2
weight of the considered bit. The voltages N R/2
D1
results are added by the
sum amplifier structure. D0
If we apply the result of the amli
VRef VS
inverse consumer can be found:
VRef R D 3 D2 D1 D0
VS  (    )
2 R 2R 4R 8R
VRef D2 D1 D0 VRef VRef VRef VRef
VS  ( D3   ) ( D3 D2 D1 D0 )
2 2 4 8 2 4 8 16
VRef n-1
Generalization: for an input CNA: VS  D i×2i
2n i=0

CNA to R−2R network

This type of converter takes into account the shortcomings of the previous one. It uses a structure in
R2R scale. The reference voltage is distributed across the R2R network.


+
AOP

D3 D2 D1 D0

N
Each bit of the binary word to be converted connects a current either to the ground (DI= 0) either towards

the wired op-amp in summation (Di= 1). We therefore find:

VS−2R(D3I 3D2I 2D1I1D0I 0)

VRef VRef VRef VRef

VS ( D3 D2 D1 D0 )
2 4 8 16
VRef n-1
Generalization: for an input CNA: VS  D i×2i
2n i=0

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Simulation examples: Unipolar sampler

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For Vin = 5V / 800Hz and CLK = 20kHz, we obtain:

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University of Frères Mentouri - CONSTANTINE 1

Faculty ST Department of Electronics
5
Study of active filters

In general, the studied filters consist of passive elements. This means that they are
made using capacitors, coils, and resistors. When they are inserted into
in a circuit, they often cause unwanted signal attenuation. Additionally, during
the use of passive filters, for low frequencies, the value of the inductances is high and
Their dimensions are important. This presents particular problems for integration.

The use of operational amplifiers (OPAMPs) has enabled the development of a new
filter category. These filters are called active filters because the filtering cells (RC cells)
are jointly mounted to an amplifier stage. Indeed, active filters have
identical characteristics to passive filters but have a smaller footprint.

There are several types of active filters, each with specific characteristics.
We will focus more specifically on the most common filters.

I- Transformation of a passive filter into an active filter

When designing a passive filter, the characteristics are defined by the values of
elements and the application of formulas. This principle can also be used with an AOP. By
consequently, the AOP only compensates for losses and mainly adapts the input impedances
output of the filter. In this case, the AOP behaves linearly with frequency, but with a
non-unit gain. The following figure shows an example of a simple first-order passive low-pass filter.
(R-C) and asset mounted with an AOP.

+
R R

C C
And Vs And
Vs
R1
R2

First-order passive R-C filter Active filter

In an amplifier configuration, the voltage gain is determined by the feedback.

For the previous circuit, the feedback is composed of the resistors R1and R2The gain in
The stage voltage is defined by the relationship: AV = 1 + R1/ R2It is a first-order filter and
the cutoff frequency fCis defined by the same formula: fC= 1 / (2πR C).

In an active filter, we sometimes use the operational amplifier by modifying the voltage gain [Link] on
from the frequency (the feedback will be active and realized with a capacitor). In this case, the
gain AVwill vary depending on the frequency and will no longer be fixed as in the previous example.

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The following figure shows a second example of a simple passive bipolar low-pass filter.
(two R cellsC) and active in feedback with an AOP.

C
+
R R R R

C C
And Vs And C
Vs
R1
R2

Simple bipolar passive filter Active filter with 2 poles

Note: The filters we have just seen are low-pass filters, but it is clear that their
The transformation into a high-pass filter is done with the same simplicity as for low-pass filters.

II- Examples of first-order filters

There are a considerable number of different active filters, classified according to the shape of their
transfer function: Bessel filters, Chebyshev filters, Butterworth filters, etc. (from works
integers in their study). We will only examine a few simple examples here.

First order low-pass filterheorder

R2
Let ZCthe complex impedance of the capacitor
and Z the total impedance: C
R2
jCw R2
Z R 2//ZC R1
R 2 (1jC
/ w) 1  j R 2Cw
-
+
The transfer function of the filter is therefore: Ve(t) Vs
Z R2
H(jw)  
R Rj R R C w
R2 1 1 R2 1
H(jw)  A0 with: A0  etw0
R 11  j R 2Cw w R1 R 2C
1 j
w0
1
The cutoff frequency is:f C
2πR2C
Note: We obtain the characteristic transfer function of a low-pass filter of 1er
order, itself multiplied by a gain set by the values R2and R1.

Active high-pass filter of 1erorder

The assembly of the following figure is the combination of a passive high-pass cell R.C
and an op-amp set up as an inverting amplifier.

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First, let's consider the overall impedance Z: R2

1 1 j R C w
Z R Z C R
jCw jCw R C
-
The transfer function is:
+
R2 R
j 2Cw And
H(jw)   Vs
Z 1 j R C w

w
j
w1 1 1
H(jw)  with: w0 etw1
w RC R2C
1 j
w0

Another assembly, the assembly of the following figure, is still the association of a passive cell.
type C high-passR and an AOP set up as a follower.
To obtain the transfer function of this filter, we apply the voltage divider formula.
tension considering the complex impedance ZC, as well as the complex voltages Ve and Vs:

Let ZCthe complex impedance of the capacitor:

1
ZC
jCw
C -
R R
jCw +
Vs You And
1 1 j R C w
R
jCw And R Vs

The transfer function of the filter is therefore:

w
j
Vs w0 1
A(jw) with: w0
And w RC
1 j
w0
1
The cutoff frequency is:f 0
2πR C
Note: The transfer function has the same classic form as a first-order high-pass [Link]
and the cutoff frequency is determined by the values of the passive elements R and C.

This circuit has a maximum gain of 1 (follower circuit), to add a gain

strictly positive to this filter, it is necessary to add two resistors at the feedback loop
reaction. The following setup shows an active filter based on a non-inverting amplifier.
C
We find: +

R1 R
jCw
H(jw) (1 )
R2 1 j R C w And R R1
Vs
R2

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Band-pass filter
In order to simplify the study, we consider that the R
resistances and capacities are equal two by two.
C
Let's consider the resulting impedances from the arrangement.

series and in parallel the elements R and C, noted

respectively Z1and Z2: C R
1 j R Cw -
Z1 R Z C
jCw +
And Vs
R
Z2 R / / ZC
1 j R Cw
Z2 R
jCw
The transfer function of the filter is therefore: H(jw)  
Z1 (1 j R C w ) 2
1 1
H(jw)  with : w0
w w0 RC
2 j 
w0 w

Active all-pass filter of 1erorder: phase shifter

In the assembly of the following figure, one recognizes a cell R.C at the non-inverting input
and a divider bridge at the inverting input: R V R
And Vs
V-
2 -
R V+
1 +
V And And
1 j R C w
C Vs
And Vs And
V V-
2 1 j R Cw
Vs 1 j R C w
G(jw) G 1 G dB 0
And 1 j R C w
Note: The gain of the circuit is zero regardless of the frequency. This circuit has only
function to phase shift the output signal with respect to the input.

II- Examples of second-order filters

Second-order low-pass active filterthSallen and Key Cell

Let the admittances of the elements:
1 C1
Y1 Y2 j C 1w R1 R2
R1
+
1 
Y3 Y4 j C 2w
R2 And C2
Vs
The structure is characterized by:

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Vs Y1 Y3
And ( Y1 Y2Y3 Y4)  Y3(Y4 Y2)
That is to say, we are looking to obtain a normalized transfer function H of the filter form
A
second order bass: H(jw) (m: the amortization factor)
w w 2
1 2 jm (j )
wC wC
By replacing each admittance with its expression in the general equation, we obtain:
1
R 1R2
H(jw)
1 1 1
(  j C 1w) (  j C 2w) (jC2w  j C 1w)
R1 R2 R2
1
H(jw)
1 C 2(R 1 R2) jw R 1R2C1C 2(jw)2

Identification according to the standardized form allows for the identification of:

A 1
1 1
R 1 R 2C 1C 2 wC
wC R 1R2C1C 2

2m C 2(R 1 R2)
C 2(R 1 R2) m
wC 2 R1R2C1C 2

To remedy the unit gain of this setup, it is possible to add a voltage divider in the
negative feedback loop. This is referred to as a Sallen and Key cell with variable gain.
Vs Y1 Y3
KA
And (Y1 Y2)(Y3 Y4)  Y3(Y4 Y2K A) C
R R
With: +
R 1 R2 
KA C
R2 And
Vs
R1
In the same way, we obtain: R2

1
H(jw) KA
1 ( 3 K A) j R Cw (j R Cw)2

Identification with respect to the previous normalized form allows for identifying:
R1  R 2
A KA
R2
1
wC
RC
1 R1 R1
2m 3 m 1
Q R2 2R2

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Second-order high-pass active filterèmeOrder: Sallen and Key Cell

By swapping the two resistors and the two capacitors from the previous setup, we obtain
a high-pass filter (with 2 non-identical poles).
Let the admittances of the elements be: R1
C1 C2
1
Y1 j C 1w Y2
R1 +

1 R2
Y3 j C 2w Y4 And Vs
R2
The structure is characterized by
Vs Y1 Y3
And ( Y1 Y2)(Y3 Y4)  Y3(Y4 Y2)
In the same way as before, we are looking to obtain a normalized transfer function H of
w 2
(j )
wC
the second-order high-pass form: H(jw) A
w w 2
1 2 jm (j )
wC wC
By replacing each admittance with its expression in the general equation, we obtain:
C1C 2( jw)2
H(jw)
1 1 1 1
(jC1w ) (jC2w )  j C 2w( j )
R1 R2 R2 R1

C1C 2R 1R2( jw ) 2
H(jw)
1 R 1( C 1 C 2) jw R 1R2C1C 2(jw)2

The identification of parameters in relation to the normalized form allows for identifying:
A 1
1 1
R 1R 2C 1C 2 wC
wC R 1R2C1C 2

2m R 1( C 1 C 2)
R 1( C 1 C 2) m
wC 2 R1R2C1C 2

In the same way as before, it is possible to add a dividing bridge in the feedback loop.
negative reaction (variable gain).
R 1 R 2 R
A KA C C
R2
+
1
wC 
RC
R
R1 You
Vs
m 1 R1
2R2 R2

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Active band-pass filter 2thSallen and Key Cell

By swapping a capacitor and a resistor in the previous circuit, we obtain a filter.
band-pass (assembly of a low-pass filter followed by a high-pass filter).

In fact, the order of the cells is not

not important. R3
R C
What allows to differentiate the
+
band-pass filters, that's their

quality factor, which corresponds to C R
And Vs
the selectivity of the filter.

In the same way as before, we seek to obtain a normalized transfer function H

w
2 jm
wC
of the second-order band-pass form such that: H(jw) A
w w 2
1 2 jm (j )
wC wC
By using Millman's theorem and substituting the terms, we obtain after simplification:
3R3
R C jw
1 R R 3
H(jw)
3 R3 R3
1 3 R C jw (RC) 2(jw)2
R R 3 R R 3
The identification of parameters according to the normalized form allows for the identification of:

1 1 R3 R 1
A ; (RC) 2 wC (1 )
3 wC R R 3 R3 R C

2m R3 3 R3
3 RC m
wC R R 3 2 R R 3

To change the gain of this circuit, it is possible to add a voltage divider in the loop.
negative feedback (as previously).

Rauch Structure

The structure of Rauch is used for

create active filters of 2thorder. She Y4 Y5
use negative feedback. Y1 Y3

In general, the elements of A B
+
montages are represented by their Y2
And Vs
complex admissions to allow a
easier formatting.

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At node A:I Y1 I Y2 I Y3 I Y4

from where:Y1 ( Ve VA) Y2VA Y3VA Y4( VA VS)

At node B:I Y3 I Y5

Y5
from where:VA  VS
Y3
By replacing VAin the expression of node A, we obtain:
Y5 Y5 Y5 Y5
Y1 ( Ve VS)  Y2 VS Y3 VS Y4( VS VS)
Y3 Y3 Y3 Y3

Y5 Y5 Y4
Y1 ( Ve VS)  VS( Y2 Y3)  VS( Y3 Y5)
Y3 Y3 Y3

Vs Y1 Y3
So: 
And Y3Y4 Y5(Y1 Y2 Y3 Y4)

Second-order low-pass active filterthorder: structure of Rauch

Vs Y1 Y3

And Y3Y4 Y5(Y1 Y2 Y3 Y4)
For the particular case R1= R2= R3= R :
1
H(jw)  R3 C2
1  3jRC2w (j C1C 2wR)2 R1 R2

1
wC
+
R C1C 2
And C1 Vs

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University of Frères Mentouri - CONSTANTINE 1

Faculty ST Department of Electronics
6
Introduction to the principles of printed circuit board (PCB) design

Nowadays, electronics are present in every aspect of our daily activities.

automobiles, mobile phones, computers,... etc. All these applications require
the manufacturing of electronic cards for connecting various components.
An electronic circuit board is a set of components such as resistors, capacitors.
and integrated circuits assembled on a board, so as to form a circuit intended for use
Precise. All electronic cards are made from printed circuit boards, abbreviated as PCB.
Printed Circuit Board.
A printed circuit board or PCB is a support, generally a plate, used to hold and
electrically connecting a set of electronic components together. It is also referred to as
by the term electronic card.

I- Generalities
A printed circuit board consists of an assembly of one or two thin layers of copper.
(single-sided or double-sided) separated by an insulating material. The insulating material of a PCB is
generally made of fiberglass embedded in epoxy. Epoxy is a resin
thermosetting, rigid and insulating.
The copper layers are etched onto the surface of the PCB using a chemical process to achieve
a set of tracks, ending with pads. These conductive tracks are used for
interconnections between the electronic components soldered on the chips.
We talk about 'single-sided' circuits when the copper tracks are only on one side.
face of the board, and 'double-sided' circuits when the copper conductive tracks are found
on both surfaces of the board. Indeed, single-sided and double-sided circuits can be
manufactured without using sophisticated equipment. On the other hand, the production of the cards
Multi-layer complexes (like computer cards) are only possible at the industrial level.

II- PCB Fabrication

Amateur and professional electronics designers create prototypes of simple circuits to
starting from pre-sensitized printed circuit boards. The entire surface of the insulating board is
coated with copper (25 to 75 µm thick) and then with a photoresist under ultraviolet rays
violets (UV). A black plastic film (coating) protects the card from light.

Plastic coating
Photoresin
Thin layer of copper
Epoxy (insulating support)

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To create a printed circuit board, a film (mask, plate, or negative) is used, which is the drawing.
of the printed circuit board (tracks and pads) done on transparent paper. The tracks and pads
are drawn or printed with opaque black ink. The black will protect the resin.
photosensitive against UV rays, during the exposure step. The stencil must be applied on the
pre-sensitized surface before subjecting the circuit to intense UV radiation.

The production of PCBs always goes through the following steps:

Step drawing: used to establish the layout template for the placement circuit of the components, whether it is

manually or by using CAD software (Computer-Aided Design).

Exposure step: used to transfer the drawing onto the plate. The outlines in opaque ink on
the typons prevent UV rays from reaching the photosensitive resin, where the copper will have to
to be preserved. The sun exposure time is generally between 2 minutes and 3 minutes.
Revelation stage (development): a developing liquid will dissolve the resin.
photosensitive that was exposed to UV without altering the resin that remained masked underneath
the opaque ink outline of the typon. The plate is immersed in the developer for 30
seconds to 90 seconds.
Etching step: after rinsing the plate with water, it is immersed in a solution.
chemical (ferrous perchlorate) that will attack and dissolve the copper that is not protected by
the resin. The engraving time is generally between 20 minutes and 1 hour.
Cleaning step: after a new rinse with water, the plate is cleaned to remove the
photosensitive resin that remained on the tracks and copper pads.
Drilling stage: the holes, which will be used for the passage of the component pins for the
welding, are drilled with fairly fine bits (0.6 mm to 1.2 mm).

III- PCB circuit tracing by software

Currently, there are various types of CAD (Computer-Aided Design) software.
dedicated to the tracing of printed circuit boards (PCB). For example, we mention 'ExpressPCB',
Eagle,…etc. which are very simple software. They come with many features allowing
to carry out the implementation of simple or double-sided electronic circuits more quickly.

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The different stages of creating a PCB must be addressed, up to

printing the typon. The following steps are valid regardless of the software used (Proteus for example
of example).

Structural diagram
The first step in creating an electronic circuit board is the input of the structural diagram.
of the electronic circuit. The components are placed using the built-in libraries.

Netlist and routing preparation

Once the schematic is entered, the Netlist must be generated: a list of the components used and their
connections. The generated Netlist is imported into the routing software. As soon as the components
are placed, we obtain what is called 'hairy', where the connections are materialized by
very fine wires directly connecting the "pins" of the components.

Example of hair

To route the electronic circuit board, it is necessary to organize this mess by tracing the tracks, but

some rules must be imposed.

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Note: The spacing between the 'legs' of the electronic components is given in 'pitch' (a
tenth of an inch) or in 'th' (one thousandth of an inch).
1 pouce = 2,54 cm ; 1 pas = 2,54 mm ; 1 th = 25,4µm
Routing
The steps to route a printed circuit board are as follows:
Outline of the map: draw the edge of the map to be created (a working grid of 1 mm
is used in most cases).
Placement of components: the placement of components is crucial, it is this that will
directly influence the routing difficulty of the board. The placement grid is 50th for
traditional components and CMS (Surface Mount Components)
can be placed with a finer grid. Indeed, it is always necessary to place first the
components that have mechanical constraints (specific location, such as
power supply,...etc.) then the placement of other components, grouping them by layer.

Path tracing: The path tracing is done manually, or by using the auto-function.
routing available on most CAD tools. The drawing grid is 25th and
sometimes 12th for certain components.

Note: during the drawing, the width of the

tracks and the distance between the tracks
depend on the currents flowing in the
tracks and the tensions present on them.

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To be continued ....

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