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Microprocessor Instruction Set Overview

The document outlines the architecture and functionality of various registers in a microprocessor, including the Accumulator, General-Purpose Registers, Program Counter, Stack Pointer, and Flag Register. It details instructions for data transfer, arithmetic, logical operations, control transfers, and flag manipulation, along with their effects on the registers and flags. Additionally, it classifies the instruction set into categories such as data transfer, arithmetic, logical, branching, and control instructions.
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0% found this document useful (0 votes)
5 views5 pages

Microprocessor Instruction Set Overview

The document outlines the architecture and functionality of various registers in a microprocessor, including the Accumulator, General-Purpose Registers, Program Counter, Stack Pointer, and Flag Register. It details instructions for data transfer, arithmetic, logical operations, control transfers, and flag manipulation, along with their effects on the registers and flags. Additionally, it classifies the instruction set into categories such as data transfer, arithmetic, logical, branching, and control instructions.
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Registers:

1. Accumulator (A):
8-bit register used for arithmetic, logic, and data transfer operations.
It holds one of the operands and stores the result of an operation.
2. General-Purpose Registers (B, C, D, E, H, L):
Six 8-bit registers, often used in pairs to hold 16-bit data (BC, DE, HL).
→ combinations like BD etc. can't be used

HL Pair: Often used as a memory pointer.


→ MOV A, M = MOV A, [HL]

3. Program Counter (PC):


16-bit register that holds the address of the next instruction to be executed.
Automatically increments after each instruction fetch.

4. Stack Pointer (SP):


16-bit register that points to the top of the stack in memory.
Used during PUSH , POP , CALL , RET
5. Flag Register:
8-bit register that reflects the status of the last arithmetic or logical operation.
Key Flags:
Z (Zero Flag): Set if the result is zero.
S (Sign Flag): Set if the result is negative (i.e., the most significant bit is 1).
P (Parity Flag): Set if the result has an even number of 1s. Checks the A
register
CY (Carry Flag): Set if there is a carry out from the most significant bit in
addition/subtraction.
AC (Auxiliary Carry): Set if there is a carry from bit 3 to bit 4.

Data Transfer Instructions


PUSH: Pushes the contents of a register pair onto the stack. SP-2
PUSH B (pushes BC register pair onto the stack).
POP: Pops the top two bytes from the stack into a register pair. SP+2
POP D (pops top two bytes from the stack into DE register pair).

→ Keep in mind that the PUSH and POP instructions always work on 2 bytes at a time
MVI: Move immediate data to a register or memory location.
`MVI <register/memory>, <8-bit immediate value>``
LDA: Load Accumulator Direct
Registers Affected: Accumulator (A).
LDA 2500H (loads the contents of memory location 0x2500 into the accumulator).
STA: Store Accumulator Direct
STA 2500H (stores A at memory location 0x2500).

Arithmetic Instructions
→ Only work accumulator. All flags affected

ADD: Adds the contents of a specified register or memory to the accumulator.


ADD B (adds the contents of B to A).
ADI: Add immediate to the accumulator.
ADI 0FH (adds 0x0F to A).
ADC: Add with carry to the accumulator.
ADC R/M
SUB: Subtracts the contents of a specified register or memory from the accumulator.
SUB B (subtracts the contents of B from A).
SBI: Subtract immediate from the accumulator with borrow.
SBI 0AH (subtracts 0x0A from A with borrow).

Logical Instructions
ANA: Logical AND with the contents of a register or memory.
Registers Affected: Accumulator (A).
ANA B (ANDs the contents of register B with A).
ANI: Logical AND with immediate data and accumulator.
Registers Affected: Accumulator (A).
ANI 0F0H (ANDs A with 0xF0).
ORA: Logical OR with the contents of a register or memory.
Registers Affected: Accumulator (A).
ORA B (ORs the contents of register B with A).
CMP: Compare accumulator with the contents of a register or memory.
Registers Affected: None.
CMP B (compares A with the contents of register B).
XRI: Exclusive OR immediate data with the accumulator.
Registers Affected: Accumulator (A).
XRI 0FFH (XORs A with 0xFF).
CPI: Compare immediate data with the accumulator.
Registers Affected: None.
CPI 0AH (compares A with 0x0A).
XRA: XRA <reg>/<mem>
A = A ⊕ <reg>/<mem>
INR/DCR:`INR/DCR /

Control Transfer Instructions


JNZ: JNZ 2000H ; memory address
JPO: Jump if Parity Odd; jumps to the specified address if the Parity flag (P) is not set.
Flags Affected: None, but depends on the Parity flag state.
JPO 5000H (jumps to 0x5000 if P = 0).
CALL: Calls a subroutine at the specified address.
Registers Affected: Program Counter (PC) is saved to the stack.
CALL 3000H (calls the subroutine at 0x3000).
RET: Returns from a subroutine.
Registers Affected: Stack Pointer (SP), Programm Counter (PC).
RET (returns from the current subroutine)
RNZ: Return if Not Zero; returns from a subroutine if the Zero flag (Z) is not set.
Registers Affected: Program Counter (PC).
RNZ (returns if Z = 0).
PCHL: Loads the program counter with the contents of HL register pair.
Registers Affected: Program Counter (PC).
PCHL (jumps to the address in HL).

Rotate and Shift Instructions


→ Only work on the accumulator, A

RLC: Rotate accumulator left through carry.


RRC: Rotate accumulator right through carry.

RAR: Rotate accumulator right through carry.

RAL: Rotate accumulator left through carry (without using RLC's MSB).

Flag Manipulation Instructions


STC: Set the Carry flag.
Flags Affected: Carry Flag (CY).
STC (sets CY to 1).
CMC: Complement the Carry flag.
Flags Affected: Carry Flag (CY).
CMC (complements CY).
CMA: Complement the accumulator (inverts all bits).
Registers Affected: Accumulator (A).
Flags Affected: None.
CMA (complements A).

Miscellaneous Instructions
HLT: Halts the microprocessor.
HLT
LXI: Load immediate data into a register pair.
LXI H, 2000H
DAD: Double Add; adds the contents of a register pair to HL.
Registers Affected: HL pair.
Flags Affected: Carry Flag (CY).
DAD B (adds BC to HL).
NOP: NOP (no operation).
DI: Disable Interrupts; disables interrupts.]
Registers Affected: None.
Flags Affected: None.
DI (disables interrupts).
EI: Enable Interrupts; enables interrupts.
Registers Affected: None.
Flags Affected: None.
EI (enables interrupts).

Instruction Set Classification:


1. Data Transfer Instructions: MOV, MVI, LXI, LDA, STA, etc.
2. Arithmetic Instructions: ADD, SUB, INR, DCR, etc.
3. Logical Instructions: ANA, XRA, ORA, CMP, etc.
4. Branching Instructions: JMP, JNZ, JZ, CALL, RET, etc.
5. Control Instructions: NOP, HLT, DI, EI, etc.

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