INTERRUPTS IN 8051
INTERRUPT :
An interrupt is an event that temporarily stops the main
program execution, allowing the microcontroller to respond to
important tasks or events (either from hardware or software
sources).
ISR:
ISR stands for Interrupt Service Routine.
An ISR is a special block of code that is executed in response
to an interrupt event. When an interrupt occurs, the 8051
microcontroller halts its main program, saves the current
context, and jumps to the ISR address for that interrupt.
The execution of an ISR is always concluded with
the RETI (Return from Interrupt) instruction to signal the end
of the service routine.
INTERRUPTS IN 8051:
INTERRUPT VS POLLING:
HARDWARE INTERRUPT:
DEFINITION:
A hardware interrupt in the 8051 microcontroller is an
external event or signal received on specific interrupt pins
(such as INT0 on P3.2 or INT1 on P3.3) that causes the
microcontroller to temporarily halt its current program
execution and jump to a special Interrupt Service Routine
(ISR) to respond to that event.
Hardware interrupts can operate in two modes:
level-triggered
edge-triggered
ACTIVATION ON INT0, INT1:
LEVEL-TRIGGERED INTERRUPT:
DEFINITION:
In the level-triggered mode, the interrupt is activated and held
active as long as the external interrupt pin is kept low.
OPERATION:
When the external interrupt pin (P3.2 for INT0 or P3.3 for
INT1) is held low, the 8051 recognizes it as an interrupt
request.
The interrupt flag (IE0 or IE1) is set.
The 8051 jumps to the corresponding Interrupt Service
Routine (ISR).
After executing the ISR and returning (RETI), if the pin is still
low, the interrupt will be repeated.
EDGE-TRIGGERED INTERRUPT:
DEFINITION:
In the edge-triggered mode, the interrupt is activated by a
falling edge signal (high-to-low transition) on the external
interrupt pin.
OPERATION:
The interrupt occurs only once when the signal transitions
from 1 → 0 (falling edge).
By default, INT0 and INT1 are level-triggered (low-level
active) after reset.
To make them edge-triggered, set bits IT0 (TCON.0) and IT1
(TCON.2) in the TCON register.
SETB TCON.0 ; Makes INT0 edge-triggered
SETB TCON.2 ; Makes INT1 edge-triggered
TCON REGISTER :
EXAMPLES BASED ON THE HARDWARE INTERRUPT:
1) Assume that the INT1 pin is connected to a switch that
is normally high. Whenever it goes low, it should turn on
an LED. The LED is connected to P1.3 and is normally off.
When it is turned on it should stay on for a fraction of a
second. As long as the switch is pressed low, the LED
should stay on.
ANSWER:
BLOCK DIAGRAM:
CODE:
ORG 0000H
LJMP MAIN ; bypass interrupt vector table
ORG 0013H ; INT1 ISR
SETB P1.3 ; turn on LED
MOV R3, #255 ; load counter
BACK: DJNZ R3, BACK ; keep LED on for a while
CLR P1.3 ; turn off the LED
RETI ; return from ISR
ORG 30H
MAIN: MOV IE, #1000100B ; enable external INT1
HERE: SJMP HERE ; stay here until interrupted
END
2) Assuming that pin 3.3 (INT1) is connected to a pulse
generator, write a program in which the falling edge of the
pulse will send a high to P1.3, which is connected to an
LED (or buzzer). In other words, the LED is turned on
and off at the same rate as the pulses are applied to the
INT1 pin.
ANSWER:
BLOCK DIAGRAM:
CODE:
ORG 0000H
LJMP MAIN ; bypass interrupt vectortable
ORG 0013H ; INT1 ISR
SETB P1.3 ; turn on the LED
MOV R3, #255
BACK: DJNZ R3,BACK ; keep the LED on for while
CLR P1.3 ; turn off the LED
RETI ; return from ISR
ORG 30H
MAIN: SETB TCON.2 ; make INT1 edge-trigger interrupt
MOV IE,#1000100B ; enable External INT1
HERE: SJMP HERE ; stay here until interrupted
END
TIMER INTERRUPT:
DEFINITON:
A timer interrupt occurs when a hardware timer (Timer0 or
Timer1) in the 8051 overflows.
On overflow the timer set its overflow flag (TF0 or TF1) and,
if enabled, the CPU vectors to the corresponding Interrupt
Service Routine (ISR).
GENERATING TIMER INTERRUPT:
Timer 0 → overflow flag TF0, interrupt vector at 000BH.
Timer 1 → overflow flag TF1, interrupt vector at 001BH.
Enable bits in the IE register:
• ET0 (enable Timer0 interrupt)
• ET1 (enable Timer1 interrupt)
Priority bits in IP: PT0 and PT1
EXAMPLES ON TIMER INTERRUPT:
1) Write a program to generate a square wave of 50 Hz
frequency on pin P1.2 , it uses an interrupt for Timer
0. Assume that XTA = 11.0592 MHz.
ANSWER:
BLOCK DIAGRAM:
CODE:
ORG 0000H
LJMP MAIN
ORG 000BH ; ISR for Timer 0
CPL P1.2 ; complement P1.2
MOV TLO, #00 ; reload timer values
MOV TH0, #0DCH
RETI
ORG 30H ;starting location for prog.
MAIN: MOV TMOD, #00000001B ;Timer 0, Mode 1
MOV TLO, #00
MOV TH0, #0DCH
MOV IE, #82H ; enable Timer 0 interrupt
SETB TRO ; start timer
HERE: SJMP HERE ; stay here until interrupted
END
2) Write a program that continuously gets 8-bit data from
P0 and sends it to P1 while simultaneously creating a
square wave of 200 μs period on pin P2.1. Use Timer 0 to
create the square wave. Assume that XTAL = 11.0592
MHz.
ANSWER:
Use Timer 0 in mode 2 (auto-reload)
Calculate TH0 value: 100/1.085 μs = 92
CODE:
ORG 0000H
LJMP MAIN
ORG 000BH
CPL P2.1
RETI
ORG 0030H
MAIN: MOV TMOD,#02H
MOV P0,#0FFH
MOV TH0,#-92
MOV IE,#82H
SETB TR0
BACK: MOV A,P0
MOV P1,A
SJMP BACK
END
3) Create a square wave that has a high portion of 1085 μs
and a low portion of 15 μs. Assume XTAL = 11.0592 MHz.
Use Timer 1.
CODE:
ORG 0000H
LJMP MAIN
ORG 001BH
LJMP ISR_T1
ORG 0030H
MAIN: MOV TMOD,#10H
MOV P0,#0FFH
MOV TL1,#018H
MOV TH1,#0FCH
MOV IE,#88H
SETB TR1
BACK: MOV A,P0
MOV P1,A
SJMP BACK
ISR_T1: CLR TR1
HERE: DJNZ R2,HERE
MOV TL1,#18H
MOV TH1,#0FCH
SETB TR1
SETB P2.1
RETI
END
SERIAL COMMUNICATION INTERRUPT:
DEFINITION:
A Serial Communication Interrupt in the 8051 microcontroller
is an event generated by the Serial Port (UART) hardware to
signal the CPU that a serial data transaction has completed.
OPERATIONS:
Enabling: The serial interrupt must be enabled by setting bit
ES (Enable Serial Interrupt, bit 4) in the IE (Interrupt Enable)
register.
Triggering: When the 8051 finishes receiving a byte (RI=1)
or finishes transmitting a byte (TI=1), the serial interrupt is
requested.
ISR Execution: The CPU jumps to the Serial Interrupt
Service Routine (ISR) at address 0023H.
Flag Checking & Clearing: Inside the ISR, the program
must check the SCON register to determine which flag (RI or
TI) caused the interrupt.
For reception (RI), the program reads the received data
from the SBUF register and then must clear the RI flag by
software (CLR RI).
For transmission (TI), the program can load the next byte
into SBUF for continuous transmission and then must clear
the TI flag by software (CLR TI).
SINGLE INTERRUPT FOR BOTH TI AND RI:
IE REGISTER:
EXAMPLES ON SERIAL COMMUNICATION
INTERRUPT:
1) Write a program in which the 8051 reads data from P1
and writes it to P2 continuously while giving a copy of it to
the serial COM port to be transferred serially. Assume
that XTAL = 11.0592 MHz. Set the baud rate at 9600.
ANSWER:
CODE:
ORG 0000H
LJMP MAIN
ORG 23H
LJMP SERIAL ; jump to serial interrupt ISR
ORG 30H
MAIN: MOV P1,#0FFH ; make P1 an input port
MOV TMOD,#20H ; timer 1, mode 2
MOV TH1,#0FDH ; 9600 baud rate
MOV SCON,#50H
MOV IE,#10010000B ; enable serial interrupt
SETB TR1 ; start timer 1
BACK: MOV A,P1 ; read data from port 1
MOV SBUF,A ; give a copy to SBUF
MOV P2,A ; send it to P2
SJMP BACK ; stay in loop indefinitely
;---------------------Serial Port ISR
ORG 100H
SERIAL: JB TI,TRANS ; jump if TI is high
MOV A,SBUF ; otherwise due to receive
CLR RI ; clear RI since CPU does not
RETI ; return from ISR
TRANS: CLR TI ; clear TI since CPU does not
RETI ; return from ISR
END
2) Write a program using interrupts to do the following:
(a) Receive data serially and send it to P0,
(b) Have port P1 read and transmitted serially, and a copy
given P2,
(c) Make Timer 0 generate a square wave of 5 kHz
frequency on P0.1. Assume that XTAL = 11.0592 MHz. Set
the baud rate at 4800.
ORG 0000H
LJMP MAIN
ORG 000BH
CPL P0.1
RETI
ORG 23H
LJMP SERIAL
ORG 30H
MAIN: MOV P1,#0FFH
MOV TMOD,#22H
MOV TH1,#0F6H
MOV TH0,#-92
MOV SCON,#50H
MOV IE,#10010010B
SETB TR1
SETB TR0
BACK: MOV A,P1
MOV SBUF,A
MOV P2,A
SJMP BACK
;---------------------SERIAL PORT ISR
ORG 100H
SERIAL: JB TI,TRANS
MOV A,SBUF
MOV P0,A
CLR RI
RETI
TRANS: CLR TI
RETI
PART – A QUESTIONS :
1. Compare polling and interrupts. How is a microcontroller
perform upon activation of interrupt?
2. What is the function of RETI instruction?
3. What is a hardware interrupt? Give two examples.
4. What is a software interrupt?
5. List all the interrupt sources in 8051.
6. What is the purpose of IE (Interrupt Enable) register in
8051?
7. What is the role of IP (Interrupt Priority) register in 8051?
8. Define interrupt latency.
9. What is an edge-triggered interrupt vs level-triggered
interrupt?
10. What is the function of RETI instruction?
11. Which external pins are used for external interrupts in
8051?
12. What is interrupt vector address in 8051?
13. How are interrupt priorities assigned in 8051?
14. Mention the registers involved in interrupt control in
8051.
15. When is an interrupt generated? Explain the interrupt
handling mechanism.
16. Which SFRs (Special Function Registers) are involved in
interrupt control in 8051?
17. Which are the flags bits used in 8051 for timer and serial
interrupts?
18. What are the flags bits used in 8051 for serial interrupts?
19. What is interrupt nesting?
20. How is timer overflow used to generate a timer interrupt?
21. What is the difference between maskable & non-maskable
interrupts?
PART-B:
PART – B
INTERRUPTS
1. Explain the interrupt architecture of 8051 microcontroller,
with neat diagram and vector addresses. (May/June – 2023)
2. Describe the IE and IP registers used for interrupt enable
and priority in 8051. Give bit format and explain each bit.
(Nov/Dec – 2023)
3. With neat diagram, explain how the 8051 handles multiple
interrupts and the sequence of interrupt execution.
4. Write a short note on interrupt priority and nesting
mechanism in 8051.
5. Compare polling vs interrupt-driven I/O in an embedded
system.
H/W INTERRUPTS
6. Explain the process of handling external hardware
interrupts in 8051.
7. Write an 8051 assembly language program to toggle an
LED connected to a port pin when a logical 0 is detected at
external interrupt INT0.
8. Describe edge-triggered and level-triggered modes for
external interrupt.
TIMER INTERRUPTS
9. Describe how to generate a square wave of a specific
frequency using a timer interrupt. Include the necessary
register settings.
SERIAL INTERRUPTS
10. Explain the serial communication interrupt mechanism in
8051, detailing the roles of SCON, SBUF registers and the TI
/ RI flags.
11. Write a program to transmit the message “WELCOME”
serially using interrupts.
12. Write a program to receive 10 bytes of serial data and
store them in memory using interrupts.