Digital System Design using Verilog Semester 3
Course Code BEC302 CIE Marks 50
Teaching Hours/Week (L:T:P: S) [Link] SEE Marks 50
Total Hours of Pedagogy 40 hours Theory + 8-10 Lab slots Total Marks 100
Credits 04 Exam Hours 03
Examination nature (SEE) Theory/Practical
Course objectives:
This course will enable students to:
To impart the concepts of simplifying Boolean expression using K-map techniques and Quine-
McCluskey minimization techniques.
To impart the concepts of designing and analyzing combinational logic circuits.
To impart design methods and analysis of sequential logic circuits.
To impart the concepts of Verilog HDL-data flow and behavioural models for the design of digital
systems.
Teaching-Learning Process (General Instructions)
These are sample Strategies, which teacher can use to accelerate the attainment of the various course
outcomes.
Lecture method (L) does not mean only traditional lecture method, but different type of
teaching methods may be adopted to develop the outcomes.
Show Video/animation films to explain the different concepts of Linear Algebra & Signal
Processing.
Encourage collaborative (Group) Learning in the class.
Ask at least three HOTS (Higher order Thinking)questions in the class, which promotes
critical thinking.
Adopt Problem Based Learning (PBL), which fosters students’ Analytical skills, develop
thinking skills such as the ability to evaluate, generalize, and analyze information rather than
simply recall it.
Topics will be introduced in a multiple representation.
Show the different ways to solve the same problem and encourage the students to come up
with their own creative ways to solve them.
Discuss how every concept can be applied to the real world-and when that's possible, it
helps improve the students' understanding.
Adopt Flipped class technique by sharing the materials/Sample Videos prior to the class and
have discussions on the topic in the succeeding classes.
Give Programming Assignments.
MODULE-1
Principles of Combinational Logic: Definition of combinational logic, Canonical forms,
Generation of switching equations from truth tables, Karnaugh maps-up to 4 variables, Quine-
McCluskey Minimization
Technique. Quine-McCluskey using Don’t CareTerms.(Section3.1to3.5ofText1).
MODULE-2
Logic Design with MSI Components and Programmable Logic Devices: Binary Adders and
Subtractors, Comparators, Decoders, Encoders, Multiplexers, Programmable Logic Devices(PLDs)
(Section5.1to5.7 ofText2)
MODULE-3
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Flip-Flops and its Applications: The Master-Slave Flip-flops(Pulse-Triggered flip-flops):SR flip-
flops, JK flip flops, Characteristic equations, Registers, Binary Ripple Counters, Synchronous
Binary Counters, Counters based on Shift Registers, Design of Synchronous mod-n Counter using
clocked T, J K, D and SR flip-flops.(Section 6.4, 6.6 to 6.9 (Excluding 6.9.3)of Text2)
MODULE-4
Introduction to Verilog: Structure of Verilog module, Operators, Data Types, Styles of
Description. (Section1.1to1.6.2, 1.6.4 (only Verilog),2 of Text 3)
Verilog Data flow description: Highlights of Data flow description, Structure of Data flow
description.(Section2.1to2.2(only Verilog) of Text3)
MODULE-5
Verilog Behavioral description: Structure, Variable Assignment Statement, Sequential
Statements, Loop Statements, Verilog Behavioral Description of Multiplexers (2:1, 4:1, 8:1).
(Section 3.1 to 3.4 (onlyVerilog)of Text 3)
Verilog Structural description: Highlights of Structural description, Organization of structural
description, Structural description of ripple carry adder.(Section4.1 to 4.2 of Text 3)
PRACTICAL COMPONENT OF IPCC (Experiments can be conducted either using any circuit simulation
software or discrete components)
Sl.N Experiments
1 To simplify the given Boolean expressions and realize using Verilog program
2 To realize Adder/Subtractor(Full/half)circuits using Verilog data flow description.
3 To realize 4-bit ALU using Verilog program.
4 To realize the following Code converters using Verilog Behavioral description
a)Gray to binary and vice versa b)Binary to excess3 and vice versa
5 To realize using Verilog Behavioral description:8:1mux, 8:3encoder, Priority encoder
6 To realize using Verilog Behavioral description:1:8Demux, 3:8 decoder,2 –bit Comparator
7 To realize using Verilog Behavioral description:
Flip-flops: a)JK type b)SR type c)T type and d)D type
8 To realize Counters-up/down (BCD and binary)using Verilog Behavioral description.
Demonstration Experiments (For CIE only–not to be included for SEE)
Use FPGA/CPLD kits for down loading Verilog codes and check the output for interfacing
experiments.
9 Verilog Program to interface a Stepper motor to the FPGA/CPLD and rotate the motor
in the specified direction (by N steps).
10 Verilog programs to interface Switches and LEDs to the FPGA/CPLD and demonstrate
its working.
Course outcomes (Course Skill Set):
At the end of the course the student will be able to:
1. Simplify Boolean functions using K-map and Quine-McCluskey minimization technique.
2. Analyze and design for combinational logic circuits.
3. Analyze the concepts of Flip Flops(SR, D,T and JK) and to design the synchronous sequential
circuits using Flip Flops.
4. Model Combinational circuits (adders, subtractors, multiplexers) and sequential circuits using
Verilog descriptions.
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