Chapter Two

Computer Organization

By: Abebe B

1
2 Outline

✓ Architecture of 8086
✓ Address and a Data bus
✓ Features of 8086
✓ Register Organization
✓ Instruction Set of 8086
✓ Addressing Modes

By: Abebe B
Address bus and a Data bus in a
microprocessor 8086?
By Abebe B.
 MICROPROCESSOR

• The microprocessor is nothing but a CPU (Central Procession

Unit) on a Chip.
• The Central Processing Unit can do only do Processing. i.e.
CPU knows how to do things. But it does not know what to
do.
• The Microprocessor accepts commands from outside and
performs the operations.
• Since Microprocessor does not have memory and does not
know what to do, it depends on External Memory of giving
Instructions about what to do. Also, it uses external Memory to
store and read the data.
 MICROPROCESSOR

• The Microprocessor does the following 4 Major

Operations.
[Link] the Instructions from Memory. (Instruction Fetch)
[Link] (Write) the data into Memory. (Data Write)
[Link] (Read) the data from Memory. (Data Read)
[Link] instructions.
• The first 3 operations are performed by the
Microprocessor with the help of External memory.
So, the Microprocessor needs to be connected with
the Memory.
• Since, these wires are used to address a particular location in Memory we
call these wires ADDRESS WIRES. Groups wires are called BUS, so we
call these lines ADDRESS BUS.
 DATA BUS AND ADDRESS BUS ?

• The data bus carries the data to be stored, while address bus
carries the location to where it should be stored.
1) Address Bus :
• Address bus is a part of the computer system bus that is
dedicated for specifying a physical address.
• Data bus is bidirectional, while address bus is
unidirectional.
2) Data Bus : A data bus simply carries data.
• Typically, the same data bus is used for both read/write
operations.
▪ Now Let Us Consider Microprocessor And Memory Are Connected
With 1 Wire.
Then The Microprocessor Can Put 0V Or 5V On That Wire. So, The
Microprocessor Access 2 Locations In Memory.
▪ If We Connect 2 Wires Between Microprocessor And
Memory, Then We Can Access 4 Locations Of Memory.
• If We Connect 3 Wires Between Microprocessor And
Memory, Then We Can Access 8 Locations Of Memory.
▪ If We Connect 4 Wires Between Microprocessor And
Memory, Then We Can Access 16 Locations Of Memory.
▪ If We Connect 8 Wires Between Microprocessor And
Memory, Then We Can Access 256 Locations Of
Memory.
▪ If We Connect 16 Wires Between Microprocessor And
Memory, Then We Can Access 65536 Locations Of
Memory.
• The same we connect wires from Memory to Microprocessor to
receive the DATA.
• That group of wires is called DATA BUS.
• Address Bus has located the specific location in Memory.
• Data Bus is used to Read or Write Data from Memory.
• The RD and WR signals are used by the Microprocessor to inform the
Memory whether it is performing Write Operation or Read Operations.
• The number of Address lines and Data lines varies between
Microprocessors.
• That depends on the Manufacturer.
• Intel 8086 Microprocessor has 20 Address lines (Address Bus) and 16
Data Lines (Data Bus).
 Features of 8086
➢ The 8086 is a 16-bit microprocessor.
➢ The 8086 has a 16-bit data bus, so it can read data from or write
data to memory and ports either 16 bits or 8 bits at a time.

➢ The 8086 has a 20-bit address bus, so it can directly access up

to 220 = 1Mb memory locations.
➢ The 8086 can generate 16-bit I/O address, hence it can access
216 = 65536 I/O ports. It can support up to 64k I/O ports.

➢ The 8086 provides fourteen 16-bit registers.

➢ Frequency range of 8086 is 6-10MHZ

16
 Features of 8086
➢It has a multiplexed address and data bus s AD0- AD15
and A16 – A19
➢Which reduces the number of pins needed, but does slow
down the transfer of data (drawback).
➢It requires +5V power supply.
➢A 40-pin dual in line package.
➢The Intel 8086 is designed to operate in two modes,
namely the minimum mode and the maximum
mode.
➢ The minimum mode is selected by applying logic 1 to the MN / MX# input pin.
➢ This is a single microprocessor configuration.
➢ The maximum mode is selected by applying logic 0 to the MN / MX# input pin.
➢ This is a multi micro processors configuration.

17
 Pin diagram of 8086 microprocessor

18
Features of 8086
➢The Intel 8086 supports multiprogramming.
▪ In multiprogramming, the code for two or more processes is in
memory at the same time and is executed in a time-
multiplexed fashion.
➢Intel 8086 has 6 bytes instruction cache or queue.
➢The 8086 provides powerful instruction set with different
addressing modes such as Register, immediate, direct,
indirect through an index or base, indirect through the
sum of a base and an index register, relative and
implied.

19
Architecture of 8086

20
 Architecture of 8086

21
Block Diagram Architecture
➢ The simplified block diagram of the 80x86 processor model is organized as two separate
processors :
✓ Bus Interface Unit (BIU)
✓ Execution Unit (EU).
➢ These two functional units can work simultaneously to increase system speed and hence the No.
of IPS.
1. BIU:
➢ Is the 8086’s interface to the outside world
➢ Provides a full 16-bit bi-directional data bus and 20-bit address bus.
➢ Sends address of the memory or I/O,
➢ Fetches instruction from memory,
➢ Reads/writes data from/into port/memory, supports instruction queuing and
provides the address relocation facility

❑To implement these functions; the BIU contains the instruction queue,
segment registers, instruction pointer, address summer and bus control
22
logic.
Architecture of 8086
• Instruction queue:
➢ The main linkage between the two functional blocks is the
instruction queue.
➢ To speed up program execution, BIU fetches six instruction bytes ahead of time
from the memory and holds for the EU in a group of registers called Queue.
➢ Queue makes possible to fetch next instruction when current instruction is in
execution.

➢ In case of JUMP and CALL instructions,

instruction already fetched in queue are
of no use.
➢ Fetching the next instruction while the
current instruction executes is called
pipelining.

23
Architecture of 8086
2. Execution Unit (EU)
1. The EU of 8086 tells the BIU from where to fetch
instructions or data, decodes instructions and executes
instructions.
❖ It contains:
➢ Control circuitry ➢ Flag register
➢ Instruction decoder ➢ General purpose
➢ ALU register
➢ Register ➢ Pointers and
Organization Index registers

❖ Control Circuitry, instruction Decoder, ALU:

➢ The control circuitry in the EU directs the internal operations.
➢ A decoder in the EU translates the instructions fetched from memory into a ,series of
actions which the EU performs.
➢ ALU is 16-bit. It can add, subtract, AND, OR, XOR increment, decrements, complement
and shift binary numbers.

24
 Register Organization of 8086
❑ The 8086 microprocessor has a total of 14 registers
that are accessible to the programmer. It is divided into
four groups.
➢ It includes
▪ Four General purpose registers
▪ Four Segment registers
▪ Five Pointers and Index registers
▪ Flag register.
➢ It is also known as programmer’s model of 8086.
➢ The registers shown in programmer’s model are
accessible to programmer.
➢ All registers of 8086 are 16-bit registers.
25
 Register Organization of 8086
1. General purpose registers:
➢ The 8086 has four 16-bit general purpose registers
labeled AX, BX, CX and DX.
➢ They are used for holding data, variables and
intermediate results temporarily.
➢ They can also be used as a counters or used for storing
offset address for some particular addressing modes.
➢ AX is used as 16-bit Accumulator whereas AL is used as
8-bit accumulator.
➢ BX is used as offset storage for generating physical
addresses in case of certain addressing modes.
➢ CX is used as a default counter in case of string and
loop instructions.

26
 Register Organization of 8086
2. Segment Registers:
➢ Registers Belongs to BIU of 8086
➢ The Physical Address of the 8086 is 20-bit wide
to access 1 Mbyte memory locations. However,
its registers and memory locations which
Contain logical addresses are just 16-bits wide.
➢ 8086 uses memory segmentation. It treats the 1
Mbyte of· memory as divided into segments,
with a maximum size of a segment as 64
Kbytes.
➢ The 8086 allows only four active segments at a
time, as shown in fig 2.5 and 16-bit segment
registers are used for the selection.
➢ These four segment registers are: code segment
(CS) register, the data segment (DS) register, the
stack segment (SS) register, and the extra
segment (ES) register.
27
 Register Organization of 8086
3. Pointers and Index Registers
➢ The registers in this group are all 16 bits wide and, unlike the general-purpose
registers, cannot be accessed as a low or high byte.
➢ These registers are used as memory pointers.
➢ Recall that all segment registers are 16-bit wide. But it is necessary to generate
20-bit address (physical address) on the address bus.
➢ To get 20-bit physical address one or more pointer or index registers are
associated with each segment register.
➢ The pointer registers IP, and BP are associated with Code Segment(CS)
➢ SP are associated with stack segments.(SS)
➢ The index registers DI & SI are used as an offset storage in some addressing
modes.

28
Register Organization of
8086

4. Flag Registers
➢ A flag is a flip-flop which indicates some condition produced by the execution of
as instruction or controls certain operations Of the EU.
➢ The flag register contains nine active flags as shown in the figure. Six of them are
used to indicate some condition produced by instruction.
1. CF: carry flag is set if there is a carry out operations. Not available for the
of the MSB or used as borrow flag for programmer.
subtraction (it is set when borrow is [Link]: Zero flag is set if result of ALU is
needed) zero. And also, if certain register content
2. PF: Parity flag is set if result of byte becomes zero following an increment or
operation or lower byte of the word decrement operation.
operation contain an even number of [Link]: sign flag is set if MSB of the result is
ones. 1.
3. AF: Auxiliary flag is set if there is an S=1 Negative S=0 Positive
29 overflow out of bit 3 and is used for BCD
 Register Organization of 8086
4. Flag Registers
➢ OF: Overflow flag is set if result is out of range. Overflow occurs when signed
numbers added or subtracted .An overflow indicates the result had exceeded the
capacity of the machine. For addition this flag is set when there is a carry into
the MSB and no carry out of the MSB or vice-versa. For subtraction, it is set
when the MSB needs a borrow and there is no borrow from the MSB, or vice
versa bit 3 and is used for BCD operations. Not available for the programmer.
➢ Example2.1. : Give the contents Of the Flag Registers after Execution of the
Following addition.
0110 0101 1101 0001
+0010 0011 0101 1010
1000 1001 0010 1011
SF=1 PF=0 CF= 0 AF=0 ZF=0 OF=0

30
31
 Register Organization of 8086
4. Flag Registers
The three remaining flags are used to control certain operations of the
processor.
1. TF: Trap flag is used for single stepping through a program (for
debugging). If TF is set a trap is executed after execution of each
instruction, i.e. interrupt service routine is executed which displays
various registers and memory variable contents.
2. IF: Interrupt flag is used to allow/ prohibit the interruption of a
program. If set, a certain type of interrupt (a maskable interrupt) can
be recognized by the 8086; otherwise, these interrupts are ignored.
3. DF: direction flag is used with string instruction. If DF = 0, the string is
processed from its beginning with the first element having the lowest
address. Otherwise, the string is processed from the high address
towards the low address.

32
Instruction Set of 8086 By Abebe B.

MICROPROCESSOR
 Instruction Set of 8086

❑Instructions are classified on the basis of functions

they perform.
❑They are categorized into the following main types:
1. Data Transfer instruction
2. Arithmetic Instructions
3. Logical Instructions
4. Rotate Instructions
5. Shift Instructions
6. Branch Instructions
7. Flag Manipulation and Processor Control Instructions
8. String Instructions
[Link]
 Instruction Set of 8086

1. Data Transfer instruction:

• All the instructions which perform data movement
come under this category.
• The source data may be a register, memory
location, port etc. the destination may be a
register, memory location or port.
• The following 13 instructions come under this
category
• Example: 1. MOV
2. PUSH
3. POP
4. Etc..
Instruction Description
MOV Moves data from register to register, register to memory, memory to register, memory to
accumulator, accumulator to memory, etc.
LDS Loads a word from the specified memory locations into specified register. It also loads a word
from the next two memory locations into DS register.
LES Loads a word from the specified memory locations into the specified register. It also loads a word
from next two memory locations into ES register.
LEA Loads offset address into the specified register.
LAHF Loads low order 8-bits of the flag register into AH register.
SAHF Stores the content of AH register into low order bits of the flags register.
XLAT/XLATB Reads a byte from the lookup table.
XCHG Exchanges the contents of the 16-bit or 8-bit specified register with the contents of AX register,
specified register or memory locations.
PUSH Pushes (sends, writes or moves) the content of a specified register or memory location(s) onto the
top of the stack.
POP Pops (reads) two bytes from the top of the stack and keeps them in a specified register, or
memory location(s).
POPF Pops (reads) two bytes from the top of the stack and keeps them in the flag register.
IN Transfers data from a port to the accumulator or AX, DX or AL register.
OUT Transfers data from accumulator or AL or AX register to an I/O port identified by the second byte
of the instruction.
 Instruction Set of 8086

2. Arithmetic Instructions
• Instructions of this group perform addition,
subtraction, multiplication, division, increment,
decrement, comparison, ASCII and decimal
adjustment etc.
• The following instructions come under this category:
• Example:
1. ADD
2. SUB
3. MUL
4. Etc..
Instruction Description
ADD Adds data to the accumulator i.e. AL or AX register or memory locations.
ADC Adds specified operands and the carry status (i.e. carry of the previous stage).
SUB Subtract immediate data from accumulator, memory or register.
SBB Subtract immediate data with borrow from accumulator, memory or register.
MUL Unsigned 8-bit or 16-bit multiplication.
IMUL Signed 8-bit or 16-bit multiplication.
DIV Unsigned 8-bit or 16-bit division.
IDIV Signed 8-bit or 16-bit division.
INC Increment Register or memory by 1.
DEC Decrement register or memory by 1.
CBW Convert signed Byte to signed Word.
CWD Convert signed Word to signed Doubleword.
NEG Obtains 2's complement (i.e. negative) of the content of an 8-bit or 16-bit
specified register or memory location(s).
CMP Compare Immediate data, register or memory with accumulator, register or
memory location(s).
 Instruction Set of 8086

3. Logical Instructions
• Instruction of this group perform logical AND, OR, XOR, NOT
and TEST operations.
• The following instructions come under this category:

1. AND
2. OR
3. NOR
4. Etc..
 Instruction Set of 8086

[Link] Instructions
• The following instructions come under this category:
 Instruction Set of 8086

5. Shift Instructions
• The following instructions come under this category :
 Instruction Set of 8086

[Link] Instructions
• It is also called program execution transfer instruction. Instructions of
this group transfer program execution from the normal sequence of
instructions to the specified destination or target.
• Example;
1. JA or JNBE Here, CF = Carry Flag
ZF = Zero Flag
2. JAE/JNB/JNC
OF = Overflow Flag
3. JB/JNAE/JC SF = Sign Flag
4. Etc.. CX = Register
Instruction Description
JA or JNBE Jump if above, not below, or equal i.e. when CF and ZF = 0
JAE/JNB/JNC Jump if above, not below, equal or no carry i.e. when CF = 0
JB/JNAE/JC Jump if below, not above, equal or carry i.e. when CF = 0
JBE/JNA Jump if below, not above, or equal i.e. when CF and ZF = 1
JCXZ /JE/JZ Jump if CX register = 0 /Jump if zero or equal i.e. when ZF = 1
JG/JNLE Jump if greater, not less or equal i.e. when ZF = 0 and CF = OF
JGE/JNL Jump if greater, not less or equal i.e. when SF = OF
JL/JNGE Jump if less, not greater than or equal i.e. when SF ≠ OF
JLE/JNG Jump if less, equal or not greater i.e. when ZF = 1 and SF ≠ OF
JMP Causes the program execution to jump unconditionally to the memory address or label given in the instruction.
CALL Calls a procedure whose address is given in the instruction and saves their return address to the stack.
RET Returns program execution from a procedure (subroutine) to the next instruction or main program.
IRET Returns program execution from an interrupt service procedure (subroutine) to the main program.
INT Used to generate software interrupt at the desired point in a program.
INTO /LOOP Software interrupts to indicate overflow after arithmetic operation. /Jump to defined label until CX = 0.
LOOPZ/LOOPE Decrement CX register and jump if CX ≠ 0 and ZF = 1.
LOOPNZ/LOOPNE Decrement CX register and jump if CX ≠ 0 and ZF = 0.
 Instruction Set of 8086

[Link] Manipulation and Processor Control Instructions

• Instructions of this instruction set are related to flag manipulation
and machine control.
• Example:
1. CLC
2. CLD
3. CLI
4. ESC
5. Etc..
Instruction Description

CLC Clear Carry Flag: This instruction resets the carry flag CF to 0.

CLD Clear Direction Flag: This instruction resets the direction flag DF to 0.

CLI Clear Interrupt Flag: This instruction resets the interrupt flag IF to 0.

CMC This instruction take complement of carry flag CF.

STC Set carry flag CF to 1.

STD Set direction flag to 1.

STI Set interrupt flag IF to 1.

HLT Halt processing. It stops program execution.

NOP Performs no operation.

ESC Escape: makes bus free for external master like a coprocessor or peripheral device.

WAIT When WAIT instruction is executed, the processor enters an idle state in which the processor does no processing.

LOCK It is a prefix instruction. It makes the LOCK pin low till the execution of the next instruction.
 Instruction Set of 8086

8. String Instructions
• String is series of bytes or series of words stored in sequential
memory locations.
• The 8086 provides some instructions which handle string operations
such as string movement, comparison, scan, load and store.
• Example:
1. MOVS/MOVSB/MOVSW
2. CMPS/CMPSB/CMPSW
3. SCAS/SCASB/SCASW
4. Etc..
 By Abebe B.
8086 Addressing Modes
50 Addressing Modes
➢ Efficient software development for the microprocessor requires a
complete familiarity with the addressing modes employed by
each instruction
➢ The 8086 has about 117 different instructions with about 300
opcodes.
➢ The 8086 instruction sets can contain no operand, single operand,
and two operand instructions.
➢ The 8086 instructions do not permit memory to memory operations
except for string instructions which involve array operations.
➢ The processor can access memory in different ways that are
collectively called addressing mode.
➢ In this chapter, the MOV (move data) instruction is used to
describe the data-addressing modes
➢ The MOV instruction transfers bytes or words of data between two
registers or between registers and memory in the 8086.
By: Abebe B

By:Getinet G
51 8086 Addressing Modes
 The addressing modes describe the types of operands and
the way they are accessed for executing an instruction.
 The number of addressing modes is determined when the
microprocessor is designed and cannot be changed.
 The 8086 provides a total of seven distinct addressing modes:
a) Register e) Based relative
b) Immediate f) Indexed relative
c) Direct g) Based indexed
d) Register indirect relative

MOV instructions are used to explain addressing modes.

By: Abebe B
52 8086 Addressing Modes
A) Register Addressing Mode: MOV reg1, reg2;
Relatively fast transfer since memory is not accessed.
Examples:
MOV BX, DX ; copy the contents of DX into BX
MOV ES, AX ; copy the contents of AX into ES
ADD AL, BH ; add the contents of BH to
Contents of AL.
The size of reg1 and reg2 must be the same.
MOV CL, AX is illegal for instance.

By: Abebe B
53 8086 Addressing Modes
B) Immediate Addressing Mode:
➢ MOV reg, constant;
It can be used to load info into any of the registers
except the segment registers(DS,ES ,SS & CS) and flag
register.
Examples:
➢ MOV AX, 2550H ; move 2550H into AX
➢ MOV CX, 625 ; Load the decimal value 625 into CX
➢ MOV BL, 40H ; Load 40H into BL
➢ MOV DS, 0123H; is illegal why?
Instead we can use: MOV AX, 0123H followed by
MOV DS, AX

By: Abebe B
54 8086 Addressing Modes
C) Direct Addressing Mode: MOV reg, [constant] or MOV
[constant], reg;
➢ Here constant is not operand but it is an offset or address in
memory of operand.
➢ Example:
MOV DL, [2400H]; move contents of DS: 2400H into DL
❑ Exercise 3-1: Find the physical address of the memory
location and its contents after the execution of the following,
assuming that DS = 1512H.
MOV AL, 99H
MOV [3518H], AL
➢ The instruction set does not support a memory-to memory
transfer, except with the MOVS instruction.
✓ Example: The MOVS CX, LIST instruction copies the word-
sized contents of memory location LIST into register CX.
By: Abebe B
55 8086 Addressing Modes
D) Register indirect Addressing Mode:
MOV reg1, [reg2] or MOV [reg2], reg1; here the address of the memory
location where the operand resides is held by a register, [Link] One
with Square bracket.
reg1 can be any general purpose register and reg2 can be either of
SI, DI, or BX
❑ Example: MOV AL, [BX]; moves into AL the contents of the memory
location pointed to by DS:BX
MOV CL, [SI] ; move contents of DS:SI into CL
MOV [DI], AH; move contents of AH into DS:DI
For 16 bit register: This have two physical addresses(the lower
physical address (LPA) and the higher physical address (HPA))
➢ The higher byte of the data belongs to the higher physical
address and the lower byte of the data belongs to the lower
physical address
MOV DX, [BX]; move contents of DS:BX into DL and contents of
DS:BX+1 into DH
By: Abebe B
 56 8086 Addressing Modes
Exercise 3-2: Assume that DS = 1120H, SI = 2498H,
and AX = 17FEH. Show the contents of memory
locations after the execution of MOV [SI], AX

Solution: The contents of AX are moved into

memory locations with logical address DS: SI and
DS: SI + 1;
Therefore, the physical address starts at DS (shifted
left) + SI = 13698. According to the little endian
convention, low address I3698H contains FE, the low
byte, and high address 13699H will contain 17, the
high byte.
By: Abebe B
57 8086 Addressing Modes
E) Based Relative Addressing Mode:
❖ MOV reg1, [reg2]+const; or
❖ MOV [reg2]+const, reg1;
➢ NB: const is an 8-bit displacement value.
✓ Reg2+const=an Effective address(EA)
 reg1 can be any general purpose register and reg2
can only be either of BP or BX
 The default segments used for the calculation of the
physical address (PA) are DS for BX and SS for BP.
➢ PA= DS*10H+BX+const; EA=BX + const or
➢ PA=SS*10H+BP+const
By: Abebe B
and EA= BP + const
58 8086 Addressing Modes
❑ Examples:
MOV CX, [BX]+10 ; move DS:BX+10 and DS:BX+10+1 into CX.

➢ LPA = DS*10H+ BX + 10,the data at this memory location is moved to CL

➢ HPA= DS*10H+ BX + 10+1,the data at this memory location is moved to CH
MOV AL, [BP]+5 ;PA = SS*10H + BP + 5
Alternative codings for MOV reg1, [reg2]+const is
MOV reg1, [reg2+const] or MOV reg1, const[reg2]
For instance, MOV CX, [BX]+10 is same as "MOV CX, [BX+10]" or
"MOV CX, 10[BX]"

By: Abebe B
59 8086 Addressing Modes

F) Indexed relative Addressing Mode: MOV reg1, [reg2]+const or MOV

[reg2]+const, reg1; const is an 8-bit displacement value.
 reg1 can be any general-purpose register and reg2 can only be
either of DI or SI
 PA= DS*10H+DI+const; EA=DI+ const or PA=DS*10H+SI+const and
EA= SI + const
 Examples: MOV DX, [SI]+5
;PA = DS (shifted left) + SI + 5
MOV CL, [DI]+20;PA = DS (shifted left) + DI + 20

By: Abebe B
60 8086 Addressing Modes
Exercise 3-3: Assume that DS = 4500, SS = 2000, BX = 2100, SI = 1486,
DI = 8500, BP = 7814, and AX = 2512. Show the exact physical
memory location where AX is stored in each of the following. All
values are in hex.

a)MOV [BX]+20,AX c)MOV [DI]+4,AX

b)MOV [SI]+10,AX d)MOV [BP]+12,AX

Solution: In each case PA = segment register (shifted left) + offset

register + displacement.
(a) DS:BX+20 location 47120 = (12) and 47121 =(25)
(b) DS:SI+10 location 46496 = (12) and 46497 = (25)
(c) DS:DI+4 location 4D504 = (12) and 4D505 = (25)
(d) SS:BP+12 location 27826 = (12) and 27827 = (25)

By: Abebe B
 61 8086 Addressing Modes
G) Based Indexed Addressing Mode: MOV reg1, [reg2][reg3]+const
or MOV [reg2][reg3]+const, reg1; const is an 8-bit displacement
value.
 reg1 can be any general-purpose register and reg2 can only be
either of DI or SI and reg3 can only be either of BX or BP.
 PA= DS*10H+BX+DI+const; EA=DI+BX+ const or
PA=SS*10H+BP+SI+const and EA= SI +BP+ const

▪ Examples:
MOV CL,[BX][DI]+8 ;PA = DS (shifted left) + BX + DI + 8
MOV CH,[BX][SI]+20 ;PA = DS (shifted left) + BX + SI + 20
MOV AH,[BP][SI]+29 ;PA = SS (shifted left) + BP + SI + 29
Note that "MOV AX, [SI][DI]+displacement" is illegal.

By: Abebe B
62 8086 Addressing Modes

▪ Summary of addressing modes:

By: Abebe B
63 8086 Addressing Modes

▪ Summary of addressing modes

By: Abebe B
64 8086 Addressing Modes
▪ Summary of addressing modes

By: Abebe B
65

By: Abebe B