Design For Testability

Lab Manual

[Link]
 VLSI Training Services
Setting standards in VLSI Design

Table of Contents

Lab Instructions .................................................................................................................................... 3

Lab - 1: Path sensitization .................................................................................................................... 4
Lab - 2: Fault Simulation ..................................................................................................................... 6
Lab - 3: Test set minimization ............................................................................................................. 8
Lab - 4: Redundancy .......................................................................................................................... 10
Lab - 5: Test point insertion ............................................................................................................... 12
Lab - 6: Scan chain insertion ............................................................................................................. 14
Lab - 7: Test pattern generation on a stitched netlist ...................................................................... 15
Lab - 8: EDT IP creation .................................................................................................................... 17
Lab - 9: Boundary scan ...................................................................................................................... 19
Lab - 10: IJTAG Implementation...................................................................................................... 22
Lab - 11: Pseudorandom Testing using LFSR patterns .................................................................. 23
Lab - 12: Pseudorandom Testing using LFSR circuit ..................................................................... 25
Lab - 13: Memory BIST ..................................................................................................................... 28
Lab - 14: Clock and DRC ................................................................................................................... 30
Lab - 15: Iterative diagnosis............................................................................................................... 32

[Link] tech_support@[Link] Page 2

 VLSI Training Services
Setting standards in VLSI Design

Lab Instructions

1. The recommended editor is vi or gvim editor.

2. Mentor Graphics Tessent tool is used to insert DFT logic & Questasim is used to run the
test pattern simulation. [Tessent & Questa are the registered trademark of Siemens EDA]
3. The following directory structure is followed for all the lab exercises:
libs/ - contains design, cell & simulation libraries
design/ - contains the source either as RTL or gate-level netlist
tsdb/ - contains sub-directories, files related to DFT flow
simulation_outdir/ - contains simulation log files

4. We use the [Link] script to implement the DFT flow.

5. The command to invoke the tessent shell is $ tessent -shell -logfile <filename> -replace
6. For any technical support to do the lab exercises, please reach out to us on
tech_support@[Link]

[Link] tech_support@[Link] Page 3

 VLSI Training Services
Setting standards in VLSI Design

Lab - 1: Path sensitization

Objective : To understand the generation of ATPG reports & fault simulation process using
test patterns generated by path sensitization algorithm (Path sensitization is one of the fault
simulation algorithm) for a given combinational circuit.

Introduction : For the given combinational circuit, apply path sensitization technique
and identify test pattern that detect h/1 and f/1 faults.

Tool : Tessent Fastscan

Working Directory : Tessent_labs/Lab1/

Dofile script : [Link]
Instructions : The following instructions have been included in the script as
comments. Refer to the comments in the script and understand the script.
 Set the context to Patterns and sub context to scan
 This is done to set the primary context to patterns and subcontext to scan.
This is mainly done to generate test patterns and perform fault simulation.
 Read the design source codes
 The RTL files needs to be read.
 Elaborate the design top
 The design files top has to be elaborated to make sure that the lower sub-
modules are instantiated and integrated to the top module.
 Set the system mode to analysis
 This is done inorder to create test patterns and run fault simulation.
 Adds all the faults to the fault list
 Here the tool will add all the possible fault in the given circuit to the fault
list.
 Generates test patterns
 Here the tool will generate multiple test patterns to detect all the faults in
the fault list.
 Save the test patterns to an ASCII file
 Reports all faults
 The tool will report all the faults.

[Link] tech_support@[Link] Page 4

 VLSI Training Services
Setting standards in VLSI Design

Dofile script : fault_sim.do

Instructions : The following instructions have been included in the script as
comments. Refer to the comments in the script and understand the script.
 Set the context to Patterns and sub context to scan
 This is done to set the primary context to patterns and subcontext to scan.
This is mainly done to generate test patterns and perform fault simulation.
 Read the design source codes
 The RTL files needs to be read.
 Elaborate the design top
 The design files top has to be elaborated to make sure that the lower sub-
modules are instantiated and integrated to the top module.
 Set the system mode to analysis
 This is done inorder to create test patterns and run fault simulation.
 Reading the test pattern from an external file which is created by adding 1 test
pattern from the [Link] file generated in the previous step.
 The test pattern that detects f/1 is stored in a external file.
 Adds all the faults to the fault list
 Here the tool will add all the possible fault in the given circuit to the fault
list.
 Simulate test patterns
 Here the tool will run simulation by reading patterns from an external file.
 Reports statistics
 Tool generates the report of fault simulation.
 Reports faults
 The tool will report all the fault that are detected by simulation.
 Reset state
 Ready to take the next set of test pattern.

*Note: Same steps as in [Link] will be repeated for h/1fault by reading test patterns from the external file
c1_pat_h1.ascii.

DFT implementation process :

 Go to the directory: cd Tessent_labs/Lab1
 Run the dofile script.
 Observe the output
 The [Link] file will generate an ascii file named
“[Link]”.
 The [Link] file is used to do fault simulation using 2 test
patterns file and we need to compare the test coverages
generated by each test pattern file.

Learning outcomes :
Understanding how to generate test patterns for a particular fault using path
sensitization technique.

[Link] tech_support@[Link] Page 5

 VLSI Training Services
Setting standards in VLSI Design

Lab - 2: Fault Simulation

Objective : For the given combinational circuit , use deductive fault simulation technique for 3
test patterns to determine the lists of faults on the primary output.
Introduction : For the given combinational circuit, deductive fault simulation technique
is applied on given test patterns & the fault lists are obtained. Test vectors which can
identify these faults are stored in external files and using these patterns, fault simulation
is performed.

Tool : Tessent Fastscan

Working Directory : Tessent_labs/Lab2/

Dofile script : fault_sim.do
Instructions : The following instructions have been included in the script as
comments.

Refer to the comments in the script and understand the script.

 Set the context to Patterns and sub context to scan
 This is done to set the primary context to patterns and subcontext to scan.
This is mainly done to generate test patterns and perform fault simulation.
 Read the design source codes
 The RTL files needs to be read.
 Elaborate the design top
 The design files top has to be elaborated to make sure that the lower sub-
modules are instantiated and integrated to the top module.
 Set the system mode to analysis
 This is done inorder to create test patterns and run fault simulation.
 Reading the test pattern from an external file
 The test patterns are stored in a external file.
 Adds all the faults to the fault list
 Here the tool will add all the possible fault in the given circuit to the fault
list.
 Simulate test patterns
 Here the tool will run simulation by reading patterns from an external file.
 Report statistics
 Tool generates the report of fault simulation.

[Link] tech_support@[Link] Page 6

 VLSI Training Services
Setting standards in VLSI Design

 Report faults
 The tool will report all the faults that are detected by simulation.
 Reset state
 Ready to take the next set of test pattern.

*Note: Same steps as in [Link] are repeated by using different external test patterns files c2_11011_2.pat
and c2_00110_3.pat.

DFT implementation process :

 Go to the directory: cd Tessent_labs/Lab2
 Run the dofile script.
 Observe the output
 After running the fault simulation, analyze the fault report and
indicate the detected faults.
 Compare the obtained results with the fault lists detected by the
deductive fault simulation technique.

Learning outcomes :
To understand deductive fault simulation technique.

[Link] tech_support@[Link] Page 7

 VLSI Training Services
Setting standards in VLSI Design

Lab - 3: Test set minimization

Objective : For the given combinational circuit, test set minimization is done by selecting test
patterns that identifies all the faults after applying equivalent fault collapsing.

Introduction : For the below combinational circuit, create a fault table for all stuck-at
faults. Then determine the equivalent fault classes. Then create a reduced fault table
by removing all faults but the first member of each class and undetectable faults.
Then select a minimal set of tests to cover all the detectable [Link] fault
simulation is performed on all the test patterns.

Tool : Tessent Fastscan

Working Directory : Tessent_labs/Lab3/

Dofile script : fault_sim.do
Instructions : The following instructions have been included in the script as
[Link] to the comments in the script and understand the script.
 Set the context to Patterns and sub context to scan
 This is done to set the primary context to patterns and subcontext to scan.
This is mainly done to generate test patterns and perform fault simulation.
 Read the design source codes
 The RTL files needs to be read.
 Elaborate the design top
 The design files top has to be elaborated to make sure that the lower sub-
modules are instantiated and integrated to the top module.
 Set the system mode to analysis
 This is done inorder to create test patterns and run fault simulation.
 Pattern are read from the external source(c1_0.ascii).
 The test patterns are stored in a external file.
 Adds all the faults to the fault list
 Here the tool will add all the possible fault in the given circuit to the fault
list.

[Link] tech_support@[Link] Page 8

 VLSI Training Services
Setting standards in VLSI Design

 Simulate test patterns

 Here the tool will run simulation by reading patterns from an external file
 Reports statistics
 Tool generates the report of fault simulation
 Reports faults
 The tool will report all the fault that are detected by simulation.
 Reset state
 Ready to take the next set of test pattern.

*Note: Same steps followed as in [Link] by using 16 external test patterns files from c1_0.ascii to
c1_15.ascii file.

DFT implementation process :

 Go to the directory: cd Tessent_labs/Lab3
 Run the dofile script.
 Observe the output
 After running the fault_sim.do file, compare the performances
i.e test coverages obtained from each test set from the
minimzed test sets.

Learning outcomes :
To understand how equivalent fault collapsing is performed by the tool and how test set
is minimized.

[Link] tech_support@[Link] Page 9

 VLSI Training Services
Setting standards in VLSI Design

Lab - 4: Redundancy

Objective : For the given combinational circuit, we need to remove redundancy by modifying
the circuit.

Introduction : Analyse the redundant fault for the given circuit and remove the
redundant fault without affecting the functionality of the circuit.

Tool : Tessent Fastscan

Working Directory : Tessent_labs/Lab4/

Dofile script : [Link], atpg_mod.do
Instructions : The following instructions have been included in the [Link]
script as comments. Refer to the comments in the script and understand the script.
 Set the context to Patterns and sub context to scan
 This is done to set the primary context to patterns and subcontext to scan.
This is mainly done to generate test patterns and perform fault simulation.
 Read the design source codes
 The RTL files needs to be read.
 Elaborate the design top
 The design files top has to be elaborated to make sure that the lower sub-
modules are instantiated and integrated to the top module.
 Set the system mode to analysis
 This is done in-order to create test patterns.
 Select the type of fault to be stuck-at-fault
 Stuck at fault is a type of fault to be detected.
 Adds all the faults to the fault list
 Here the tool will add all the possible fault in the given circuit to the fault
list.
 Generate test patterns
 Tool will generate test patterns to detect all stuck at faults in the given
circuit.
 Reports faults of RE type

[Link] tech_support@[Link] Page 10

 VLSI Training Services
Setting standards in VLSI Design

 The tool will report all the fault that are redundant.

*Note: The Given circuit is modified such that redundancy is removed and again the steps in atpg_mod.do file is
applied to the modified circuit and after ATPG analysis, redundant faults are not [Link] analysis purpose
given circuit and modified circuit are simulated using Questa sim using a Verilog test bench such that the
simulation outputs are same.

DFT implementation process :

 Go to the directory: cd Tessent_labs/Lab4
 Run the dofile script.
 Observe the output
 The no of redundant faults after running the [Link] file was
observed to be 11. Then after running the modified atpg dofile
i.e atpg_mod.do file, the no of redundant faults was observed
to be 0.

Learning outcomes :
To understand how redundant faults can be removed from a combinational circuit
without affecting its functionality.

[Link] tech_support@[Link] Page 11

 VLSI Training Services
Setting standards in VLSI Design

Lab - 5: Test point insertion

Objective : To insert control and observation points inorder to increase the test effectiveness
without removing redundancy.

Introduction : For the given combinational circuit control and observation points are
added such that redundant faults are removed.

Tool : Tessent Fastscan

Working Directory : Tessent_labs/Lab5/

Dofile script : [Link], atpg_mod.do
Instructions : The following instructions have been included in the script as
comments. Refer to the comments in the script and understand the script.
 Set the context to Patterns and sub context to scan
 This is done to set the primary context to patterns and subcontext to scan.
This is mainly done to generate test patterns and perform fault simulation.
 Read the design source codes
 The RTL files needs to be read.
 Elaborate the design top
 The design files top has to be elaborated to make sure that the lower sub-
modules are instantiated and integrated to the top module.
 Set the system mode to analysis
 This is done inorder to create test patterns and run fault simulation.
 Select the type of fault to be detected
 Stuck at fault is a type of fault to be detected.
 Adds all the faults to the fault list
 Here the tool will add all the possible fault in the given circuit to the fault
list.

[Link] tech_support@[Link] Page 12

 VLSI Training Services
Setting standards in VLSI Design

 Generate test patterns

 Tool will generate test patterns to detect all stuck at faults in the given
circuit.
 Reports faults of RE type
 The tool will report all the fault that are redundant.

*Note: The Given circuit is modified such that redundancy is removed by insertion of test points and
observation points and again the steps in atpg_mod.do file is applied to the modified circuit and after ATPG
analysis, redundant faults are not reported.

For analysis purpose given circuit and modified circuit are simulated in Questa sim using a Verilog test bench
such that simulation outputs are same.

DFT implementation process :

 Go to the directory: cd Tessent_labs/Lab5
 Run the dofile script.
 Observe the output.
 The no of redundant faults after running the [Link] file was
observed to be 11. Then after running the modified atpg dofile
i.e atpg_mod.do file, the no of redundant faults was observed
to be 0.

Learning outcomes :
To understand how redundant fault can be removed from a combinational circuit
without affecting its functionality by adding test points.

[Link] tech_support@[Link] Page 13

 VLSI Training Services
Setting standards in VLSI Design

Lab - 6: Scan chain insertion

Objective : To understand how to insert scan chain into a design.

Introduction : In this lab we are going to use a gate level netlist and insert scan chain
into this netlist.

Tool : Tessent scan

Working Directory : Tessent_labs/Lab6/

Dofile script : [Link]
Instructions : The following instructions have been included in the script as
comments. Refer to the comments in the script and understand the script.
 Set the context to “dft” with the sub-context to “scan”
 This is done to set the primary context to DFT & sub-context to scan as
DFT instrument has to be inserted i.e scan cells.

 Read the cell library files.

 Read the synthesized design

 The gate-level netlist file needs to be read.
 Elaborate the design top
 The design files top has to be elaborated to make sure that the lower sub-
modules are instantiated and integrated to the top module.
 Set design level to chip
 Define the clocks

 Run the DRC

 DRC i.e design rule check is performed to validate the DFT requirements.
 Set a chain constraint for scan chains
 It is going to set the scan chain as per the count given and FFs will be
distributed depending upon the no of chains.
 Distribute the scan elements to chain
 This will distribute the FFs on the chain.
 Report the distribution prior to insertion
 Reports the scan chain & cells.
 Modify the Netlist
 Insert the test logic.
 Review the report files.
 Write the modified stitched netlist
 Create the ATPG set up files

DFT implementation process :

 Go to the directory: cd Tessent_labs/Lab6
 Run the dofile script.
 Observe the output
 After running the dofile script, a scan inserted netlist file
“scan_stitched.v” will be created.

[Link] tech_support@[Link] Page 14

 VLSI Training Services
Setting standards in VLSI Design

 ATPG set up files are also created which will be used during
ATPG process.

Learning outcomes : To insert the scan chain in a single mode for a given design and
generate a scan inserted netlist.

Lab - 7: Test pattern generation on a stitched netlist

Objective : Understand how to generate ATPG test patterns on a scan stitched netlist.
Introduction : In this lab we are generating the test patterns on the scan chain stiched
netlist that we got from the previous lab.

Tool : Tessent Fastscan

Working Directory : Tessent_labs/Lab7/

Dofile script : [Link]
Instructions : The following instructions have been included in the script as
comments. Before running the dofile script, we need to copy the ATPG setup
files and scan stitched netlist file to this lab from the previous lab. Refer to the
comments in the script and understand the script.
 Set the context to “patterns” with the sub-context to “scan”
 This is done to set the primary context to patterns & sub-context to scan as
test patterms need to be generated.
 Read the cell library files
 The I/O cell library needs to be read.
 Read the scan inserted netlist.
 The scan stiched netlist file needs to be read.
 Define the clocks.

 Elaborate the design top

 The design files top has to be elaborated to make sure that the lower sub-
modules are instantiated and integrated to the top module.
 Read the ATPG setup dofile that was created by Tessent scan during scan
insertion.
 Run the TCL procedure from the [Link]
 Run the DRC
 DRC i.e design rule check is performed to validate the DFT requirements.
 Displays a list of all clocks
 Generate the test patterns
 ATPG tool is used to generate the test patterns.
 Displays a statistics report
 Generate the test patterns
 Displays faults for selected fault class
 Write the test patterns to an ASCII file

DFT implementation process :

 Go to the directory: cd Tessent_labs/Lab7
 Run the dofile script.

[Link] tech_support@[Link] Page 15

 VLSI Training Services
Setting standards in VLSI Design

 Observe the output

 A test pattern file “[Link]” will be generated.

Learning outcomes :
To generate the test patterns onto a scan inserted Netlist.

[Link] tech_support@[Link] Page 16

 VLSI Training Services
Setting standards in VLSI Design

Lab - 8: EDT IP creation

Objective : To understand how to insert EDT IP core using Tessent Test-kompress.

Introduction : In this lab you start with a gate level Netlist, a non-scan Netlist, insert
scan chains using Tessent scan, create Tessent Test-kompress EDT IP core.

Tool : Tessent scan, Tessent Test kompress

Working Directory : Tessent_labs/Lab8/

Dofile script : [Link], edt_ip.do
Instructions : The following instructions have been included in the script
[Link] as comments. Refer to the comments in the script and understand the
script.
 Set the context to DFT scan mode
 This is done to set the primary context to DFT & sub-context to scan mode
for scan insertion.
 Read the cell library files
 The I/O cell library needs to be read.
 Read the synthesized design
 The gate-level netlist file needs to be read.
 Set the current design for elaboration process.
 The design files top has to be elaborated to make sure that the lower sub-
modules are instantiated and integrated to the top module.
 If any module descriptions are missing, design elaboration will identify
them by adding add_black_boxes -auto.
 Identify and define control signals.
 Run DRC
 Set the scan chains count to 2
 Insert the scan logic
 Report scan chains and new test logic
 Write the scan inserted netlist
 It creates the scan chain netlist inside the netlist directory.
 Write out atpg dofile and testproc file
The following instructions have been included in the script edt_ip.do
as comments. Refer to the comments in the script and understand the
script.
 Set the context to DFT edt mode
 This is done to set the primary context to DFT & sub-context to edt mode
for EDT ip insertion.
 Read the scan chain netlist
 Read the cell library files
 The I/O cell library needs to be read.
 Set the current design for elaboration process.
 The design files top has to be elaborated to make sure that the lower sub-
modules are instantiated and integrated to the top module.
 Define scan chains & control signals
 Used to run the TCL procedure from the [Link]
 Specify parameters for EDT logic

[Link] tech_support@[Link] Page 17

 VLSI Training Services
Setting standards in VLSI Design

 Report EDT channels & pins

 Run DRC
 Report configuration of EDT logic
 Write the EDT modified RTL files

DFT implementation process :

 Go to the directory: cd Tessent_labs/Lab8
 Run first the [Link] script followed by edt_ip.do script.
 Observe the output
 The [Link] file will generate a scan inserted netlist file inside
the netlist directory and create the ATPG setup files in the
current directory.
 The edt_ip.do file will create the EDT IP core RTL files inside
the results directory.

Learning outcomes :
To insert an EDT IP core into a scan stitched netlist.

[Link] tech_support@[Link] Page 18

 VLSI Training Services
Setting standards in VLSI Design

Lab - 9: Boundary scan

Objective : To understand how to insert Boundary scan at the chip level.

Introduction : There is a gate level circuit and few DFFs for which boundary scan needs
to be implemented at chip level.

Tool : Tessent Boundary scan

Working Directory : Tessent_labs/Lab9/

Dofile script : [Link]
Instructions : The following instructions have been included in the script as
comments. Refer to the comments in the script and understand the script.
 Set the context to DFT
 This is done to set the primary context to DFT as DFT instrument has to be
inserted i.e Boundary scan.
 Create & set the TSDB directory
 Use “mkdir” linux command to create a directory in Linux terminal.
 Then set the directory as TSDB directory in the tessent shell.
 Read the cell library files
 The I/O cell library needs to be read.
 Read the design source codes
 The RTL files needs to be read.
 Elaborate the design top
 The design files top has to be elaborated to make sure that the lower sub-
modules are instantiated and integrated to the top module.
 Set the design level to chip level
 The boundary scan is always inserted at chip level.
 Specify the DFT requirement
 Here the boundary scan needs to be turned on.
 Set attributes for the TAP controller pins
 Here the attributes for the TAP controller pins (i.e) TDI,TCK,
TMS,TRST,TDO are specified.
 Run the DRC
 DRC i.e design rule check is performed to validate the DFT requirements.
 Create & report the DFT specification

[Link] tech_support@[Link] Page 19

 VLSI Training Services
Setting standards in VLSI Design

 After a successful DRC run, create DFT specification & report the same on
the Tessent shell.
 Insert the DFT instruments
 This is going to insert the DFT components and a modified RTL file is
created inside the TSDB directory.
 Display the visualizer
 This will display the added DFT components using the DFT visualizer.
 Set the system mode to SETUP

Please follow the below steps to view the modified netlist in the visualizer.

[Link] tech_support@[Link] Page 20

 VLSI Training Services
Setting standards in VLSI Design

DFT implementation process :

 Go to the directory: cd Tessent_labs/Lab9
 Run the dofile script.
 Observe the output
 After running the dofile, the modified RTL file is created
under the path below :
tsdb/dft_inserted_designs/dff_top_rtl.dft_inserted_design/
modified_rtl_files
 The modified file has the Boundary scan components inserted
i.e TAP interface, Boundary scan cell insterface.

Learning outcomes :
To insert Boundary scan using Tessent shell at chip level.

[Link] tech_support@[Link] Page 21

 VLSI Training Services
Setting standards in VLSI Design

Lab - 10: IJTAG Implementation

Objective : To understand how to create ICL & PDL files using Tessent shell.

Introduction : In this lab we have used a PLL design file for which .icl file will be
created & .pdl file for the .icl file will be generated.
Create [Link] file inside the directory PLL_models as per the syntax mentioned in the
dofile.
Working Directory : Tessent_labs/Lab10/
Dofile script : icl_pdl.do
Instructions : The following instructions have been included in the icl_pdl.do
script as comments. Refer to the comments in the script and understand the script.
 Set the context to DFT
 This is done to set the primary context to DFT as .icl files are elaborated
with the set_current_design.
 Read the design source codes
 This reads the design source code.
 Elaborate the design top
 The design files top has to be elaborated to make sure that the lower sub-
modules are instantiated and integrated to the top module.
 Read the .icl file with a switch -force
 This is going to read the .icl file such that tessent shell is aware of this file.
 Elaborate the design top
 The design file top has to be elaborated to make sure that the .icl file gets
elaborated.
 Create the .pdl file using the below tessent commands.
 Set the context to patterns
 The primary context should be set to patterns and sub-context should be
set to ijtag.
 Set the design level to chip
 Verify the ICL ports
 The Tessent shell will recognize the ICL ports.
 Run DRC
 Create a PDL pattern set
 The pattern set will define how the ports are driven with values.

DFT implementation process :

 Go to the directory: cd Tessent_labs/Lab10
 Run the dofile script.
 Observe the output
 The .pdl file will be created inside the PLL_Models directory.

Learning outcomes :
To create .icl & .pdl files for a design.

[Link] tech_support@[Link] Page 22

 VLSI Training Services
Setting standards in VLSI Design

Lab - 11: Pseudorandom Testing using LFSR patterns

Objective : To test a combinational circuit using random test patterns that are generated
using Linear feedback shift register (LFSR).

Introduction : For the given combinational circuit, random test patterns are generated
using a 4 bit LFSR which is designed using a primitive polynomial x4+x+1. The initial
state is given as 0001 and from this, maximum length sequences have to be generated &
these states are saved as test patterns in an external file. Using the test patterns, fault
simulations have been carried out.

Tool : Tessent Fastscan

Working Directory : Tessent_labs/Lab11/

Dofile script : [Link]
Instructions : The following instructions have been included in the script as
Refer to the comments in the script and understand the script.
 Set context to patterns and sub-context to scan
 This is done to set the primary context to patterns and subcontext to scan.
This is mainly done to generate test patterns and perform fault simulation.
 Read the design source codes
 The RTL files needs to be read.
 Elaborate the design top
 The design files top has to be elaborated to make sure that the lower sub-
modules are instantiated and integrated to the top module.
 Set the system mode to analysis
 This is done inorder to create test patterns and run fault simulation.
 Test patterns are read from an external file
 Test patterns generated from the LFSR, are stored in the files c1_1.pat,
c1_2.pat, c1_4.pat, c1_8.pat, c1_16.
 Adds all the faults to the fault list
 Here the tool will add all the possible faults in the given circuit to the fault
list.
 Simulate patterns
 Tool will perform simulation using test patterns stored in external files.

[Link] tech_support@[Link] Page 23

 VLSI Training Services
Setting standards in VLSI Design

 Reports statistics
 The tool will report all the fault that are detected by the test patterns along
with the fault coverage.
 Reset state
 Ready to take the next set of test pattern.

DFT implementation process :

 Go to the directory: cd Tessent_labs/Lab11
 Run the dofile script.
 Observe the output.
 Compare the test coverages for each pattern file during fault
simulation.

Learning outcomes :
To understand how random test patterns are generated and are applied to a
combinational circuit for fault simulation.

[Link] tech_support@[Link] Page 24

 VLSI Training Services
Setting standards in VLSI Design

Lab - 12: Pseudorandom Testing using LFSR circuit

Objective : To generate random test patterns for the given combinational circuit using
patterns generated from a Verilog HDL file.

Introduction : For the given combinational circuit, random test patterns are generated
using a 3 bit LFSR designed using a primitive polynomial x3+x2+1. The Verilog HDL
code for the LFSR is shared in the design directory. A testbench has to be used to
generate the outputs of the LFSR which are saved as the test patterns.

Tool : Tessent Fastscan

[Link] tech_support@[Link] Page 25

 VLSI Training Services
Setting standards in VLSI Design

CUT

[Link] tech_support@[Link] Page 26

 VLSI Training Services
Setting standards in VLSI Design

Working Directory : Tessent_labs/Lab12/

Dofile script : [Link]
Instructions : The following instructions have been included in the script as

Refer to the comments in the script and understand the script.

 Set the context to Patterns and sub context to scan
 This is done to set the primary context to patterns and subcontext to scan.
This is mainly done to generate test patterns and perform fault simulation.
 Read the design source codes
 The RTL files needs to be read.
 Elaborate the design top
 The design files top has to be elaborated to make sure that the lower sub-
modules are instantiated and integrated to the top module.
 Set the system mode to analysis
 This is done inorder to create test patterns and run fault simulation.
 Test patterns are read from an external file
 Test patterns generated from LFSR are stored in files c1_1.pat, c1_2.pat,
c1_4.pat, c1_8.pat.
 Adds all the faults to the fault list
 Here the tool will add all the possible faults in the given circuit to the fault
list.
 Simulate patterns
 Tool will perform simulation using test patterns stored in external files.
 Reports statistics
 The tool will report all the fault that are detected by the test patterns.

*Note: For analysis purpose a 3 bit LFSR is designed and simulated in Questa sim using a Verilog test bench
in-order to generate random test patterns.

DFT implementation process :

 Go to the directory: cd Tessent_labs/Lab12
 Run the dofile script.
 Observe the output
 Compare the test coverages for each pattern file during fault
simulation.

Learning outcomes :
To understand how random test patterns are generated and are applied to a
combinational circuit for fault simulation.

[Link] tech_support@[Link] Page 27

 VLSI Training Services
Setting standards in VLSI Design

Lab - 13: Memory BIST

Objective : To understand the DFT flow for inserting MBIST.

Introduction : There is a blockB which is a single level of hierarchy which has a

memory instance i.e memA. clkb is the functional clock for blockB.

Tool : Tessent Memory BIST

Working Directory : Tessent_labs/Lab13/

Dofile script : [Link]
Instructions : The following instructions have been included in the script as
comments. Refer to the comments in the script and understand the script.
 Set the context to DFT & sub-context to rtl
 This is done to set the primary context to DFT as DFT instrument has to be
inserted i.e MBIST.
 Create & set the TSDB directory
 Use “mkdir” linux command to create a directory in Linux terminal.
 Then set the directory as TSDB directory in the tessent shell.
 Read the cell library files
 The I/O cell library needs to be read.
 Read the design source codes & memory files
 The RTL & memory files needs to be read.
 Elaborate the design top
 The design files top has to be elaborated to make sure that the lower sub-
modules are instantiated and integrated to the top module.
 Set the design level to sub-block level
 The memory block to which MBIST is inserted is a sub-block.
 Specify the DFT requirement
 Here the MBIST needs to be turned on and a clock needs to be added for
the MBIST.
 Verify the DFT requirement
 DRC i.e design rule check is performed to validate the DFT requirements.
 Create & report the DFT specification
 After a successful DRC run, create DFT specification & report the same on
the Tessent shell.
 Display the DFT specification

[Link] tech_support@[Link] Page 28

 VLSI Training Services
Setting standards in VLSI Design

 This is going to open the GUI interface of the DFT visualizer and you will
see the specification as IJTAG network & MBIST.
 Insert the DFT instruments
 This is going to insert the DFT components and a modified RTL file is
created inside the TSDB directory.
 Display the visualizer
 This will display the added DFT components using the DFT visualizer.

 Extract the ICL

 This will generate the .icl(Instrument connectivity language),
.pdl(procedural description language), .sdc(synopsys design constraint)
files.
 Create & report the pattern specification
 This will create the pattern specification & report the same.
 Process the patterns
 This will generate the patterns needed for simulation.
 Set up the simulation library
 This will set the simulation libraries needed for testbench simulations.

 Run & check the simulation

 This will validate the IJTAG & MBIST insertions.

DFT implementation process :

 Go to the directory: cd Tessent_labs/Lab13
 Run the dofile script.
 Observe the output
 After MBIST is inserted, check the MBIST instances in the
modified RTL file under the path as below:
TSDB/dft_inserted_designs/blockB_rtl.dft_inserted_design/m
odified_rtl_files
 After the fault simulation check the simulation status which
should be pass 4 fail 0.

Learning outcomes :
To insert the MBIST at sub-block level using Tessent DFT flow.

[Link] tech_support@[Link] Page 29

 VLSI Training Services
Setting standards in VLSI Design

Lab - 14: Clock and DRC

Objective : To understand what could be clock DRC violations for MBIST at core level.

Introduction : There is a physical block that contains two instances of blockA and one
instance of blockB. The physical block also includes a clock divider, a clock mux and
clock gaters. As you go through the DFT flow, there will be DRC violations that has to
be fixed.

Working Directory : Tessent_labs/Lab14/

Dofile script : [Link]
Instructions : The following instructions have been included in the script as
comments. Refer to the comments in the script and understand the script.
 Set the context to DFT
 This is done to set the primary context to DFT as DRCs are checked in the
DFT flow.
 Read the cell library files
 The I/O cell library needs to be read.
 Read the design source codes
 The RTL files needs to be read.
 Read the TSDBs of the sub-blocks
 The TSDBs of the sub-blocks to be opened.
 Elaborate the design top
 The design files top has to be elaborated to make sure that the lower sub-
modules are instantiated and integrated to the top module.
 Source the PDL file of the clock divider
 The .pdl file won’t be automatically elaborated unlike the .icl file, hence
needs to be sourced.
 Report the open tsdb directories
 This will display the list of tsdb directories.

[Link] tech_support@[Link] Page 30

 VLSI Training Services
Setting standards in VLSI Design

 Report the name & location of the tsdb directories

 This will display the location of tsdb directories.
 Report IJTAG instances that are included in this design
 This will display the ijtag instances.
 Report all the ICL modules
 This will display the .icl modules loaded into the design.
 Report the identified clock enables
 It will report the clock enable point of the clock gaters.
 Set the design level to physical block level
 The memory blocks are part of a core block now.
 Specify the DFT requirements
 Here the MBIST needs to be turned on without adding clock so that the
DRC violations will be observed.
 Validate the DFT requirements
 DRC i.e design rule check is performed to validate the DFT requirements.

For the rest of the steps, run the relevant commands from the tessent shell.
 Report a specific DRC violation
 DRC violation errors about a specific violation can be reported.
 Analyze the violation using schematic viewer
 DRC violation errors can be viewed in GUI mode using DFT visualizer.
 Fixing the violation DFT_C1-1
 DRC violations are fixed.
 Run the DRC
 DRC i.e design rule check is performed to validate the DFT requirements.
 The above process is repeated till all the violations are fixed.
 Report the clocks
 All the clocks will be defined now.

DFT implementation process :

 Go to the directory: cd Tessent_labs/Lab14
 Run the dofile script.
 Observe the output
 This lab has got 3 Clock violations.
 After these violations are fixed, the clocks will get defined
which will be reported by the command “report_clocks”.

Learning outcomes :
To fix DRC violations at physical block level in a MBIST environment.

[Link] tech_support@[Link] Page 31

 VLSI Training Services
Setting standards in VLSI Design

Lab - 15: Iterative diagnosis

Objective : To generate additional test patterns for use on the ATE in order to improve
the diagnostic resolution.

Introduction : The failure logs from the ATE machine, testing the chip is collected.
Then we need to run the diagnosis on the failure logs using Tessent Diagnosis and save
the diagnosis report. New test patterns are created using the tool and then applied on the
ATE. Collect the failure logs from the ATE on the device of interest using the new
iterative diagnosis pattern. Re-run Tessent Diagnosis with the new pattern and the new
failure log.

Tool : Tessent Diagnosis

Working Directory : Tessent_labs/Lab15/

Dofile script : 1_iterative.dofile, 2_defect.dofile, 3_eval.dofile
Instructions : The following instructions have been included in the
1_iterative.dofile script as comments. Refer to the comments in the script and
understand the script.
 Set the context to patterns and sub-context to scan_diagnosis
 This is done to set the primary context to patterns and sub-contexts to
scan_diagnosis.
 Read the flattenned model
 Set the diagnosis option
 Read the pattern file produced by test-kompress
 Run diagnosis
 This is done using the [Link] file from the ATE machine.
 Create additional internal patterns
 Save additional patterns
The following instructions have been included in the 2_defect.dofile
script as comments. Refer to the comments in the script and
understand the script.
 Set the context to patterns and sub-context to scan_diagnosis
 This is done to set the primary context to patterns and sub-contexts to
scan_diagnosis.
 Read the flattenned model
 Set the diagnosis option
 Read the pattern file produced by the 1st step
 Emulate the failure
The following instructions have been included in the 3_eval.dofile
script as comments. Refer to the comments in the script and
understand the script.
 Set the context to patterns and sub-context to scan_diagnosis
 This is done to set the primary context to patterns and sub-contexts to
scan_diagnosis.
 Read the flattenned model
 Set the diagnosis option
 Read both the patterns file produced from the previous steps

[Link] tech_support@[Link] Page 32

 VLSI Training Services
Setting standards in VLSI Design

 Read both the failure files

 Perform the diagnosis

DFT implementation process :

 Go to the directory: cd Tessent_labs/Lab15
 Run the dofile script.
 Observe the output
 Analyze the diagnosis report and compare the results. Out of 13
suspects, 6 suspects will be reported now for the symptom number 2.

Learning outcomes :
To improve the diagnosis performance by doing iterative failure files diagnosis.

[Link] tech_support@[Link] Page 33