Sequential Logic

Sequential logic
Exit
Entrance Logic
Combinatorics
In sequential logic, the state of the
outcome depends not only on the state
entries but also of the state
Next state
previous to the exit.
Sequential systems introduce State
so the concept of memory (for future
stocker l’état du système) et
from the clock (to determine the Memory element
measurement moments

Sequential systems bring a memory aspect to logic.

We remember that the present state is an output of the memory element, while
The future state is an input.
Notation of the states
How to note a state 'Q' in the past, present or future?
Passed Present Future
Qn , Qn-1, Qn+1 state of Q respectively at the present moment, previous and following.

Qn-1 Qn Qn+1 Time

To determine the present state at output, it is necessary to:

 The current state at the entrance

 The previous state of the output

 Clock: component passing indefinitely and regularly from one level
high to a low level (sequence of 1s and 0s), each transition is called
untop
The consideration of the top occurs during the clock transitions.

Two types of sequential logic:

 asynchronous: The output changes state "at the same time" as the state of
entries.
 The output changes state when a control signal (clock)
I authorize it. This clock can intervene by:
front amount 0 to 1
front descendant 1→0

1 1 1 1 1 1 1
h 0 0 0 0 0 0 0

T
Front mounting Front descendant
 Elements of Memory
In sequential logic, the previous states of the outputs come into play for
the preparation of the output statement. The memory function is the main one
constituting sequential systems. Thus, a sequential system
A complex can be developed from an organized set of memories.
elementary and combinatorial logic operators.

Element of Q
command memory Value
memorized

Order Qn Qn+1
QnCurrent state
Set X 1
Qn+1 ouQ+Next state
Reset X 0
0 0
Memorization 1 1

The memory element is said to be in the "Set" state if Q=1 and Q'=0.
The memory element is said to be in the 'Reset' state if Q=0 and Q'=1.
 Asynchronous Bascule
2 NOR doors Equivalent diagram
R
Q
S Q

Q' R Q'
S

2entries:SetR
2 Outputs: QetQ’
It is formed by two NOR gates connecting their outputs to
the entrance of the other door.

The RS flip-flop is said to be in the 'Set' state if Q=1 and Q'=0

The RS flip-flop is said to be in the 'Reset' state if Q=0 and Q'=1
Qn+1 =(R + Q')' n
Q' n+1 = (S + Qn )’
 Asynchronous Bascule
__
R=0 , S=0 et Q = 0 S R QnQn+1 Qn+1
0 0 0
0

0
0

(Hold State)

7
Asynchronous Bascule
__
S R QinQn+1 Qn+1
0 0 0 0 1
0 0
1

0 1
0

(Hold State)

8
 Asynchronous Bascule
__
R=0 , S=0 et Q = 0 S R Qn Qn+1 Qn+1
0 0 00 0
0 1 0 0 1

1
0
0

Hold State

9
RSAsynchronous Bascule
__
S R Qn Qn+1 Qn+1
0 0 00 0
0 1 0 0 11 0
0

1 0
0

Hold State
Qn+1=Qn State Hold (memorization)
10
 Asynchronous Bascule
R=1 , S=0 __
S R QnQn+1 Qn+1
0 0 00 0
1 0 0 0 11 0
0 1 0 0 1
0 1 0 0 1

0
1
0

(Set State)

11
 Asynchronous Bascule
R=0 , S=1 __
S R Qn Qn+1 Qn+1
0 0 00 0
0 0 0 11 0
0 0 1 00 1
0 1 10 1
1 0 0

0 0
1

(Set State)

12
 Asynchronous Bascule
R=0 , S=1 et Q = 1 __
S R QnQn+1 Qn + 1
0 0 00 0
0 1 0 0 11 0
0 0 1 00 1
0 1 10 1
1 0 01 0
1 0 11 0
1 0
1

(Set State)

13
 Asynchronous Bascule
R=1 , S=1 __
S R Qn Qn+1 Qn+1
0 0 00 0
1 0 0 0 11 0
0 1 00 1
0 1 10 1
1 0 01 0
1 0 11 0
0 1 1
1
1 1

(Invalid State)
14
Asynchronous Bascule
__
S R QnQn+1 Qn+1
0 0 00 0
1 0 0 0 11 0
1 0 1 00 1
0 1 10 1
1 0 01 0
1 0 11 0
0 1
1

(Invalid State) Invalid state

15
Truth table S R Qn+1
0 0 Memorization
__ 0 1 0 (reset)
S R QnQn+1 Qn+1 1 0 1 (set)
0 0 00 1
Frozen Exit No action
0 0 11 0
0 1 00 1 Reset Reset
0 1 10 1
1 0 01 0
Put to 1 Set
1 0 11 0
1 1 00 0
State to avoid (Q)n+1 =n+1)
1 1 10 0

Outputs are always complemented, except for S = R = 1.

S R Qn+1
Frozen
0 1 0 (reset)
1 0 1 (set) 0 Set 0 0
S 0

R 0 0 0 Reset 0
1
Q 0 0 0
1 1 1
/Q 0
Setting to 1 Frozen Reset
 Qn+1 Output equation
Bascule RS SR
Qn 00 01 11 10
0 0 0 X 1 Qn+1 = S RQ+n
S R Qn+1 1 0 X
0 0 Memorization
0 1 0 (reset) State graph
1 0 1 (set) The internal states (Q) define the
vertices of the graph
Current state Next state The input states (R and S) define
the arrows leaving the summits
Qn Qn+1
SR=10
SR=00 01 10 11 1
0
0 00 1X SR=01
1 10 1X ["00","01"] 00, 10
Table of States
 Bascule S'R'
Bascule formed by two NAND gates by connecting their
outputs at the entrance of the other NAND gate.

S' S’ R’ Q
Q
1 1 No change
1 0 0 (reset)
Q' 0 1 1 (set)
R' 0 0 Prohibited

PS NS
S'R'Qn Qn Qn+1 Qn+
1 Current state Qn
01 XX 10 set NS: State following Qn+1
10X X0 1 reset
1 1 01 01 hold
1 1 10 10 hold
0 0X X1 1 forbidden
 RSH Bascule
An improvement of the RS flip-flop (latch) consists of adding a signal.
prohibiting or allowing the modification of the output. If this signal is 1, the state of
The output can be modified, otherwise it does not change regardless of the state of the inputs.
S and R.
S Q
C
R Q'

C= 1 we are in the normal operating case of the RS flip-flop.

 C= 1
Qn S R Qn + 1
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 indeterminate
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 indeterminate

S R Qn + 1
0 0 Qn mem
0 1 0 Reset C S R S ’ R ’ Q
1 0 1 Set 0 x x 1 1 memorization
1 1 undetermined 1 0 0 1 1 memorization
1 0 1 1 0 0 (reset)
Qn+1 =S+R'.Q n 1 1 0 0 1 1 (set)
WithS.R=0 1 1 1 0 0 undetermined
 Asynchronous D Bascule
A D flip-flop ('Data' or 'D') is actually an RS flip-flop.
particular, for which we always have D=S=R’.
D (“data”) and C (“control”).
When C = 0, S' = R' = 1, memorization. C D Q
0 x memorization
When C = 1, the output Q is equal to the input 1
D.
0 0
1 1 1

C D S R State Qn+1 Qn+1

0 0 1 1 Mem Qn Qn
0 1 1 1 Mem Qn Qn
1 0 10Reset 0 1
1 101 Set 1 0
D Flip-Flop with level control (Latch-D)
Its operation is simple: if C is equal to 0, the outputs Q and /Q keep their previous state.
(whether it is 0 or 1). If C is equal to 1, we have: Q=D and /Q=/D.
Cette bascule réalise une fonction mémoire de la valeur D. (C=1, écriture dans la mémoire).
 1*Q=Q
Bascule D 1/0 S 1/0 /1
D 1/0
Data Q
0/1 01
D Q H
1
H Q R What
01/ 10/
Logical symbol 0/1

H
Truth table
H D Qn+1 D

0 X Qn Q
1 0 0
When H = 1, Qn+1= D, mode transparent
1 1 1 In this case, if D changes, Q faithfully follows D.
Qinitial=0
When H = 0, Qn+1=n, locked outings
Bascule D H D Qn+1

Bascule D: copy switch. 0 X Qn

H=0: memorization mode 1 0 0
H=1: acquisition mode (copy D) 1 1 1
Differentiation of inputs:
D: data entry
H(Clock): control command input

Present state Next State

Qn Qn+1 D=1
D=0 1
0 0 1 0 1
1 0 1 D=0
D=0 D=1
 Bistable D flip-flop
Master Slave
Qm Qn
D D Q D Q
Clk
Clk H H
/Qn

Active master Inactive master Active master

Inactive slave Active slave Inactive slave

Master Slave

Clk=0, Qm+1active Clk=0, Qn+1=Qninactive

Clk=1, Qm+1=Qminactive Clk=1, Qn+1active

Operating principle:
At any moment, one and only one of the switches is active, the other is frozen.
Clk=0 Bascule 1 "Master" is active and flip-flop 2 "slave" is frozen.
Clk=1 Bascule 1 "Master" is frozen and Bascule 2 "slave" is active.
The 2 floors are therefore decoupled and thus prevent a direct propagation of the inputs on the
outputs.
Operating principle: Master Slave
At any time, one and only one of the switches QM QS
one works the other is frozen D D Q D Q

Clk H H
Clk=0, Qm+1Active master balancing beam. /QS
Clk=1Qm+1=QmFrozen master seesaw.

D Q
D Q
CLK

QM

QS Active bascule on front

amount of the clock,
Qs=D
Inactive master Active master
Active slave Inactive slave
 Synchronous Bascule D
Active at the front rising of Clk, Qn+1 = D
Front mount if not Qn+1 =n
D Clk Qn+1 Qn+1
D Q
0 0 1
Clk Q' 1 1 0
X 0QnQn

Clk
Front mounting
D
D
Q
Q
/
Q Q
 Synchro Bascule D: active on the falling edge
Master Slave
Qm Qs
D D Q D Q Q

Clock Clk Q Clk Q Q

(a) Circuit

Clock

D
Qm

Q = Qs

D Q

Q
Bascule D
Asynchronous Bascule D
D Q D
CLK
CLK

Transparent mode

Synchronous Bascule D
D

D Q CLK
CLK
Q

Active on the rising front

The JK flip-flop

J H
D Q K
K

H Q

D = J Qn+ K Qn At the rising front Qn+1 = D

JK
H JnKn Qn+1
1X
0X ↑0 0 Qn Memorization
0 1 X0
↑0 1 0 reset
X1 ↑1 0 1 set
↑1 1 /Qn Togle
No front
amount X X X Qn Memorization
 Bascule JK
J=K=0 fixed scale memorization
J=1 and K=0, the flip-flop sets the output Q to 1 on the rising edge of the clock.
J=0 and K=1, the flip-flop sets the output Q to 0 on the rising edge of the clock.
J=K=1 the state output Q changes after each subsequent rising clock edge.

J H JnKn Qn+1

↑0 0 Qn
K ↑0 1 0
↑1 0 1
↑1 1 /Qn
Q X X X Qn

set
toggle J=K=0 reset J= 1 K=0
J=K=1frozen J= 0 K=1
 Bascule T
T Q
T
J Q D
T Q H
H
K H

T=J=K H T Qn+1
D = T Qn+ T Qn
H=0, Qn+1 = Qn
x 0 Qn
H=0, Qn+1 =n 1 /Qn
H
J=K=1, Qn+1 = Qn
H , Qn+1 = D
J=K=0 , Qn+1 =n T = 0 D = Qn Qn+1 = T Qn+ T Qn
T T = 1 D = /Qn
0 1 0

0 1

1
 Preset and Clear: Forcing inputs
Allows the switches to be controlled independently of the clock signal H
Pr(preset) forces the output to 1, regardless of other inputs
Cr(Clear) forces the output to 0, regardless of other inputs.
Pr and Cr are not activated simultaneously.

? Pr Q ? Pr
H H
? Cr Q ? Cr Q

Cr and Pr are active at a low level Cr and Pr are active at a high level
Bascule D 7474
Preset
Data Pr Normal
D Q
Entry FF Exit
Clock CLK Q Complemented
CLR
Clear

Truth table
Operation Entries Outputs
Asynchronous Synchronous
Pr CLR CLK D Q Q
Asynchronous set 0 1 X X 1 0

Asynchronous reset 1 0 X X 0 1

Prohibited state 0 0 X X 1 1

Set 1 1 L to H 1 1 0
Reset 1 1 L to H 0 0 1
 Bascule D: Preset and Clear
Pr Preset active at low level => Qn+1 = 1
set asynchronous
D Q Clearactive at the low level => Qn+1 = 0
reset asynchronous
H
Q*

Cr
Pr Cr DnQn+1 H
0 1 X 1 D
1 0 X 0
Pr
0 0 X Forbidden
1 1 0 0 Clr
1 1 1 Dn Q
 Preset and Clear: asynchronous input
PRE PRESET
J Q Activate at level Q= 1
Clk
__
K Q CLR CLEAR

Active at low level Q = 0

Operation Appetizers Outputs

Print Clear Click J K Q n 1+Q’ n + 1
Seasytnchronziaoitn 0 1 x xx 1 0
Resetasynchronous 1 0 x xx 0 1
This is prohibited 0 0 x xx 1 1
-------------------------------------------------------------------------
Hold 1 1 0 0 Mem
Reset 1 1 0 1 0 1
Set 1 1 1 0 1 0
Toggle 1 1 1 1 Q n ' Qn
 Resume
PRE

Flip-flops J Q

CLK

Determine the output Q of the flip-flop

K Q
JK,
CLR

Set Toggle Set Reset Toggle Latch

CLK

K Set
PRE Reset
CLR

Q
 Resume

Bascule D
D Qn+1 Operation
0 0 Reset
1 1 Set Q n+1 = Dn

JK balance
J K Qn+1 Opération
0 0 Qn Mem
0 1 0 Reset Qn+1 K’Qn+ JQ’n
1 0 1 Set
1 1 Q’ n Complement

Bascule T
T Qn+1 Operation Qn+1 T’Qn+ TQ’n
0 Qn Mem = T Qn
1 Q’ n Supplement
Sequential Circuit

Often in SOP form

AND-OR logic

D
Often switches D but
we can have the 4 switches
(SR, JK, D or T) T

The number of toggles used

depends on the number of states J

39
 II Moore and Mealy Machine
Finite state machine: it is a machine that has a finite amount of memory
to represent the states.
There are two main categories of finite state sequential machines.
Moore Machine: Outputs depend only on the states.
S = g(Current_state)
Mealy Machine: Outputs based on states and inputs
S = f( Input, Current State )
A toute machine de Mealy correspond une machine de Moore et réciproquement

In a Mealy machine, a change in the inputs causes

immediately a variation of output
In a Moore machine, the output variations do not occur.
that at the moments of state changes.
Mealy machines are faster and have fewer states than the
Moore machines, but they transmit parasites.
Moore machines are simpler to design.
 Mealy and Moore machines

MyMooremachine

Starters Outputs
Circuit Flip Circuit
Combinatorics Flops Combinatorics

MyMealymachine

Starters Circuit Circuit Outputs

Flip
Combinatorics Flops Combinatorics
 The states are represented by circles with their names inscribed inside; the transitions
between the states are represented by directed arcs connecting the circles; the conditions
enchantment these transitions are noted on the arcs; and finally the value of the outputs is
usually indicated either on the arch (separated from the entries by a slash: /) or inside
of the circle (separated from the name of the state by a slash: /)

State diagram: Moore machine

X
0=

In the state graph of the Moore machine:

Y/Z each vertex corresponds to a present state y
each arrow corresponds to an input state x and
pointing to a future state yn+1
X
1= the output state z is indicated at the vertices

State diagram: Mealy machine

ZX
/0=

each vertex corresponds to a present state y

Y each arrow corresponds to an input state x and
points to a future state yn+1
the exit state z is indicated on the arrows
ZX
/1=
 Diagrams, Tables, and State Variables

To design a sequential circuit

o We determine the total number of internal states (the
different states through which the circuit goes that will need to
manipulate
o A symbol is assigned to each state.

The operation of such a circuit can be represented schematically by

a state diagram where the internal states are indicated and the
transitions between these states
Implementation using JK flip-flops
Excitation table
A truth table does not provide enough information about the past of the flip-flop. A
The transition table does not concern itself with the output based on a particular state of
the input, but in the state of input necessary for a particular transition of the output.
JK Flip-Flop Excitation Table

Truth table Excitation table

J K Qn Qn+1 QnQ n+1 J K Operation

0 00 0 X Frozen/reset
0 0 1 1 1 X Set/complement
0 10 X 1 Reset/complement
0 11 1 1 X 0 Frozen/set
1 00
1 0 1 1
1 10
1 11
 Implementation using D, T, RS, and JK flip-flops

Excitation table of D, T, SR, JK flip-flops

Excitation tables

QnQn+1 D TS RJ K

0 0 0 00 X0 X
0 1 1 11 01 X
1 0 0 10 1X 1
1 1 1 0X 0X 0
 II 1 The FSM method

For the design of a sequential circuit, one must follow the steps
below

1. Specify the problem

2. State diagram
3. State Minimization
4. State attribution
5. Transition table
6. Design equation
7. Implementation of the circuit
 Example 1: modulo 4 counter / Implementation at
the help of JK flip-flops

Let the following state diagram correspond to a modulo 4 counter with a

entry X.
0
X= 0 frozen 2. State diagram
00
X=1 count State Following state
1 1 present x=0 x=1
+ + + +
0 QA QB QAQ BQAQB
0 0 0 00 1
0 0 1 0 1 1 0
1 0 1 0 1 1
1 1 1 1 1 0 0
1

0
We learn to convert a state diagram into equations of
recurrences. This is done very simply using a state table
present/future state.
 Example 1 continuation
. Sequential circuit
QA’QA QB'QB

K K
Clk
KA JA KBJB

4 states 2 JK scales QA' circuit Exit

QA
QB Combinatorics
QB'
x
Entry
Circuit at
to conceive?
It is important to understand the role of this combinatorial circuit:
calculate the future state from the present state.
It is necessary to use the JK flip-flop excitation table to find the
recurrence equations on J and on K.
Example 1 continuation State State Inputs of the toggles
present Entry Next JK

Transition table QAQB x QA + QB + J AK A J BK B

0 0 0 X 0 X
Q Q +
J K 00 1 0 1 0 X 1 X
01 0 0 1 0 X X 0
0 0 0 X 01 1 1 0 1 X X 1
0 1 1 X 10 0 1 0 X 0 0 X
1 0 X 1 10 1 1 1 X 0 1 X
11 0 1 1 X 0 X 0
1 1 X 0 X 1
11 1 0 0 X 1

. Design equation

Q Bx QB
QA 00 01 11 10
0 X X1
QA 1 X X 1

x
 Example 1 Continued

. Sequential circuit
JA=KAQBx JB=KB= x
 Implantation using T switches
0

00 State State Entry of the

Present Entry following Scales
1 1 QAQB x QAQ+
B
+
TA TB
0 00 0 0 0
00 1 0 1
01 0 0 1
0 01 1 1 0
10 0 1 0
1
1 10 1 1 1
11 0 1 1
11 1 0 0
0
Bascule T Bascule JK for T=J=k
QA
QB
Qn Qn+1 J K T

0 0 0 X 0
0 1 1 X 1
1 0 X 1 1 Clk
1 1 X 0 0
TAQBx,TB=x
x 51
 Implementation using D flip-flops
0
State State Entry of
00 present Entrance following Scales
+ +
QA QB x QAQ B DADB
1 1 00 0 0 0 00
0 00 1 0 1 01
01 0 0 1 01
01 1 1 0 10
0 10 0 1 0 10
10 1 1 1 11
1
1 11 0 1 1 11
11 1 0 0 00

Q Bx QB
QA 00 01 11 10 A Bx QB
0 1 QA 00 01 11 10
0
QA 1 1
QA 1
x
x
DA=A .QB + xQA'QB+QA x' DB=B .x + QB .x
= QB xor QA
Example 1 DA=A .QB + xQA'Q B+QA x'
DB=B .x + QB .x

. Sequential circuit:

QA .QB ‘

D Q QA
QA .x
x
xQA’.QB Q' QA '

D Q QB

Q' QB '
Clk
Example 2
Moore machine recognizing the sequence 10
S0No element of the sequence
S11 observed 0 1
S210 observed reset 0
1
S0/0 S1/0 1 S2/1
Machine de Mealy
S0No element of the sequence 0
S1"1" observed 0/0 1/0 1/0

S0 S1

reset 0/1
 Moore & Mealy Chronogram

Clock
0 1 0 0 0
Entry

Moore S0 S1 S2 S0 S0

Mealy S0 S1 S0 S0 S0

0 1 0/0
0 1/0 1/0
1 S1/0
S0/0 1 S2/1 S0 S1
reset reset 0/1
0
Example 3: 101 Sequence Detector

w Z

Clock

X = 0 0 11 0 11 0 01 0 101 0 10 0
Z = 0 0 0 0 010 0 0 0 0101010 0

Z=1whenasequence101isdetectedattheinput
duringthelastthreecyclesoftheclock,ifnotz=0
 0/0
Mealy
None No element of the sequence is detected
Sequence to detect: 101
1/0 1/0

0/0 a An element of the sequence is detected

1/1 0/0

two Two elements of the sequence are detected.

State Next state Z

Present w= 0 w= 1 w= 0 State
w= Code
1
Q1,n Q0,n
Nonenoneone 0 0
A two one 0 0 None00
two none a 0 1 A 0 1
Two 1 0
Codingtable
Statetabled
Q1,nQ0,n Q1,n+1Q0, n+1
state nextstate Z D1D0 wQ1,n
present w= 0 w= 1 w= 0 w= Q0,n1 00w=01 110 10 w= 1
00 01 0 000 01 0
00
01 10 01 0 010 01 1 XX
10 00 01 0100 01 Z = Q1,nw

w Z
w Q1,n
Q0,n 00 01 11 10
0
Q0 1
D0 XX 1
CK
D 0= w
Q1
wQ1,n
D1 Q0,n 00 01 11 10
CK
Clock 0
D1=0,nw
1
 Sequence 101
Mealy diagram
0/0
0 State State following Z
Present w= 0 w= 1
none Z=0
none
Nonenoneone0
1/0 1/0 A two one 0
1 1
two none found 0
0/0 un Trouvé deux un 0
0 a Z=0
1/1
0/0
0
State Code
two 1 Q1Q0
two Z=0
none 00
0 1
a 01
found two 10
Z=1 found 11
Moore diagram
 Q1
Current State Following state Z 0 1
Q1,n Q0,n Q1,n+1Q0,n+1 D1 D0 Q0
0
w= 0 w= 1 w=0 w=1
Z = Q0Q1
1
00 00 01 000 01
01 10 01 010 01 wQ1
10 00 11 000 11 Q0 00 01 11 10
11 10 01 110 01 0
D0= w
1

Q0 Z
w D0
CK wQ1
Q0 00 01 11 10
0

1
Q1
D1
CK

D1=0w + Q0Q1w
Clock
 Sequence detector circuit: Mealy and
Moore
Mealy Moore
w Z

X Q0
D0 Z
CK
Q0
D0
CK

Q1
Q1
D1
D1
CK
CK
Clock

Clock

D0= X D0= X
D1Q0X’
D1= Q0X’ + Q0'Q1X
Z = Q1X
Z= Q0Q1
 IV Binary counters
Asynchronous binary counter

In this type of structure, the impulse for progression of

counter is applied to the clock input of the first stage,
the clock inputs of the other flip-flops receive the signal from
exit from the previous floor.

Synchronous binary counter

In the synchronous structure, the clock is the same for everyone.

the levels: the tilting of all the scales occurs in
same time
 Named references
CTR counter
Distinctive symbol of meters CTR DIV m: counter-timer by
m or modulo m
Counting entry Increment the counter output by 1.
Counting entry DOWN: Decrements the output of the counter by 1.
End of counting cycle output CO: Carry. Status indicating that the Counter is full.
End of counting cycle output BO: Borrow. State indicating that the meter is empty
Validation entry EN, CTEN, CE, OE: Validate the circuit, the outputs
Entrée d’horloge CLK, H: Signal permettant l’évolution des sorties
Dynamic entry Internal state = 1 on the rising edge of the signal
Dynamic input with negation O Internal state = 1 on the front
logic descendant of the signal
H: high level (stable)
L: low level (stable)
X: indifferent level
Symbol of the tables of you descending flank or front
of the signal (transition from H to L.
operation
you flank or ascending front
of the signal (transition from L to H).
Asynchronous counters modulo 2n(in scales)
Full cycle counters
. Example: modulo 4 counters (n = 2 bits).(0 1 2 3 0…..)
1
J Q0 J Q1
CLK C C
Q0

FF0 FF1

CLK 1 2 3 4

Q0 0 1 0 1 0
Q0= CLK÷2
Q0 Q1= CLK÷4
Q2= CLK÷8
Q1 0 0 1 1 0
Q3= CLK÷16
Q1Q0 00 01 10 11 00 ...
 clk q0 frequencyf/2
(freq.f) counter q1 frequencyf/4
q2
n-bit frequency f/8

qn-1 frequency f/2n

Asynchronous counters modulo 2n(in scales)
Full cycle meters
. Example: Asynchronous counter modulo 8 (n = 3 bits).
HIGH

J Q0 J Q1 J Q2
CLK C Q0 C Q1 C

FF0 FF1 FF2

CLK 1 2 3 4 5 6 7 8

Q0 0 1 0 1 0 1 0 1 0

Q0

Q1 0 0 1 1 0 0 1 1 0

Q1

Q2 0 0 0 0 1 1 1 1 0

Q[2..0] 0 1 2 3 4 5 6 7 0
Asynchronous counters modulo 2n(in scale)
Full cycle counters
. Example: Asynchronous counter modulo 16 (n = 4 bits)
HIGH
Q0 Q1 Q2 Q3
J J J J
CLK C C C C

FF0 FF1 FF2 FF3

CLK 1 2 3 4 5 6 7 8

Q0

Q1

Q2

Q3

Q[3..0] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 Decimalvalue
 Frequency Divider Counter
CLK 1 2 3 4 5 6 7 8
Q0 0 1 0 1 0 1 0 1 0

Q1 0 0 1 1 0 0 1 1 0

÷4
÷8 200Hz
100Hz 400Hz
50Hz ÷2
16
Clock

800Hz
Modulo 8 counter: JK flip-flop
In the case of JK flip-flops, taking J = K = 1, we get Qn+1 =/Qn .

Clk
1 J Qa 1 J Qb 1 J Qc
Clk Clk Clk
1 K Qa 1 K Qb 1 K Qc
Top QcQbQa
0 1 2 3 4 5 6 7
0 0 0 0

1 0 0 1

2 0 1 0
Qa at the front descending from the clockQa,n+ 1 =/Qa,n Togle.
3 0 1 1
By
At connecting another Jk flip-flop
the descending front of to the
Qaoutput of1Q/Q toggle.b,n
:Qb,n+ a
4 1 0 0
Qb
5 1 0 1
If we
At connect
the a 3ièmebascule
descending b: Qexit
frontJkofatQthe c,n+1=of/Q
Q,toggle.
we c,n
will have:
b
6 1 1 0
Qc
7 1 1 1
For the first 7 impulses of the clock, we have the following table.

This table represents a MOD 8 counter. The counter returns to 000 at 8.ièmeimpulse of
the clock
If we connect the three outputs Qa, Qb, and Qc to 3 LEDs, this represents a counter that counts.
from 0 to 7.
Counter Mod 8:
If this time we connect each output /Q of the flip-flop i to the input clk.
bascule i+ 1. We obtain a modulo 8 counter.

Input
1 J Qa 1 J Qb 1 J Qc
Clk Clk Clk
1 K Qa 1 K Qb 1 K Qc

In QcQbQa

0 0 0 0

1 1 1 1

Qa 2 1 1 0

3 1 0 1

The 4 1 0 0
5 0 1 1

6 0 1 0
Qc
7 0 0 1

If we place LEDs at the output of each flip-flop, we will have.

Asynchronous modulo 2 counter / decodern
. Example: counter / decrementer (MOD-23(With an Up/Down entry)

Up/Down = 0 counting function

HB=A
1
Q0 Q1 Q2
J Q J Q J Q
CLK C C C
Q' Q' Q'

Up/Down = 1 counting function HB= /QA

1
Up/Down Clk
Q0 Q1 Q2
J Q J Q J Q
CLK C C C 0 Q
Q' Q' Q'
1 /Q

Clk = Up/Down*Q + Up/Down*Q

Up/Down Counter :

Clk = Up/Down * Q + Up/Down * Q

1 J Qa 1 J Qb 1 J Qc
Clk > Clk Clk
1 K Qa 1 K Qb 1 K Qc
Qa•1 Qb•1

Up/Down

WhentheUp/Downinputis0,theclockClkisconnectedtotheoutputQoftheflip-flop.
preceding.
[Link]

When the input Up/Down = 1, the clock Clk is connected to the output Q of the
preceding bascule.

The counter is counting down.

 Asynchronous counters modulo N < 2n
Incomplete cycle counters

Initialization and positioning of the meters

Very often, it is appropriate to position the outputs of the meter

way to know the initial operating condition of the
structure. This function is performed from inputs
initialization that forces all outputs to logical state 0
(CLR, Clear, RAZ, RESET…) or to 1 (SET, RAU…) and inputs
pre-positioning (LOAD) that allows to "load" in
output a binary word (0101 for example for a 4-bit counter).
These entries are most often asynchronous.
 Asynchronous counters modulo N < 2n
Incomplete cycle counters
Use of the /PRESET or /SET entry to reset the counter in
the starting state
We detect the value N and use it to reset the counter to zero.

C B A
Q J Q J Q J
Allentries CLK CLK CLK
JetK are at Q Q Q
CLR CLR CLR
high level
B
C
N Detector
….

Clr
 Asynchronous counters modulo N < 2n
Incomplete cycle counters
CBA . Example 1 modulo 6 counter:
000
001 610=1102CBA When CB=11 reset the counter to 0
010 C B A
Q J Q J Q J
011
100 CLK CLK CLK
101 Temporary state Q Q Q
CLR CLR CLR
necessary for the All the
reset of the B entréesJ,K
compteur C sont au niveau
1 (HIGH).
1 2 3 4 5 6 7 8 9 10 11 12
Clock
The doorNand
A put back the output
at 000 when the
B value (110)
appears at the
C exit
Exit 1
NAND 0
 n
Asynchronous counters modulo < 2

1 2 3 4 5 6 7 8 9 10 11 12
Clock
A 0 1 0 1 0 1 0 1
B 0 0 1 1 0 0 0 0
C 0 0 0 0 1 1 0 0
NAND 1
Output 0

Although the counter goes to state 110, it's barely a few nanoseconds.
before its recycling at 000
111 000
State 001
Temporary
CounterMOD-6.
110 010

101 011
100

Modulo 6 counter obtained by resetting a modulo 8 counter to 0

quand le contenu du registre atteint six (110)
 Asynchronous counters modulo < 2n

What function is performed by this circuit?

F E D C B A
Q J Q J Q J Q J Q J Q J

Q Q Q Q Q Q
CLR CLR CLR CLR CLR CLR

C
D
E All entries J, K
F
are at 1
When FEDC = 1111: Clr = 0
 n
Asynchronous counters modulo < 2

. BCD counters: "or modulo 10 counter, or decade counter"

. 0000 0001 0010 0011 0100 0101 0110 0111 1000 1
001: 10 states (modulo 10).

1010=10102ABCD When AC=11 reset the counter to zero

ie Clr = (AC)'
(A.C)'

HIGH
D C B A
J Q J Q J Q J Q

CLK C C C C

CLR CLR CLR CLR

 n
Asynchronous counters modulo < 2
. BCD counters
HIGH D C B A
J Q J Q J Q J Q (A.C)'
CLK C C C C
CLR CLR CLR CLR

1 2 3 4 5 6 7 8 9 10 11
Clock
D 0 1 0 1 0 1 0 1 0 1 0
C 0 0 1 1 0 0 1 1 0 0 0
B 0 0 0 0 1 1 1 1 0 0 0
A 0 0 0 0 0 0 0 0 1 1 0
Exit
NAND
 Cascaded asynchronous counters
. The term cascade indicates that one can put several in succession.
counters, ultimately allowing for a larger counter to be obtained
capacity
. Example: A modulo 32 counter can be built from a
cascade modulo 8 counter with a modulo 4 counter.
Q0 Q1 Q2 Q3 Q4

J J J J J
Q Q Q Q Q

CLK C C C C C
Q' Q' Q' Q' Q'

counters Count +1
modulo 8
modulo 4

The MSB of counter i is applied to the clock of counter i+1

Each time a counter resets to 0, the next counter is incremented.
 Decade counter
freq/10
1 CTEN Counter
every decade TC
CLK C Q3Q2Q1Q0
freq

The T exitCindicate when the counter is at 9, that is (1001)2

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0
Clk

Q0 0 1 0 1 0 1 0 1 0 1 10 0 1 10

Q1 0 0 1 1 0 0 1 1 0 0 11 0 0 11
Q2 0 0 0 0 1 1 1 1 0 0 00 1 1 11
0 0 0 0 0 0 0 0 1 1 11 1 1 11
Q3
Asynchronous counters in cascade
. Example: Modulo 100 counter
Theend-of-countoutputTCallows the cascading of
counter. We then obtain a counter modulo the powers of
Units Dozens
freq/10
1 CTEN Counter CTEN Counter freq/100
per decade TC to decade TC
CLK C Q3Q2Q1Q0 C Q3Q2Q1Q0
freq

TC= 1 when the unit counter returns to 0

CTEN=1 Counting

A BCD counter is obtained by cascading the

modulo 10 counters (decade counters)
 Synchronous counters
. Example: 2-bit synchronous binary counter (using)
T flip-flops, or JK flip-flops with J and K inputs at the same time
level.
State State Entries From QnQn+1 T
present following scales
00 01 + + 0 0 0
Q1Q0Q1Q0 T1 T0
0 0 01 0 1 0 1 1
0 1 10 1 1 1 0 1
11 10
1 1 0
1 0 11 0 1
1 1 00 1 1

Q0
Logic 1 Q1
T1=Q0
T0 = 1
Clk

Clk

Q0
Q1
Using JK flip-flops

State State Entries From 1

present following scales
+ + Q0 J Q1
Q1Q0Q1Q0 J1K1J 0K0 J Q Q
0 0 01 C C
0 1 10 Q' Q'
1 0 11
1 1 00 CLK

Using a T flip-flop and a D flip-flop

State State Entries From
présent suivant bascules
+ +
Q1Q0Q1Q0 T D
0 0 01
0 1 10
1 0 11
1 1 00
Qn Qn+1 D TS RJ K

0 0 0 00 X0 X
0 1 1 11 01 X
1 0 0 10 1X 1
1 1 1 0X 0X 0
 Synchronous counters
. Example: 3-bit counter (using T flip-flops, JK flip-flops)
with J and K inputs at the same level). Q1

State State Entries of T2=1.Q0

present next T Scales Q2
Q2Q1Q0 Q2Q1Q0 +
+ +
T2T1T0
0 0 0 001 001 Q0
Q1
0 0 1 010 011
0 1 0 011 001
0 1 1 100 111 T1=0
Q2
1 0 0 101 001
1 0 1 110 011 Q0
Q1
1 1 0 111 001
1 1 1 000 111 1 1 1 1
T0=1
Q2 1 1 1 1
Q2 Q1 Q0
Q0

T2 T1 T0
Clk
1
. 3-bit counter with JK flip-flops
State State Entries of
present following JK Scales
+ + +
Q2Q1Q0Q2Q1Q0 J 2K2J 1K1J 0K0
0 0 0 001
0 0 1 010
0 1 0 011
0 1 1 100
1 0 0 101
1 0 1 110
1 1 0 111
1 1 1 000
Q2 Q1 Q0

J J J
Clk
1
 Synchronous counters
. Note: In a binary counter, the nth bit (underlined in blue) is always
supplemented
011...11 100...00
ou111…11 000…00
. So, Xnis complemented if Xn-1Xn-2 ... X1X0= 11…11.
. As a result, if we use T flip-flops, then
Tn= [Link]-2.....X1.X0
Exemple n=3
Clock Q2Q1Q0 Q1change Q0changes with each cycle
0 0 0 0
Q2change Le bit Q1change when Q0=1
1 0 0 1 So T1=Q0
The Q bit2change if Q at the same time1and Q0
2 0 1 0
are equal to 1.
3 01 1
So T2=Q1Q0
4 1 0 0
In general, for an n-bit counter,
5 1 0 1
a switch changes state if the
6 1 1 0 the states of the previous switches are
7 11 1 in state 1.
8 0 0 0 Ti=Qi-1Qi..Q0
Example 4
Complex counter: Sequence 000 010 011 101 110 000
Present state Next state Entry of the toggles
State diagram
QC,nQB,nQA,nQC,n+1QB,n+1QA,n+1 TCTBTA

000 010
0 0 0 01 0 0 1 0
0 0 1 X XX XXX
110 011 0 1 0 0 11 0 0 1
0 1 1 1 0 1 1 1 0
1 0 0 X XX XXX
101 1 01 1 10 0 1 1
1 1 0 0 00 1 1 0
Excitation table Table of states
1 1 1 X XX XXX
QnQn+1 T
000 QBQA QBQA QBQA
011 QC 00 01 11 10 QC 00 01 11 10 QC 00 01 11 10
101 0 0X 1 0 0 0 0 X 0 1
110
1 X 0 X 1 1 1

TB=QA+QB' + QC TA=QA'QBQC' + QB'QC

TC=QA QC
 QA’
QA QB
QB’ TB QC’
QC
TA

QB’
QA
TC QC
QC

TC QC TB TA
TS TS QB TS QA
CLK CLK CLK
R R R
1
Count 0
/Reset
Example 5
BCD decade counter: T flip-flops

. Example: BCD decade counter using T flip-flops

T01
T1=3'.Q0
T2=Q1.Q0
T3=Q2.Q1.Q0 +Q3.Q0

Q0

1 T T Q1 T Q2 T Q3
Q Q Q Q
C C C C
Q' Q' Q' Q'

CLK
 Synchronous Counters/De-counters

. Example: 3-bit synchronous binary counter/decrementer

Clock pulse Up Q2Q1Q0Down
Up=1 Account
0 0 0 0
Up=0 Countdown 1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1

T0= 1
T1= ([Link]) + ([Link]
T2=[Link]) + ([Link]
 Synchronous Counters/De-counters

. Example: 3-bit synchronous binary counter/decrementer

T0= 1
T1= ([Link]) + ([Link]
T2([Link]) + ([Link])

Q0 Q1

1T T T Q2
Q Q Q
Up C C C
Q' Q' Q'

CLK
 3-bit Gray code counter: JK flip-flop
000
. Example: 3-bit gray code counter 100 001
using JK flip-flops.
101 011

111 010
110
State State Entrance of
present following scales
Q2Q1Q0 Q2Q1Q0 +
+ +
J 2K 2J 1 K 1J 0K 0
0 0 0 001 0 X0 X1 X
0 0 1 011 0 X1 XX 0
0 1 0 110 1 XX 0 0 X
0 1 1 010 0 XX 0X 1
1 0 0 000 X 1 0 X0 X
1 0 1 100 X 0 0 XX 1
1 1 0 111 X 0X 0 1 X
1 1 1 101 X 0X 1X 0
 Gray code 3-bit counter: JK flip-flop

. Example: 3-bit gray code counter (in

using JK flip-flops.

Q1 Q0 Q1 Q0 Q1 Q0
Q2 Q2 00 01 11 10 Q2 00 01 11 10
00 01 11 10
0 0 0

1 X X XX 1 X X 1 XX 1

J 2Q1.Q0' J 1=2'.Q0 J 0 =2.Q1+Q2'.Q1'

=2Q1)'
Q1 Q0 Q1 Q0 Q1 Q0
Q2 00 01 11 10 Q2 00 01 11 10 Q2 00 01 11 10
0 0 X X 0 X
1 1 XX 1 1 X

K 2=1'.Q0' K 1Q2.Q0 K 0=2.Q1+Q2.Q1

=2 Q1
 Gray code 3-bit counter: JK Flip-Flop

. Gray code counter 3 bits.

J2= Q1.Q0' J1=2'.Q0 J0=(Q2 Q1)'
K2= Q1.Q0' K1Q2.Q0 K0=2 Q1

Q0 Q1 Q2
J Q J Q J Q
C C C
Q1 Q2
K Q' K Q' ' K Q' '
Q0
'
CLK