Module 2
Sl.
No.
Differentiate between a Demultiplexer and Multiplexer.
1
Obtain the logical expression for sum and carry for a
2 half adder.
Multiplexer's another name is “Data Selector” – examine this statement.
3
4 Differentiate between encoder and decoder.
5 Differentiate between demultiplexer and decoder.
Differentiate between a combinational and a sequential circuit with the help of suitable block
6 diagrams.
Construct the basic block diagram of a 4:1 Multiplexer (with all notations available).
7
8 What is a magnitude Comparator?
Construct the basic block diagram of a 2-bit magnitude comparator.
9
Formulate the truth table for a half Subtractor and also obtain the expression for difference
10
and borrow.
Construct the block diagram of a 4:2 priority
11 encoder.
12 Design a 1-bit Priority encoder circuit.
13 Design a Half adder using NOR gates only.
14 Design a Half adder using NAND gates only.
15 Discuss the function of select lines in multiplexer.
Explain the differences between even parity and odd parity.
16
17 Explain the need for enable pin in Multiplexer.
Construct the following circuit using multilevel NAND-NAND structure: Y = A+ (B+C’)
18
(D’E+F)
19 Define K-Map or Karnaugh Map.
20 Write about parity generator.
21 Define parity checker.
22 State the purpose of ‘carry in’ input in Full Adder.
23 Design a half subtractor using ‘NOR’ Gates.
24 Design a half subtractor using ‘NAND’ Gates.
What is the functional difference between a half adder and a full adder?
25
How many outputs do you get from a half-subtractor circuit? What are these?
26
State the difference between encode and priority encode.
27
28 What do you mean by Buffer?
29 Find the 2’s complement of 1001001.
Obtain the octal number of the given hexadecimal number A72E16.
30
Reduce the following Boolean expressions to five literals.
1 ABC + A'B'C + A'BC + ABC' + A' B'C'
Demonstrate the validity ofIhe following identities by means of truth tables: (a)
2 DeMorgan'stheoremfor three variables: (x + y + z)' = x'y'z'
Name the universal gates. Implement NOT, AND, OR using any one of the universal gates.
3
Find the complement of the following expressions: (A'B + CD)E' + E
4
Implement the Boolean function F = xy+x'y'+y'z
5 with AND, OR, and inverter gates.
Simplify the expression Z(P, Q, R) = ∑m(1, 3, 6, 7) using K-
6 maps
Simplify the expression F (A, B, C, D) = ∑m(0, 2, 5, 7, 8, 10,
7
13, 15) using K-maps.
8 Simplify the expression F (P, Q, R) = π(0,3,6,7) using K-maps.
9 Simplify the expression F (P, Q, R, S) = π (3, 5, 7, 8, 10, 11, 12, 13) using K-maps.
Draw logic diagrams to implement the following Boolean expressions:
10 Y = A + B + B'(A + C)
Draw logic diagrams to implement the following Boolean expressions: Y = A(B xor D) +
11
C'
Simplify the following Boolean functions TI and T2 to a number of literals:
14
Express the following function as a sum of minterms and as a product of maxterms:
15 F(A,B,C) =B'C + A' + AB
Obtain the simplified expression in sum of products for the following boolean function:
16 D(A' + B) + B'(C + AD)
Obtain the simplified expressions in sum of products for the following Boolean
17 functions: F(w,x, y, z) = ∑m(2, 3, 12, 13, 14, 15)
Write Boolean expressions and construct the truth tables describing the outputs of the circuit
described by the following logic diagrams:
18
19 Implementation of F= A(B + CD) + BC' with NAND gates
20 Implementation of (A+ B')(CD + E) with NAND gates
Design and explain the working of a 4-bit Binary to Gray code converter
21
Design a combinational circuit whose input is a four-bit number and whose output is the 2's
22 complement of the input number.
Implement a full-subtractor with two half-subtractors and an OR gate.
23
Show how a full-adder can be converted to a full- subtractor with the addition of one
23
inverter circuit.
Determine the Boolean function for the output F of the circuit
24
Judge how you can cascade two 2:4 decoders to make one 3:8 decoders.
25
Simplify the boolean expression and draw the logic circuit diagram: (AB'(C+BD)+A'B')C
26
Find the boolean expression for the logic circuit shown below: (1-NAND Gate, 2-NOR Gate,
3-NOR Gate)
27
Simplify the following Boolean function in sum of products using K-Map: F(w,x,y,z)=
28
∑m(0,1,2,5,8,9,10)
Design and explain the working of a 4-bit Binary to Gray code converter.
29
Design a 4-bit Gray to Binary code converter along with the truth table.
30
Reduce the following function using K map technique,
31
F (W,X,Y,Z) = ∑m(1,3,7,11,15) + ∑d(0,2,5)
What do you mean by Standard Canonical form? Simplify using K- Map method:
32 F(W,X,Y,Z)=∑ m(0,2,3,6,7,8,10,12,13)
1. Reduce the following expressions using Boolean algebra:
a. (A+B+C) (A+B’+C) (A+B+C’)
33
b. XY+XZ+YZ’
Prove the following expressions using Boolean algebra:
34 a. A+ A'B + AB' = A + B
b. AB + A'B + A'B' = A' + B
Realize the following equation: AB + CD
35 a. Using AND gate and OR gate
b. Using only NAND gate
Realize the following equation: (A + B) (C + D)
a. Using AND gate and OR gate
36
b. Using only NOR gate
Which combinational circuit do you use to convert binary information from n input lines to a
41 maximum of 2n unique output lines? Give a brief analysis on that.
Which combinational circuit selects binary information from one of many input lines and
42 directs it to a single output line? Give a brief analysis on that.
A 3-to-8 decoder can be used for binary-to-octal
43 decoding. When 101 is on the inputs, analyze which output line will be activated?
Evaluate the operation of a full-adder circuit with a decoder and two OR gates
44
Implement the expression of Sum of Full Adder using 4:1 MUX.
45
Implement the expression of Carryout of Full Adder using 4:1 MUX.
46
How to implement a full adder by using two half adders?
47
Implement a 3-bit Parity Checker circuit using logic gates
48
Simplify the expression in the following logic circuit and implement. the simplified
expression
49
50 Construct 16:1 Mux using 4:1 Mux.
Express the Boolean function F = xy + x'z in a product of maxterm form.
51
a) Design a 16: 1 MUX using 2:1 MUX . Draw and explain the circuit.
1 b) Evaluate a full subtractor using two half subtractors.
a) Design the circuit of a 4:2 priority encoder with output indicator.
b) Draw the circuit of XOR gate using only NAND gates.
2
a) How Parity Generator works? Construct 3 bit Odd Parity Generator.
b) Draw and explain the logic diagram of a full adder using only NAND gate.
3
a) Draw and explain the logic diagram of a full subtractor using only NAND gate.
4 b) Evaluate the full adder circuit using 3:8 decoder.
a) Implement Borrow of Full subtractor using 4:1 multiplexer.
b) Reframe the logic diagram of a Half Subtractor using only NAND gates.
5
a) Reframe and explain the 3-to-8-line decoder using basic gates only.
b) Reframe and explain the logic diagram of a half adder using only NOR gates.
6
a) Implement 4:1 MUX using 2:1 MUX. Explain how the selection lines are determined.
7
Design 2 bit magnitude comparator circuit using logic gates.
8
Design a combinational circuit that takes a 4-bit binary input (A3 A2 A1 A0) and produces a
3-bit binary output (B2 B1 B0) according to the following rules:
1. If the input is divisible by 3, the output should be the binary representation of the quotient
(A3 A2 A1).
2. If the input is not divisible by 3, the output should be the binary representation of the
9 remainder when divided by 3.
Provide the truth table, logic diagram, and the simplified Boolean expressions for each output
bit (B2, B1, B0) in terms of the input bits (A3, A2, A1, A0).
An 8-to-1 MUX has inputs A, B, and C connected to the selection inputs S2, S1 and S0
respectively. The data inputs D0 through D7 are as follows: D1=D2=D7=0; D3=D5=1; D0=
10 D4=D; D6= D’. Determine the Boolean expression that MUX implements.
Convert the following SOP expression to an equivalent POS expression.
11 ABC + AB’C’ + AB’C + ABC’
Design and explain the logical circuit for BCD to Decimal Decoder.
12
Design a BCD-to-seven-segment decoder. Derive the
13
expression from the truth table and K-Map.
Implement the following function using a multiplexer.
14
F (A, B, C, D) = Σm (0, 1, 3, 4, 8, 10, 15)