FPGA/ASIC DV
=== screen ===
- describe a really bad bug and how you resolved it
- when is verification complete?
- how would you gain confidence in a design if you didn’t have access to
code/functional coverage?
- what are the pros and cons of UVM?
- write a C program to determine the endianness of the system
- take-home assignment. given a DUT, write a testbench and tests using cocotb
=== on-site ===
- take-home assignment code review
- write a test plan for the following:
- 2 LIFOs and a FIFO with fulla nd empty signals
- ingress packets are assigned to LIFOs or FIFO, determined by packet header
- egress packets are read from LIFO 1 then 2 then FIFO
- LIFOs eject packets after timeout
- write a test plan for the following:
- streaming packetized interface
- signals: data, valid, start, end, empty, halt
- leetcode: [Link]
where-n-digits-are-divisible-by-n-sunday-puzzle/
- leetcode: more complicated version of [Link]
duplicate-number/discuss/704693/Python-2-solutions%3A-Linked-List-Cycle-O(n)-and-
BS-O(n-log-n)-explained
- leetcode: [Link]
complementary/
- leetcode: [Link]