⭐ UNIT 1 – Boolean Algebra and Simplification Techniques

1. Boolean Algebra
Boolean Algebra is a mathematical system used to represent and
simplify **digital circuits**.
It uses only two values:
✔ 0 (LOW)
✔ 1 (HIGH)

1.1 Basic Operations**

(a) AND ( · )
* Output is 1 only when both inputs are 1
* Symbol: A · B
**Example:**
1·1=1
1·0=0

(b) OR ( + )
* Output is 1 when any one input is 1
**Example:**
1+0=1
0+0=0
(c) NOT ( ̅ )
* Reverses the input
A̅
**Example:**
1̅ = 0
0̅ = 1

1.2 Basic Laws of Boolean Algebra

1. Identity Law
*A+0=A
*A·1=A

2. Null Law
*A+1=1
*A·0=0

3. Idempotent Law
*A+A=A
*A·A=A

4. Complement Law
* A + A̅ = 1
* A · A̅ = 0

5. Double Negation
* (A̅)̅ = A
1.3 DeMorgan’s Theorems
DeMorgan's Theorems are two fundamental laws in Boolean algebra
that provide equivalencies between AND, OR, and NOT operations
**Rule 1**
(A · B)̅ = A̅ + B̅

**Rule 2**
(A + B)̅ = A̅ · B̅

⭐ Example
Given:
Y = (A + BC)̅
Apply Rule 2:
Y = A̅ · (BC)̅
Again apply Rule 1:
Y = A̅ · (B̅ + C̅)

2. Signed Binary Number Representation

Signed numbers are used to represent **positive and negative numbers
in binary.
2.1 Signed Magnitude
* MSB (Most Significant Bit) = Sign bit
✔ 0 = positive
✔ 1 = negative
* Remaining bits → magnitude
# Example
+5 = 0 101
-5 = 1 101

2.2 1’s Complement**

* Positive number → normal binary
* Negative number → invert all bits (0→1, 1→0)

Example
+7 = 0111
-7 = 1000 (invert 0111)

2.3 2’s Complement**

* Negative number = 1’s complement + 1
### Example
+5 = 0101
1’s complement → 1010
Add 1 → **1011 (2’s complement of –5)**

#3. SOP and POS Forms**

3.1 SOP (Sum of Products)**
* AND terms added using OR
* Example:
F = A̅B + AB̅

3.2 POS (Product of Sums)**

* OR terms multiplied using AND
Example:
F = (A + B̅)(A̅ + C)
4. K-Map (Karnaugh Map) Simplification**
Used to **reduce Boolean expressions** and minimize digital circuits.
We use **2, 3, or 4 variables**.
**Example: Simplify Using 4-variable K-map**

F(A,B,C,D) = Σm(0,1,2,3)
K-map (simplified diagram):
Group the 4 ones → forms 4-cell block.
### Final Answer:
F = A̅C̅

# ⭐ **Case Study: Digital Temperature Control System**

### **Goal:**

Maintain room temperature between 25°C – 28°C using sensors and

digital logic.
### **Boolean Expression:**

Let
T1 = temperature < 25
T2 = temperature > 28

Fan ON when T2 = 1
Heater ON when T1 = 1

### **Using SOP:**

Fan = T2
Heater = T1

### **Optimization using K-map:**

Only two simple outputs → minimizes required gates.

⭐ UNIT 2 – COMBINATIONAL LOGIC DESIGN

🔶 1. Adders and Subtractors

1.1 Half Adder
🔹 *Half Adder* adds two **single-bit** numbers (A and B).
🔹 It gives two outputs: **Sum (S)** and **Carry (C)**.

Sub-points
1. Inputs are only **A** and **B**.
2. Sum is generated using **XOR** → S = A ⊕ B
3. Carry is generated using **AND** → C = A · B
4. Cannot take carry input (no Cin).
5. Used in small systems and as a building block for Full Adder.

**Truth Table**

|A|B|S|C|
|-|-|-|-|
|0|0|0|0|
|0|1|1|0|
|1|0|1|0|
|1|1|0|1|
1.2 Full Adder
🔹 Adds **three bits** → A, B, and Carry-in (**Cin**).
🔹 Outputs: **Sum (S)** and **Carry-out (Cout)**.

Sub-points
1. Inputs: A, B, Cin.
2. Sum formula: S = A ⊕ B ⊕ Cin
3. Carry formula: Cout = AB + BCin + ACin
4. Can be built using **two Half Adders**.
5. Used in binary adders like ripple carry adder.

1.3 Half Subtractor

🔹 Performs **A – B** operation for single bits.

**Sub-points**
1. Inputs: A, B.
2. Output: **Difference (D)** and **Borrow (Bo)**.
3. D = A ⊕ B
4. Bo = A’ · B
5. Used in small subtractor circuits.
**Truth Table**

| A | B | D | Bo |
| - | - | - | -- |
|0|0|0|0 |
|0|1|1|1 |
|1|0|1|0 |
|1|1|0|0 |

1.4 Full Subtractor

🔹 Performs **A – B – Bin**.

**Sub-points**
1. Inputs: A, B, Bin
2. Outputs: Difference (D), Borrow-out (Bout)
3. D = A ⊕ B ⊕ Bin
4. Bout = B·A’ + Bin·(A’⊕B)
5. Built using two Half Subtractors.
1.5 Binary Adder (using ICs)
Example IC: **7483** 4-bit adder

Sub-points
1. Performs 4-bit addition.
2. Inputs A3–A0 and B3–B0.
3. Provides Carry-in and Carry-out.
4. High-speed addition using hardware.
5. Used in calculators and ALUs.

2. CODE CONVERTERS
2.1 BCD to Binary

Sub-points
1. BCD stores decimal digits (0000–1001).
2. Binary stores numbers in base-2.
3. Conversion can use adders.
4. Invalid BCD (1010–1111) ignored.
5. Used in digital clocks, calculators.

Example
BCD 0101 → Binary = 5
2.2 Binary to BCD

1. Required for display units (7-segment).

2. Binary 0–9 directly equals BCD.
3. Binary 10–15 needs correction (+6).
4. Implemented using adders/logic circuits.
5. Used in digital meters.

2.3 Binary to Gray Code

Gray code changes **only one bit** at a time.

Sub-points
1. Reduces errors in electromechanical systems.
2. G(n) = B(n)
3. G(n−1) = B(n) ⊕ B(n−1)
4. Used in rotary encoders.
5. Minimizes glitch.

Example
Binary 101 → Gray = 111

2.4 Gray to Binary

1. Reverse process.
2. MSB remains same.
3. Next bits: XOR of previous binary bit & current Gray.
4. Used in communication.
5. Prevents multiple-bit error.

Example
Gray 111 → Binary = 101
2.5 Excess-3 Code
Sub-points
1. Non-weighted code.
2. Add +3 to decimal digit.
3. Used in digital calculators.
4. All 4-digit combinations valid.
5. Easy error detection.

Example
Decimal 9
→ Binary = 1001
→ Excess-3 = 1100

🔶 3. Multiplexers and Demultiplexers

3.1 Multiplexer (MUX)**
MUX = **Multiple inputs, one output**

Sub-points
1. Selects one input based on select lines.
2. Example: 4×1 MUX uses 2 select lines.
3. Y = S1S0-based selected input.
4. Used in data routing, CPUs.
5. Can implement Boolean functions.
Diagram (4×1 MUX)
3.2 Demultiplexer (DEMUX)**
DEMUX = **One input, multiple outputs**

Sub-points
1. Opposite of MUX.
2. Sends input to one selected output.
3. Select lines decide path.
4. E.g., 1×4 DEMUX.
5. Used in communication lines.
4. Comparators (2-bit)**
Comparator compares two 2-bit numbers A and B.

Sub-points
1. Inputs: A1 A0 and B1 B0.
2. Outputs: A>B, A<B, A=B.
3. Comparisons done using logic gates.
4. Used in digital control systems.
5. Fast decision-making unit.

Example
A = 10 (2)
B = 01 (1)
Output → A > B
Diagram
# ⭐ **CASE STUDY – Binary Calculator for BCD Input & 2’s
Complement**

Include this in exam for bonus marks.

### Sub-points

1. Inputs are given in BCD format.

2. Calculator converts BCD → Binary.
3. Uses Full Adders for addition.
4. For subtraction: converts number into 2’s complement.
5. Output converted back to BCD for display.
⭐ UNIT 3 – SEQUENTIAL CIRCUITS
Sequential circuits = circuits that depend on:
✔ **Present Input**
✔ **Past Output (Memory)**

They use **Flip-Flops**, **Registers**, and **Counters**.

1. FLIP-FLOPS
Flip-Flop = **1-bit memory device**
It stores 0 or 1.

1.1 SR FLIP-FLOP (Set–Reset)

**Sub-Points (Write in exam)

1. S = Set input, makes output Q = 1
2. R = Reset input, makes output Q = 0
3. When S=0, R=0 → No change
4. When S=1, R=1 → Invalid condition
5. Used in simple memory and control units

**Truth Table**
| S | R | Q(next) |
| - | - | ------------- |
| 0 | 0 | Q (no change) |
|0|1|0 |
|1|0|1 |
| 1 | 1 | Invalid |
1.2 JK FLIP-FLOP
Improved version of SR (no invalid state).

**Sub-Points
1. Inputs: J and K
2. J = Set, K = Reset
3. When J=K=1 → **Toggle**
4. No invalid state
5. Used in counters

**Truth Table**
| J | K | Q(next) |
| - | - | ----------- |
|0|0|Q |
|0|1|0 |
|1|0|1 |
| 1 | 1 | Q' (toggle) |
1.3 D FLIP-FLOP (Data/Delay)

**Sub-Points**
1. Has only one input: **D**
2. Output follows input: Q(next) = D
3. Removes invalid states
4. Used in registers
5. Clock controlled

**Truth Table**
| D | Q(next) |
| - | ------- |
|0|0 |
|1|1 |

#1.4 T FLIP-FLOP (Toggle)

### **Sub-Points**
1. T = 1 → Flips state
2. T = 0 → No change
3. Used in counters
4. Built from JK Flip-Flop
5. Frequency divider
**Truth Table**
| T | Q(next) |
| - | ------- |
|0|Q |
| 1 | Q' |

1.5 Master-Slave JK Flip-Flop

**Sub-Points**
1. Made of two JK FFs → Master + Slave
2. Master active at clock HIGH
3. Slave active at clock LOW
4. Removes race condition
5. Used in synchronous circuits
1.6 EXCITATION TABLES**
Used for **designing** sequential circuits.

**Example – D FF Excitation Table

| Q | Q(next) | D |
| - | ------- | - |
|0|0 |0|
|0|1 |1|
|1|0 |0|
|1|1 |1|

Used to find input needed for state change.

1.7 FLIP-FLOP CONVERSION**

Example: **JK → D Flip-Flop**

Formula:
D = JQ' + K'Q
Used when one type of FF is available but circuit needs another.

2. REGISTERS
Register = **Group of Flip-Flops** used to store multi-bit data.

2.1 SISO (Serial-In Serial-Out)

**Sub-Points
1. Data enters serially (one bit at a time)
2. Data leaves serially
3. Simple design
4. Uses D FFs
5. Used in data transmission
2.2 SIPO (Serial-In Parallel-Out)

### **Sub-Points**
1. Input comes serially
2. Output available in parallel
3. Used in ADCs, communication
4. Uses shift registers
5. Converts serial data to parallel

2.3 PISO (Parallel-In Serial-Out)

**Sub-Points**
1. Input loaded in parallel
2. Output sent serially
3. Used for transmitting data in serial lines
4. Uses control signal (load)
5. Used in keyboards

2.4 PIPO (Parallel-In Parallel-Out)

### **Sub-Points**
1. Input loaded simultaneously
2. Output also available simultaneously
3. Used in CPUs
4. Fastest register
5. Used in temporary data storage
2.5 Shift Registers

Shift registers **shift data** left or right.

### **Types**
1. SISO
2. SIPO
3. PISO
4. PIPO
5. Bidirectional

### Uses:
✔ Data storage
✔ Bit manipulation
✔ Serial communication

3. COUNTERS
Counter = Sequential circuit that **counts clocks**.
Types:
3.1 Ring Counter

**Sub-Points**
1. Circular shift register
2. One FF holds “1”, others “0”
3. Pattern rotates
4. Requires n FFs for n states
5. Used in sequence generators

3.2 Johnson Counter

**Sub-Points**
1. Inverted output of last FF fed to first FF
2. 2n states with n FFs
3. More efficient than ring counter
4. Pattern: 000 → 100 → 110 → ...
5. Used in timing circuits
3.3 BCD Counter

Sub-Points
1. Counts from 0000 to 1001 (0–9)
2. After 9 resets to 0
3. Uses modulo-10
4. Used in digital clocks
5. Built using JK FFs

# ⭐ **CASE STUDY – DIGITAL STOPWATCH USING FF,

REGISTERS, COUNTERS**

### **Main points**

1. Flip-Flops store start/stop control.

2. Counters count milliseconds, seconds.
3. Registers hold display data.
4. BCD counters used for digits.
5. Output shown on 7-segment display.
⭐UNIT 4 – Algorithmic State Machines and Logic Families
🔶 1. ALGORITHMIC STATE MACHINES (ASM)
ASM = A method to design **sequential circuits** using **step-by-
step diagrams**.
It is an improved form of **Finite State Machine (FSM)**.

🔷 1.1 Finite State Machine (FSM)

**Sub-Points**
1. FSM is a model that moves between states based on input.
2. Has **current state**, **input**, **next state**.
3. Used in controllers like vending machine, traffic signals.
4. Designed using **state diagram**.
5. Cannot show complex operations easily → therefore ASM used.

🔷 1.2 What is ASM (Algorithmic State Machine)?

**Sub-Points**
1. ASM is a graphical method to design **synchronous sequential
circuits**.
2. Shows **states**, **decisions**, **operations** clearly.
3. Makes digital system design easy and modular.
4. Combines **flowchart + state diagram**.
5. Used for complex systems like vending machines, elevators.

1.3 Elements of ASM Chart*

ASM chart has **three main blocks**:
**1. State Box
* Represents a state.
* Contains operations performed in that state.
* Executes at the **clock edge**.

2. Decision Box**
* Diamond shape.
* Shows input conditions (0 or 1).
* Decides the path to next state.

3. Conditional Output Box**

* Shows outputs that occur only when condition is true.
* Connected to decision box.

###ASM Diagram Sample**

+-------------+
| State S0 |
| A←1, B←0 |
+-------------+
 |
+-----+
| X=1 |
+-----+
/ \
YES NO
| |
+--------+ +--------+
| State1 | | State2 |
+--------+ +--------+

1.4 Construction of ASM Chart**

**Steps**
1. Identify all **states** of the system.
2. Write operations inside **state boxes**.
3. Add **decision boxes** for conditions.
4. Show transitions using arrows.
5. Verify working with truth table.

1.5 Realization of Sequential Circuits Using ASM

**Sub-Points**
1. Convert ASM to **state table**.
2. State table → **flip-flop input equations**.
3. Use **JK/D/T flip-flops** to implement circuit.
4. Add combinational logic for conditions.
5. Final circuit = FFs + logic gates.
# ⭐ **CASE STUDY – Vending Machine Controlled Using ASM**

### **Main Points**

1. States: Idle, Selection, Payment, Dispense.

2. Decision box checks if amount inserted is enough.
3. Outputs: Motor ON, Display, Refund.
4. ASM helps remove errors and makes design clear.
5. Used in real digital vending machines.

2. LOGIC FAMILIES
Logic families = **types of digital circuits** built using different
technologies.

Mainly two types → **Unipolar** & **Bipolar**

2.1 Classification of Logic Families**

Unipolar Logic Family**
* Uses MOSFET
* Example: CMOS

Bipolar Logic Family**

* Uses BJT
* Example: TTL, ECL

2.2 Characteristics of Digital ICs

(VERY IMPORTANT FOR EXAM)

**1. Fan-In**
* Number of inputs a gate can handle.
* Example: NAND gate with fan-in 4 can take 4 inputs.
**2. Fan-Out**
* Number of gates a gate can drive.
* Example: Fan-out = 10 → output can connect to 10 inputs.

*3. Noise Immunity**

* Ability of logic gate to withstand noise.
* Higher = more stable.

**4. Propagation Delay**

* Time taken for input change to reflect at output.
* Measured in nanoseconds (ns).
* Less delay = faster IC.

**5. Power Dissipation**

* Power consumed by IC.
* Measured in mW.
* Low power = better.

**6. Operating Temperature**

* Range in which IC works safely.
* Example: 0°C to 70°C.

**7. Power Supply Requirement**

* Voltage needed.
* TTL uses 5V, CMOS uses 3–15V.

2.3 TTL (Transistor–Transistor Logic)**

 **Sub-Points**
1. Uses **BJT (bipolar transistors)**
2. Fast switching
3. High power consumption
4. Works at 5V
5. Widely used in older computers

2.4 CMOS (Complementary MOS)**

**Sub-Points**
1. Uses **NMOS + PMOS**
2. Very low power consumption
3. Works on wide voltage (3V–15V)
4. High noise immunity
5. Used in modern chips, CPUs, mobile processors

2.5 Comparison: TTL vs CMOS**

| Parameter | TTL | CMOS |

| -------------- | ------ | ------------------------ |
| Technology | BJT | MOSFET |
| Power | High | Low |
| Speed | Fast | Very fast (new versions) |
| Noise Immunity | Medium | High |
| Voltage | 5V | 3–15V |
# ⭐ **CASE STUDY – Vending Machine Controller Using ASM**

### **Points to Write**

1. ASM chart used to define states like Idle, Selection, Amount Check,
Dispense.
2. Flip-flops store current state.
3. Combinational logic checks money inserted.
4. Output lines control motor and display.
5. ASM method reduces design errors and increases system reliability.
⭐ UNIT 5 – PROGRAMMABLE LOGIC DEVICES (PLD)
PLDs are **digital ICs** that can be **programmed** to implement
any logic circuit.
They reduce the need for multiple gates and ICs.

1. What is PLD?

**Simple Meaning:**
A **Programmable Logic Device (PLD)** is a chip where you can
design your own digital logic (AND, OR, NOT gates) by programming
it.

**Sub-Points:**
1. Can be programmed to perform different logic functions.
2. Used to replace many separate logic ICs.
3. Easy to update or change design (re-programmable).
4. Saves hardware cost and space.
5. Used in calculators, controllers, communication devices.

**Example:**
Implementing a **vending machine controller** on a single PLD chip.
2. ROM as a PLD
ROM = **Read Only Memory**, but it can also be used as a PLD.

**Sub-Points:**
1. ROM contains a fixed set of memory locations.
2. Inputs are used as **address lines**.
3. Outputs store the logic truth table.
4. Any combinational circuit can be implemented using ROM.
5. ROM performs **all minterms → OR array**.

**Example:**
Designing a **7-segment display** decoder using ROM.

3. Programmable Logic Array (PLA)

PLA = Programmable AND + Programmable OR

**Sub-Points:**
1. Both **AND array** and **OR array** are programmable.
2. Very flexible for designing custom logic.
3. Used when SOP or POS expressions are required.
4. Suitable for complex combinational circuits.
5. Faster compared to ROM because unused minterms are removed.

**Working of PLA (easy explanation):**

1. Take logic function → convert to SOP form.
2. Select required AND terms.
3. Connect needed AND terms to OR gates.
4. Program PLA using fuses or software.
5. Output produces correct logic.

**Example (To Write in Exam):**

Design F = A’B + AB’ using PLA.

AND array produces:

* P1 = A’B
* P2 = AB’
OR array:

* F = P1 + P2

**Advantages of PLA:**
1. Fully programmable → very flexible.
2. Can implement many functions on same chip.
3. Reduces hardware complexity.
4. Faster than ROM for logic functions.

4. Programmable Array Logic (PAL)

PAL = **Programmable AND + Fixed OR**

**Sub-Points:**
1. AND array is programmable, OR array is fixed.
2. Easier to design than PLA.
3. Less flexible but faster.
4. Ideal for small and medium digital circuits.
5. Cheaper than PLA.
### **How PAL Works (simple):**
1. Select AND terms required.
2. Use predefined OR structure.
3. Program AND connections using fuses/software.
4. Generates output logic.
**Programming PAL (simple steps):**
1. Write the logic equation.
2. Generate AND product terms.
3. Connect AND terms to fixed OR gate.
4. Burn the fuse (hardware) / write code (software).
5. PAL produces final output.

**Example:**
Implement F = A + B using PAL
* AND array produces A and B
* OR gate permanently adds them: F = A + B

# **Advantages of PAL:**
1. Faster than PLA because OR is fixed.
2. Simple design and low cost.
3. Good for medium-size digital circuits.
4. Less power consumption.

5. Designing Combinational Circuits Using PLDs

**Sub-Points:**
1. Choose the PLD type (ROM / PLA / PAL).
2. Convert logic into SOP or POS.
3. Map logic terms to AND/OR arrays.
4. Program device using software like Verilog, CUPL, or fuses.
5. Test output using simulation.
**Example

Design a **2-bit comparator** using PLA

* F1 = A = B
* F2 = A > B
* F3 = A < B
Use AND & OR products to implement.

# ⭐ **CASE STUDY – Traffic Light Control System Using PLD**

### **Write these 5 points in exam:**

1. Traffic lights operate through states like RED → GREEN →

YELLOW.
2. Using PLA/PAL, all state transitions are implemented on a single
chip.
3. AND array generates conditions (car detected, timer finished).
4. OR array produces control signals for lights.
5. PLD gives compact design, reliability, and faster switching.