Chapter 2

HARDWARE DESCRIPTION
LANGUAGE - VERILOG

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 I. INTRODUCTION
1.1. Hardware Description Language 1950’s 1980’s
- Digital circuit design (1950’s,1980’s):
draw schematic -> select components
-> implement.
- A schematic has:
• Component: Gate, Resistor,
(LEDs, LCD), Chips,…
• Wires: Interconnecting these
components
• Input, Output: Can be used as
component
- A schematic can include other one:
hierarchy
- A schematic is a netlist representation
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 I. INTRODUCTION
1.1. Hardware Description Language
1995’s
- Digital circuit design (1995’s ->):
draw schematic ->... finish.
- 2 popular HDLs: Verilog HDL
(1984) and VHDL (1980).
- HDLs are widely used in digital
circuit design and simulation at
register-transfer level.
- A HDL design has several modules,
each module has several hierarchical
modules and communicates with
other modules through input, output,
and bidirectional port.

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 I. INTRODUCTION
1.2. HDL instead of Schematic
- We can build and store HDL
designs in files.
- Files can be parsed and processed
by tools:
• Write HDL – Design activity
• Select components – Tool
activity (Synthesis)
• Implement – Tool activity (pin
assignment, program)
- Easily edit or modify designs
without changing hardware.
- Meet complex design requirements

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 I. INTRODUCTION
1.3. Summary
- A digital circuit design is concerned with mapping ideas into digital logic
components (gates, registers).
- Schematic capture of a netlist is a very convenient way to express the
design as a model.
- HDLs developed as a replacement for schematics.
- HDLs are the entry of a modern digital design flow:
• Synthesis: convert textual form to digital logic components
• Implementation: map digital logic components into technology
• Verification: use simulation to verify functionality and timing of the
implementation.

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 II. HIERARCHICAL DESIGN
2.1. Abstraction in hardware
design
- HDLs offer a textual
description of a netlist.
- Through abstraction in the
HDL, we can capture more
than a single transistor or
gate at a time.
- Verilog offers 3 types of
abstraction:
• Structural modeling
• Dataflow modeling
• Behavioral modeling

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 II. HIERARCHICAL DESIGN
2.1. Abstraction in hardware
design
- HDLs offer a textual
description of a netlist.
- Through abstraction in the
HDL, we can capture more
than a single transistor or
gate at a time.
- Verilog offers 3 types of
abstraction:
• Structural modeling
• Dataflow modeling
• Behavioral modeling

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 II. HIERARCHICAL DESIGN
2.2. Structural description vs
Behavioral description
- Structural description: explains
what happens to Q and Qbar in
terms of a netlist of lower-level
components.
- Behavioral description: explains
what happens to Q and Qbar in
terms of Rbar and Sbar.
- A model can be expressed as
behavior or structure (of lower-
level models)
- In Verilog, a given module can be
expressed as structure or else as
behavior
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 II. HIERARCHICAL DESIGN
2.3. Example: Behavioral modeling

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 II. HIERARCHICAL DESIGN
2.3. Example: Structural modeling

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 III. VERILOG HDL
3.1. Synthesis and Simulation

- We are focusing on simulation and writing correct Verilog code as behavior.

- Keep in mind: A correct simulation does not mean a correct implementation.
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 III. VERILOG HDL
3.1. Synthesis and Simulation

This will synthesize

This will simulate, but
not synthesizable.

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 III. VERILOG HDL
3.2. Module
module name(portlist); -> name of module (list of ports)
port declarations; -> direction of ports (input, output, bidir)
parameter declarations; -> module variants
wire declarations; -> local communication
reg declarations; -> local storage, local variables
variable declarations; -> local storage
module instantiations; -> structural
dataflow statements; -> behavioral
always blocks; -> behavioral
initial blocks; -> behavioral
tasks and functions; -> behavioral
endmodule
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 III. VERILOG HDL
3.2. Module – Example 1
module name(portlist); module or_nand_3 (enable, x1, x2, x3, x4, y);
port declarations; input enable, x1, x2, x3, x4;
parameter declarations; output y;
wire declarations; reg y;
always @ (enable or x1 or x2 or x3 or x4)
reg declarations;
if (enable)
variable declarations;
y = !((x1 | x2) & (x3 | x4));
module instantiations; else
dataflow statements; y = 1; // operand is a constant.
always blocks; endmodule
initial blocks;
tasks and functions;
endmodule
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 III. VERILOG HDL
3.2. Module – Example 1
module name(portlist); module or_nand_4 (enable, x1, x2, x3, x4, y);
port declarations; input enable, x1, x2, x3, x4;
parameter declarations; output y;
wire declarations; assign y = or_nand(enable, x1, x2, x3, x4);
function or_nand;
reg declarations;
input enable, x1, x2, x3, x4;
variable declarations;
begin
module instantiations; or_nand = ~(enable & (x1 | x2) & (x3 |
dataflow statements; x4));
always blocks; end
initial blocks; endfunction
tasks and functions; endmodule
endmodule
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 III. VERILOG HDL
3.2. Module – Example 2
module or_nand_5 (enable, x1, x2, x3, x4, y);
module name(portlist); input enable, x1, x2, x3, x4;
port declarations; output y;
parameter declarations; reg y;
wire declarations; always @ (enable or x1 or x2 or x3 or x4)
reg declarations; or_nand (enable, x1, x2, x3, x4, y);
variable declarations; task or_nand;
input enable, x1, x2, x3, x4;
module instantiations;
output reg y1;
dataflow statements;
begin
always blocks;
y1 = !(enable & (x1 | x2) & (x3 | x4));
initial blocks; end
tasks and functions; endtask
endmodule endmodule
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 III. VERILOG HDL
3.3. Data value
- 4 logic levels:
• 0: low, 1: high
• Z: floating(hi-Z), X: unkown
- Initially, variables start out at X
- Parameters assignment: {bit width}’{base}{value}
• parameter RED = 6’b010_111 : 010111
• parameter BLUE = 8'b0110 : 00000110
• 4'bx01 : xx01
• 16'H3AB : 0000001110101011
• 24 : 0…0011000
• 5'O36 : 11011
• 8'hz : zzzzzzzz
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 III. VERILOG HDL
3.4. Data type
- 2 types of data: wire and reg
- A wire and a reg carry information
around in a module
• wire: does not have storage,
but it reflects the value of a
driver (continuously assigned).
• reg (reg, integer): is a variable
with storage (procedurally assigned)
- Structural modeling uses wire, not use reg
- Behavioral modeling uses reg (in blocks initial and always), not use wire
- Example:
wire Reset; // 1-bit wire reg signed [3:0] counter; // 4-bit register
wire [7:0] Addr; // 8-bit wire integer cla; // maximum 32-bit 18
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 III. VERILOG HDL
3.4. Data type

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 III. VERILOG HDL
3.5. Port list
- inputs, outputs, inouts are wires by default
- output ports can also be reg

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 III. VERILOG HDL
3.6. Example:

Structural Behavioral - Procedural Behavioral – Dataflow

Procedural assignment Continuous assignment 21

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 III. VERILOG HDL
3.6. Example:
- Write verilog for the following schematics using behavioral (procedural and
dataflow)

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 IV. ASSIGNMENT
4.1. Initial and always blocks module initalways (clk);
- Procedural assignments reg [7:0] a;
- initial blocks execute once at t = 0 reg b;
(power on) initial
- always blocks execute continuously begin
• always @(a or b) a = 0;
-> any changes in a or b b = 0;
end
• always @(posedge a)
always @ (posedge clk)
-> a transitions from 0 to 1
begin
• always @(negedge a) a = a + 1;
-> a transitions from 1 to 0 b = 1;
• always @* end
-> any changes in “inputs” endmodule;
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 IV. ASSIGNMENT
4.2. Continuous assignment
// example 1
- Syntax: assign out = in1 ^ in2;
assign LHS = RHS;
- LHS : data type is mandatory wire. // example 2
- RHS: data type can be wire, reg, wire product1, product2;
parameter, expression. assign product1 = in1 & !in2;
- Order of the statement does not assign product2 = !in1 & in2;//
impact the design. assign out = product1 | product2;

- All continuous assignment

// example 3
statements execute concurrently.
assign out = (in1 != in2);
- Is used for connecting the logic
gates to save LEs.
// example 4
assign out = in1 ? (!in2) : (in2);
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 IV. ASSIGNMENT
4.2. Continuous assignment
- Syntax:
assign LHS = RHS;
- LHS : data type is mandatory wire.
- RHS: data type can be wire, reg,
parameter, expression.
- Order of the statement does not
module nand(q1, q2, a, b)
impact the design.
input a, b;
- All continuous assignment.
output q1, q2;
statements execute concurrently
assign q1 = ~(a | b);
- Is used for connecting the logic
assign q2 = ~(a & b);
gates to save LEs.
endmodule
assign {q1,q2} = {~(a | b),~(a & b)};
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 IV. ASSIGNMENT
4.3. Procedural assignment
module nand(q, a, b) //Continuous assignment
- Syntax:
output q;
LHS = RHS; // blocking
input a, b;
LHS <= RHS; // non-blocking
assign q = ~(a | b);
- LHS: data type is mandatory reg. endmodule
- RHS: data type can be wire, reg,
parameter, expression. module nand(q, a, b) //Procedural assignment
- All statements within the block output q;
are executed sequentially. reg q;
- Use (begin, end) keyword if input a, b;
there are several procedural always @(a or b)
assignments in a block. q = ~(a | b);
endmodule

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 IV. ASSIGNMENT
4.4. Blocking and non-blocking assignment // Blocking
- Blocking: reg [7:0] a, b;
• Assignment takes place immediately initial a = 4;
(i.e. assignment on a MUST complete initial b = 0;
before assignment on b can start) always @(posedge clk) begin
- Non-blocking: a = b + 2;
• All variables are updated at the same time b = a * 3;
at the end of current time step end
(i.e. a and b are updated at the same time // Non-blocking
after exiting always block) reg [7:0] a, b;
- In practice, DO NOT mix blocking and always @(posedge clk) begin
non-blocking in the same always block. a <= b + 2;
- Example: What is value of a, b after 3 b <= a * 3;
cycles of clk? end
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 IV. ASSIGNMENT
4.4. Blocking and non-blocking assignment // Blocking
- Blocking: assignment on a MUST reg [7:0] a, b;
complete before assignment on b can start) initial a = 4;
• Clk0: a=4, b=0 initial b = 0;
• Clk1: a=2, b=2*3=6 always @(posedge clk) begin
• Clk2: a=8, b=24 a = b + 2;
• Clk3: a=26, b=78 b = a * 3;
end
- Non-blocking: a and b are updated at the
// Non-blocking
same time after exiting always block
reg [7:0] a, b;
• Clk0: a=4, b=0
always @(posedge clk) begin
• Clk1: a=2, b=4*3=12
a <= b + 2;
• Clk2: a=14, b=6 b <= a * 3;
• Clk3: a=8, b=14*3=42 end
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 IV. ASSIGNMENT
4.4. Blocking and non-blocking assignment

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 IV. ASSIGNMENT
4.4. Blocking and non-blocking assignment

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 IV. ASSIGNMENT
4.4. Blocking and non-blocking assignment

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 IV. ASSIGNMENT

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 V. OPERATOR
5.1. Types of operator
• Arithmetic: + (add), - (subtract), * (multiply), //common use
/ (divide), **(power), % (modulo) //non-common use
• Bitwise: & (and), | (or), ~ (negate), ^ (xor), ^~ (xnor)
• Reduction: assign q = &a, q = |(4'b0001) = 1, q = ^(4'b0111) = 1
• Logical: !, &&, ||, !=, (4'b1100) && (4'b0011) = 1
• Relational: a < b, a > b, a <= b, a >= b, a ==b, a != b
• Logical shift: <<, >>
• Arithmetic shift: <<<, >>> (Sign-bit is preserved on arithmetic
shift-right of signed operand)
• Selection: assign q = c ? a : b
• Concatenation: {a, b[3:2], c} = {a, b[3], b[2], c} = a 4-bit vector
• Replication: 4{a} = {a, a, a, a}, {a, 3{b,c}} = {a, b, c, b, c, b, c}
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 V. OPERATOR
5.2. Example
reg [5:0] A = 6′b101111;
reg [5:0] B, C;

B = A >> 2;
B = A>>>2; suppose declaration: reg signed [5:0] A, B;

C = A + B;
C = A & B;
C = {A[2:1], B[2:0]};

assign out = &A;

assign out = A[1] ? (A[0] ? B[1] : B[2]) : B[0];
C = out ? A : C;
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 V. OPERATOR
5.2. Example
reg [5:0] A = 6′b101111;
reg [5:0] B, C;

B = A >> 2; // 6’b001011
B = A>>>2; // 6’b111011

C = A + B; // 6’b101010
C = A & B; // 6’b101011
C = {A[2:1], B[2:0]}; // 6’b011011

assign out = &A; // A[0]&A[1]&A[2] &A[3]&A[4]&A[5] = 0

assign out = (A[1]) ? ((A[0]) ? B[1] : B[2]) : B[0]; // = 1
C = out ? A : C; // 6′b101111
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 VI. CONDITIONAL STATEMENTS
6.1. if-then-else:

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 VI. CONDITIONAL STATEMENTS
6.1. if-then-else:

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 VI. CONDITIONAL STATEMENTS
6.2. Case:

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 VI. CONDITIONAL STATEMENTS
6.2. Case:

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 VI. CONDITIONAL STATEMENTS
6.3. Example: - Use selection operator:

module mux_4bits(y, a, b, c, d, sel);

input [3:0] a, b, c, d;
input [1:0] sel;
output [3:0] y;
assign y =
(sel == 0) ? a :
(sel == 1) ? b :
(sel == 2) ? c :
(sel == 3) ? d : 4'bx;
endmodule

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 VI. CONDITIONAL STATEMENTS
6.3. Example: - Use if-then-else statement
module mux_4bits(y, a, b, c, d, sel);
input [3:0] a, b, c, d;
input [1:0] sel
output [3:0] y;
reg [3:0] y;
always @ (a or b or c or d or sel)
begin
if (sel == 0) y = a;
else if (sel == 1) y = b;
else if (sel == 2) y = c;
else if (sel == 3) y = d;
else y = 4'bx;
end
endmodule
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 VI. CONDITIONAL STATEMENTS
6.3. Example: - Use case statement
module mux_4bits(y, a, b, c, d, sel);
input [3:0] a, b, c, d;
input [1:0] sel;
output [3:0] y;
reg [3:0] y;
always @ (a or b or c or d or sel)
case (sel)
0: y = a;
1: y = b;
2: y = c;
3: y = d;
default: y = 4'bx;
endcase
endmodule
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 VI. CONDITIONAL STATEMENTS
6.3. Example:
- Write verilog for the following schematic using if-then-else and case
statements

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 VI. CONDITIONAL STATEMENTS
6.4. Some typical Flip-Flops
- D Flip-Flop:

module dff (data, clk, q);

input data, clk;
output q;
reg q;
always @(posedge clk)
q <= data;
endmodule

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 VI. CONDITIONAL STATEMENTS
6.4. Some typical Flip-Flops
- D Flip-Flop with asynchonous Reset:

module dff (data, clk, reset, q);

input data, clk, reset;
output q;
reg q;
always @(posedge clk or negedge reset)
if (~reset)
q <= 1'b0;
else
q <= data;
endmodule
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 VI. CONDITIONAL STATEMENTS
6.4. Some typical Flip-Flops
- D Flip-Flop with asynchonous Preset:

module dff (data, clk, preset, q);

input data, clk, preset;
output q;
reg q;
always @(posedge clk or negedge preset)
if (~preset)
q <= 1'b1;
else
q <= data;
endmodule
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 VI. CONDITIONAL STATEMENTS
6.4. Some typical Flip-Flops:
- D Flip-Flop with asynchonous Preset, Reset:
module dff (data, clk, preset, reset, q);
input data, clk, preset, reset;
output q;
reg q;
always @ (posedge clk or negedge reset or posedge preset)
if (~reset)
q <= 1'b0;
else if (preset)
q <= 1'b1;
else q <= data;
endmodule
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 VI. CONDITIONAL STATEMENTS
6.4. Some typical Flip-Flops:

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