FULL ADDER:
`timescale 1ns/1ps
// half adder
module half_adder(
input wire a,
input wire b,
output wire sum,
output wire carry
);
assign sum = a ^ b;
assign carry = a & b;
endmodule
module full_adder(
input wire a,
input wire b,
input wire cin,
output wire sum,
output wire cout
);
wire s1, c1, c2;
half_adder HA1(.a(a), .b(b), .sum(s1), .carry(c1));
half_adder HA2(.a(s1), .b(cin), .sum(sum), .carry(c2));
assign cout = c1 | c2;
endmodule
// testbench for full adder
`timescale 1ns/1ps
module tb_full_adder;
reg a, b, cin;
wire sum, cout;
integer i;
full_adder dut(.a(a), .b(b), .cin(cin), .sum(sum), .cout(cout));
initial begin
for (i = 0; i < 8; i = i + 1) begin
{a, b, cin} = i[2:0];
#10;
end
$finish;
end
endmodule
SUBRACTOR:
`timescale 1ns/1ps
// half subtractor
module half_subtractor(
input wire a,
input wire b,
output wire diff,
output wire borrow
);
assign diff = a ^ b;
assign borrow = (~a) & b;
endmodule
// full subtractor built from two half subtractors
module full_subtractor(
input wire a,
input wire b,
input wire bin,
output wire diff,
output wire bout
);
wire d1, b1, b2;
half_subtractor HS1(.a(a), .b(b), .diff(d1), .borrow(b1));
half_subtractor HS2(.a(d1), .b(bin), .diff(diff), .borrow(b2));
assign bout = b1 | b2;
endmodule
`timescale 1ns/1ps
module tb_full_subtractor;
reg a, b, bin;
wire diff, bout;
integer i;
full_subtractor dut(.a(a), .b(b), .bin(bin), .diff(diff), .bout(bout));
initial begin
for (i = 0; i < 8; i = i + 1) begin
{a, b, bin} = i[2:0];
#10;
end
$finish;
end
endmodule
4-to-1 Multiplexer :
`timescale 1ns/1ps
module mux4to1(
input wire [3:0] d,
input wire [1:0] sel,
output wire y
);
assign y = (sel == 2'b00) ? d[0] :
(sel == 2'b01) ? d[1] :
(sel == 2'b10) ? d[2] :
d[3];
endmodule
// testbench for 4-to-1 mux
`timescale 1ns/1ps
module tb_mux4to1;
reg [3:0] d;
reg [1:0] sel;
wire y;
integer i;
mux4to1 dut(.d(d), .sel(sel), .y(y));
initial begin
d = 4'b1010;
for (i = 0; i < 4; i = i + 1) begin
sel = i;
#10;
end
$finish;
end
endmodule
DEMULTIPLEXER:
`timescale 1ns/1ps
module demux1to4(
input wire d,
input wire [1:0] sel,
output reg [3:0] y
);
always @(*) begin
y = 4'b0000;
case (sel)
2'b00: y[0] = d;
2'b01: y[1] = d;
2'b10: y[2] = d;
2'b11: y[3] = d;
default: y = 4'b0000;
endcase
end
endmodule
// testbench for demux
`timescale 1ns/1ps
module tb_demux1to4;
reg d;
reg [1:0] sel;
wire [3:0] y;
integer i;
demux1to4 dut(.d(d), .sel(sel), .y(y));
initial begin
d = 1'b1;
for (i = 0; i < 4; i = i + 1) begin
sel = i;
#10;
end
$finish;
end
endmodule
ENCODER:
`timescale 1ns/1ps
module encoder4to2(
input wire [3:0] d,
output reg [1:0] y,
output wire valid
);
assign valid = |d;
always @(*) begin
case (d)
4'b0001: y = 2'b00;
4'b0010: y = 2'b01;
4'b0100: y = 2'b10;
4'b1000: y = 2'b11;
default: y = 2'b00;
endcase
end
endmodule
// testbench for encoder
`timescale 1ns/1ps
module tb_encoder4to2;
reg [3:0] d;
wire [1:0] y;
wire valid;
integer i;
encoder4to2 dut(.d(d), .y(y), .valid(valid));
initial begin
for (i = 0; i < 4; i = i + 1) begin
d = (4'b0001 << i);
#10;
end
d = 4'b0000; #10;
$finish;
end
endmodule
DECODER:
`timescale 1ns/1ps
module decoder2to4(
input wire [1:0] a,
input wire en,
output wire [3:0] y
);
assign y = en ? (4'b0001 << a) : 4'b0000;
endmodule
// testbench for decoder
`timescale 1ns/1ps
module tb_decoder2to4;
reg [1:0] a;
reg en;
wire [3:0] y;
integer i;
decoder2to4 dut(.a(a), .en(en), .y(y));
initial begin
en = 1;
for (i = 0; i < 4; i = i + 1) begin
a = i;
#10;
end
en = 0; a = 2'b10; #10;
$finish;
end
endmodule
PRIORITY ENCODER:
`timescale 1ns/1ps
module priority_encoder4to2(
input wire [3:0] d,
output reg [1:0] y,
output wire valid
);
assign valid = |d;
always @(*) begin
casex (d)
4'b1xxx: y = 2'b11;
4'b01xx: y = 2'b10;
4'b001x: y = 2'b01;
4'b0001: y = 2'b00;
default: y = 2'b00;
endcase
end
endmodule
// testbench for priority encoder
`timescale 1ns/1ps
module tb_priority_encoder4to2;
reg [3:0] d;
wire [1:0] y;
wire valid;
priority_encoder4to2 dut(.d(d), .y(y), .valid(valid));
initial begin
d = 4'b0000; #10;
d = 4'b0001; #10;
d = 4'b0010; #10;
d = 4'b0100; #10;
d = 4'b1000; #10;
d = 4'b1010; #10; // tests priority (1000 should win)
d = 4'b0111; #10; // tests priority (0100 should win)
$finish;
end
endmodule
SR Flip-Flop:
`timescale 1ns/1ps
module sr_ff(
input clk,
input reset,
input s,
input r,
output reg q,
output qbar
);
assign qbar = ~q;
always @(posedge clk) begin
if (!reset)
q <= 0;
else begin
case ({s,r})
2'b00: q <= q;
2'b01: q <= 0;
2'b10: q <= 1;
2'b11: q <= 1'bx;
endcase
end
end
endmodule
`timescale 1ns/1ps
module tb_sr_ff;
reg clk, reset, s, r;
wire q, qbar;
sr_ff dut(clk, reset, s, r, q, qbar);
initial clk = 0;
always #5 clk = ~clk;
initial begin
reset = 0; s = 0; r = 0; #10;
reset = 1; #10;
s=0; r=1; #10;
s=1; r=0; #10;
s=1; r=1; #10;
$finish;
end
endmodule
D:
`timescale 1ns/1ps
module d_ff(
input clk,
input reset,
input d,
output reg q,
output qbar
);
assign qbar = ~q;
always @(posedge clk) begin
if (!reset)
q <= 0;
else
q <= d;
end
endmodule
`timescale 1ns/1ps
module tb_d_ff;
reg clk, reset, d;
wire q, qbar;
d_ff dut(clk, reset, d, q, qbar);
initial clk = 0;
always #5 clk = ~clk;
initial begin
reset = 0; d = 0; #10;
reset = 1; d = 0; #10;
d = 1; #10;
d = 0; #10;
$finish;
end
endmodule
JK:
`timescale 1ns/1ps
module jk_ff(
input clk,
input reset,
input j,
input k,
output reg q,
output qbar
);
assign qbar = ~q;
always @(posedge clk) begin
if (!reset)
q <= 0;
else begin
case ({j,k})
2'b00: q <= q;
2'b01: q <= 0;
2'b10: q <= 1;
2'b11: q <= ~q;
endcase
end
end
endmodule
`timescale 1ns/1ps
module tb_jk_ff;
reg clk, reset, j, k;
wire q, qbar;
jk_ff dut(clk, reset, j, k, q, qbar);
initial clk = 0;
always #5 clk = ~clk;
initial begin
reset = 0; j=0; k=0; #10;
reset = 1; #10;
j=0; k=1; #10;
j=1; k=0; #10;
j=1; k=1; #10;
$finish;
end
endmodule
T:
`timescale 1ns/1ps
module t_ff(
input clk,
input reset,
input T,
output reg Q,
output Qbar
);
assign Qbar = ~Q;
always @(posedge clk) begin
if (!reset)
Q <= 0;
else if (T)
Q <= ~Q;
else
Q <= Q;
end
endmodule
`timescale 1ns/1ps
module tb_t_ff;
reg clk, reset, T;
wire Q, Qbar;
t_ff dut(clk, reset, T, Q, Qbar);
initial clk = 0;
always #5 clk = ~clk;
initial begin
reset = 1; T = 0; #10;
reset = 0;
T = 1; #10;
T = 0; #10;
T = 1; #10;
T = 1; #10;
T = 0; #10;
$finish;
end
endmodule
UP Counter:
`timescale 1ns/1ps
module up_counter(
input clk,
input reset,
output reg [3:0] count
);
always @(posedge clk) begin
if (reset)
count <= 4'b0000;
else
count <= count + 1;
end
endmodule
`timescale 1ns/1ps
module tb_up_counter;
reg clk, reset;
wire [3:0] count;
up_counter dut(clk, reset, count);
initial clk = 0;
always #5 clk = ~clk;
initial begin
reset = 1; #10; // Reset active
reset = 0; // Start counting
#200;
$finish;
end
endmodule
DOWN:
`timescale 1ns/1ps
module down_counter(
input clk,
input reset,
output reg [3:0] count
);
always @(posedge clk) begin
if (reset)
count <= 4'b1111;
else
count <= count - 1;
end
endmodule
`timescale 1ns/1ps
module tb_down_counter;
reg clk, reset;
wire [3:0] count;
down_counter dut(clk, reset, count);
initial clk = 0;
always #5 clk = ~clk;
initial begin
reset = 1; #10; // counter = 1111
reset = 0; // start counting down
#200;
$finish;
end
endmodule
UP_DOWN:
`timescale 1ns/1ps
module updown_counter(
input clk,
input reset,
input mode, // 1 = UP, 0 = DOWN
output reg [3:0] count
);
always @(posedge clk) begin
if (reset)
count <= 4'b0000;
else if (mode)
count <= count + 1; // UP
else
count <= count - 1; // DOWN
end
endmodule
`timescale 1ns/1ps
module tb_updown_counter;
reg clk, reset, mode;
wire [3:0] count;
updown_counter dut(clk, reset, mode, count);
initial clk = 0;
always #5 clk = ~clk;
initial begin
reset = 1; mode = 1; #10; // reset + UP mode
reset = 0;
mode = 1; #50; // count UP
mode = 0; #50; // count DOWN
mode = 1; #50; // count UP again
$finish;
end
endmodule
USING JK:`timescale 1ns/1ps
module jk_ff(
input clk,
input reset,
input j,
input k,
output reg q
);
always @(posedge clk) begin
if (reset)
q <= 0;
else begin
case ({j,k})
2'b00: q <= q;
2'b01: q <= 0;
2'b10: q <= 1;
2'b11: q <= ~q;
endcase
end
end
endmodule
UP:
`timescale 1ns/1ps
module jk_up_counter(
input clk,
input reset,
output [3:0] q
);
wire J0=1, K0=1;
wire J1=q[0], K1=q[0];
wire J2=q[1] & q[0], K2=q[1] & q[0];
wire J3=q[2] & q[1] & q[0],
K3=q[2] & q[1] & q[0];
jk_ff FF0(clk, reset, J0, K0, q[0]);
jk_ff FF1(clk, reset, J1, K1, q[1]);
jk_ff FF2(clk, reset, J2, K2, q[2]);
jk_ff FF3(clk, reset, J3, K3, q[3]);
endmodule
`timescale 1ns/1ps
module tb_jk_up_counter;
reg clk, reset;
wire [3:0] q;
jk_up_counter dut(clk, reset, q);
initial clk = 0;
always #5 clk = ~clk;
initial begin
reset = 1; #10;
reset = 0;
#200;
$finish;
end
endmodule
DOWN:
`timescale 1ns/1ps
module jk_down_counter(
input clk,
input reset,
output [3:0] q
);
wire J0=1, K0=1;
wire J1=~q[0], K1=~q[0];
wire J2=~q[1] & ~q[0], K2=~q[1] & ~q[0];
wire J3=~q[2] & ~q[1] & ~q[0],
K3=~q[2] & ~q[1] & ~q[0];
jk_ff FF0(clk, reset, J0, K0, q[0]);
jk_ff FF1(clk, reset, J1, K1, q[1]);
jk_ff FF2(clk, reset, J2, K2, q[2]);
jk_ff FF3(clk, reset, J3, K3, q[3]);
endmodule
`timescale 1ns/1ps
module tb_jk_down_counter;
reg clk, reset;
wire [3:0] q;
jk_down_counter dut(clk, reset, q);
initial clk = 0;
always #5 clk = ~clk;
initial begin
reset = 1; #10;
reset = 0;
#200;
$finish;
end
endmodule
UPDOWN:
`timescale 1ns/1ps
module jk_updown_counter(
input clk,
input reset,
input mode,
output [3:0] q
);
// UP
wire J1u = q[0];
wire J2u = q[1] & q[0];
wire J3u = q[2] & q[1] & q[0];
// DOWN
wire J1d = ~q[0];
wire J2d = ~q[1] & ~q[0];
wire J3d = ~q[2] & ~q[1] & ~q[0];
wire J0=1, K0=1;
wire J1 = mode ? J1u : J1d;
wire K1 = J1;
wire J2 = mode ? J2u : J2d;
wire K2 = J2;
wire J3 = mode ? J3u : J3d;
wire K3 = J3;
jk_ff FF0(clk, reset, J0, K0, q[0]);
jk_ff FF1(clk, reset, J1, K1, q[1]);
jk_ff FF2(clk, reset, J2, K2, q[2]);
jk_ff FF3(clk, reset, J3, K3, q[3]);
endmodule
`timescale 1ns/1ps
module tb_jk_updown_counter;
reg clk, reset, mode;
wire [3:0] q;
jk_updown_counter dut(clk, reset, mode, q);
initial clk = 0;
always #5 clk = ~clk;
initial begin
reset = 1; mode = 1; #10; // reset + UP
reset = 0;
mode = 1; #60; // UP count
mode = 0; #60; // DOWN count
mode = 1; #60; // UP again
$finish;
end
endmodule
SYNCHROUNOUS USING T:
`timescale 1ns/1ps
module t_ff(
input clk,
input reset,
input T,
output reg Q
);
always @(posedge clk) begin
if (reset)
Q <= 0;
else if (T)
Q <= ~Q;
else
Q <= Q;
end
endmodule
UP:
`timescale 1ns/1ps
module t_up_counter(
input clk,
input reset,
output [3:0] Q
);
wire T0 = 1;
wire T1 = Q[0];
wire T2 = Q[1] & Q[0];
wire T3 = Q[2] & Q[1] & Q[0];
t_ff FF0(clk, reset, T0, Q[0]);
t_ff FF1(clk, reset, T1, Q[1]);
t_ff FF2(clk, reset, T2, Q[2]);
t_ff FF3(clk, reset, T3, Q[3]);
endmodule
`timescale 1ns/1ps
module tb_t_up_counter;
reg clk, reset;
wire [3:0] Q;
t_up_counter dut(clk, reset, Q);
initial clk = 0;
always #5 clk = ~clk;
initial begin
reset = 1; #10;
reset = 0;
#200;
$finish;
end
endmodule
DOWN:
`timescale 1ns/1ps
module t_down_counter(
input clk,
input reset,
output [3:0] Q
);
wire T0 = 1;
wire T1 = ~Q[0];
wire T2 = ~Q[1] & ~Q[0];
wire T3 = ~Q[2] & ~Q[1] & ~Q[0];
t_ff FF0(clk, reset, T0, Q[0]);
t_ff FF1(clk, reset, T1, Q[1]);
t_ff FF2(clk, reset, T2, Q[2]);
t_ff FF3(clk, reset, T3, Q[3]);
endmodule
`timescale 1ns/1ps
module tb_t_down_counter;
reg clk, reset;
wire [3:0] Q;
t_down_counter dut(clk, reset, Q);
initial clk = 0;
always #5 clk = ~clk;
initial begin
reset = 1; #10;
reset = 0;
#200;
$finish;
end
endmodule
UP_DOWN:
`timescale 1ns/1ps
module t_updown_counter(
input clk,
input reset,
input mode,
output [3:0] Q
);
// UP mode T signals
wire Tup1 = Q[0];
wire Tup2 = Q[1] & Q[0];
wire Tup3 = Q[2] & Q[1] & Q[0];
// DOWN mode T signals
wire Tdn1 = ~Q[0];
wire Tdn2 = ~Q[1] & ~Q[0];
wire Tdn3 = ~Q[2] & ~Q[1] & ~Q[0];
wire T0 = 1;
wire T1 = mode ? Tup1 : Tdn1;
wire T2 = mode ? Tup2 : Tdn2;
wire T3 = mode ? Tup3 : Tdn3;
t_ff FF0(clk, reset, T0, Q[0]);
t_ff FF1(clk, reset, T1, Q[1]);
t_ff FF2(clk, reset, T2, Q[2]);
t_ff FF3(clk, reset, T3, Q[3]);
endmodule
`timescale 1ns/1ps
module tb_t_updown_counter;
reg clk, reset, mode;
wire [3:0] Q;
t_updown_counter dut(clk, reset, mode, Q);
initial clk = 0;
always #5 clk = ~clk;
initial begin
reset = 1; mode = 1; #10;
reset = 0;
mode = 1; #60; // UP
mode = 0; #60; // DOWN
mode = 1; #60; // UP again
$finish;
end
endmodule
RCA AND ARRAY:
FA:
`timescale 1ns/1ps
module full_adder(
input a, b, cin,
output sum, cout
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (b & cin) | (a & cin);
endmodule
RCA:
module ripple_carry_adder_4bit(
input [3:0] a, b,
input cin,
output [3:0] sum,
output cout
);
wire c1, c2, c3;
full_adder fa0(a[0], b[0], cin, sum[0], c1);
full_adder fa1(a[1], b[1], c1, sum[1], c2);
full_adder fa2(a[2], b[2], c2, sum[2], c3);
full_adder fa3(a[3], b[3], c3, sum[3], cout);
endmodule
module tb_ripple_carry_adder_4bit;
reg [3:0] a, b;
reg cin;
wire [3:0] sum;
wire cout;
ripple_carry_adder_4bit uut(a, b, cin, sum, cout);
initial begin
a=0; b=0; cin=0; #10;
a=4'b0101; b=4'b0011; cin=0; #10;
a=4'b1100; b=4'b0110; cin=1; #10;
a=4'b1111; b=4'b1111; cin=0; #10;
a=4'b1001; b=4'b0111; cin=1; #10;
$stop;
end
endmodule
ARRAY:
module array_multiplier_4x4(
input [3:0] a, b,
output [7:0] p
);
// Partial products
wire [3:0] pp0 = a & {4{b[0]}};
wire [3:0] pp1 = a & {4{b[1]}};
wire [3:0] pp2 = a & {4{b[2]}};
wire [3:0] pp3 = a & {4{b[3]}};
// Internal wires for sums and carries
wire c1, c2, c3, c4;
wire s11, s12, s13;
wire c5, c6, c7;
wire s21, s22;
wire c8, c9, c10;
// First row
assign p[0] = pp0[0];
full_adder FA11(pp0[1], pp1[0], 0, s11, c1);
full_adder FA12(pp0[2], pp1[1], c1, s12, c2);
full_adder FA13(pp0[3], pp1[2], c2, s13, c3);
full_adder FA14(0, pp1[3], c3, p[4], c4);
// Second row
full_adder FA21(pp2[0], s11, 0, p[1], c5);
full_adder FA22(pp2[1], s12, c5, s21, c6);
full_adder FA23(pp2[2], s13, c6, s22, c7);
full_adder FA24(pp2[3], c4, c7, p[5], c8);
// Third row
full_adder FA31(pp3[0], s21, 0, p[2], c9);
full_adder FA32(pp3[1], s22, c9, p[3], c10);
full_adder FA33(pp3[2], p[5], c10, p[6], p[7]); // Last stage
endmodule
module tb_array_multiplier_4x4;
reg [3:0] a, b;
wire [7:0] p;
array_multiplier_4x4 uut(a, b, p);
initial begin
a=0; b=0; #10;
a=4'b0011; b=4'b0101; #10;
a=4'b1111; b=4'b1111; #10;
a=4'b1010; b=4'b0110; #10;
a=4'b1100; b=4'b0011; #10;
a=4'b0111; b=4'b0101; #10;
$stop;
end
endmodule
Overlapping Sequence Detector:
`timescale 1ns / 1ps
module overlap_seqx_detector(
input clk,
input rst,
input in,
output reg out
);
// State encoding
parameter s0 = 2'b00;
parameter s1 = 2'b01;
parameter s2 = 2'b10;
parameter s3 = 2'b11;
reg [1:0] state;
always @(posedge clk) begin
if (rst) begin
state <= s0;
out <= 0;
end
else begin
out <= 0; // default output
case (state)
// No match yet
s0: begin
if (in == 0)
state <= s1;
else
state <= s0;
end
// 0 seen
s1: begin
if (in == 1)
state <= s2;
else
state <= s1; // stay in s1 for 0
end
// 01 seen
s2: begin
if (in == 1)
state <= s3; // 011
else
state <= s1; // restart from 0
end
// 011 seen
s3: begin
if (in == 0) begin
out <= 1; // MATCH: 0110
state <= s1; // allow overlap
end
else begin
state <= s0; // wrong, reset
end
end
default: begin
state <= s0;
out <= 0;
end
endcase
end
end
endmodule
`timescale 1ns / 1ps
module seqx_det_test_bench();
reg clk = 0, rst = 0, din = 0;
wire out;
overlap_seqx_detector dut(clk, rst, din, out);
// Clock: period = 40ns
always #20 clk = ~clk;
initial begin
// Reset
rst = 1; #40;
rst = 0;
// Apply sequence
din = 1; #40;
din = 0; #40;
din = 1; #40;
din = 0; #40;
din = 1; #40;
din = 1; #40;
din = 0; #40;
din = 1; #40;
din = 1; #40;
din = 0; #40;
din = 1; #40;
#200 $finish;
end
endmodule
Non-Overlapping:
`timescale 1ns / 1ps
module nonoverlap_seqx_detector(
input clk,
input rst,
input in,
output reg out
);
// State Encoding
parameter S0 = 3'b000; // no match
parameter S1 = 3'b001; // got 0
parameter S2 = 3'b010; // got 01
parameter S3 = 3'b011; // got 011
parameter S4 = 3'b100; // got 0110 → FINAL (no overlap)
reg [2:0] state, next_state;
// Next state logic
always @(*) begin
case (state)
S0: next_state = (in == 0) ? S1 : S0;
S1: next_state = (in == 1) ? S2 : S1;
S2: next_state = (in == 1) ? S3 : S1;
S3: next_state = (in == 0) ? S4 : S0;
S4: next_state = S0; // NON-OVERLAP → reset after detection
default: next_state = S0;
endcase
end
// Output logic (Moore)
always @(*) begin
out = (state == S4); // output goes high ONLY in final state
end
// State update
always @(posedge clk or posedge rst) begin
if (rst)
state <= S0;
else
state <= next_state;
end
endmodule
`timescale 1ns / 1ps
module tb_nonoverlap_seqx_detector();
reg clk = 0, rst = 0, din = 0;
wire out;
nonoverlap_seqx_detector dut(clk, rst, din, out);
always #20 clk = ~clk; // 40ns clock period
initial begin
// Apply reset
rst = 1; #40;
rst = 0;
// Test sequence: 0 1 1 0 1 0 1 1 0 0 1
din = 0; #40;
din = 1; #40;
din = 1; #40;
din = 0; #40; // DETECT → out = 1 (only once, no overlap)
din = 1; #40;
din = 0; #40;
din = 1; #40;
din = 1; #40;
din = 0; #40;
din = 0; #40;
din = 1; #40;
#200 $finish;
end
endmodule
D FLIP-FLOP:
`timescale 1ns/1ps
module d_flip_flop(
input wire D,
input wire clk,
input wire rst,
output reg Q
);
always @(posedge clk or posedge rst) begin
if (rst)
Q <= 1'b0;
else
Q <= D;
end
endmodule
MUX:
`timescale 1ns/1ps
module mux4to1(
input wire i0, i1, i2, i3,
input wire [1:0] sel,
output wire y
); assign y = (sel == 2'b00) ? i0 :
(sel == 2'b01) ? i1 :
(sel == 2'b10) ? i2 :
i3;
endmodule
SISO:
`timescale 1ns/1ps
module siso(
input clk,
input rst,
input serial_in,
output serial_out
);
wire q1, q2, q3, q4;
d_flip_flop f1(.D(serial_in), .clk(clk), .rst(rst), .Q(q1));
d_flip_flop f2(.D(q1), .clk(clk), .rst(rst), .Q(q2));
d_flip_flop f3(.D(q2), .clk(clk), .rst(rst), .Q(q3));
d_flip_flop f4(.D(q3), .clk(clk), .rst(rst), .Q(q4));
assign serial_out = q4;
endmodule
`timescale 1ns/1ps
module siso_tb;
reg clk, rst, serial_in;
wire serial_out;
siso uut(.clk(clk), .rst(rst), .serial_in(serial_in), .serial_out(serial_out));
always #5 clk = ~clk; // Clock toggle every 5ns
initial begin
clk = 0;
rst = 1;
serial_in = 0;
#10 rst = 0; // Release reset
serial_in = 1; #10;
serial_in = 0; #10;
serial_in = 1; #10;
serial_in = 1; #10;
serial_in = 0; #20;
$stop;
end
endmodule
SIPO:
`timescale 1ns/1ps
module sipo(
input clk,
input rst,
input serial_in,
output [3:0] parallel_out
);
wire q1, q2, q3, q4;
d_flip_flop f1(.D(serial_in), .clk(clk), .rst(rst), .Q(q1));
d_flip_flop f2(.D(q1), .clk(clk), .rst(rst), .Q(q2));
d_flip_flop f3(.D(q2), .clk(clk), .rst(rst), .Q(q3));
d_flip_flop f4(.D(q3), .clk(clk), .rst(rst), .Q(q4));
assign parallel_out = {q4, q3, q2, q1};
endmodule
`timescale 1ns/1ps
module sipo_tb;
reg clk, rst, serial_in;
wire [3:0] parallel_out;
sipo uut(.clk(clk), .rst(rst), .serial_in(serial_in), .parallel_out(parallel_out));
always #5 clk = ~clk;
initial begin
clk = 0; rst = 1; serial_in = 0;
#10 rst = 0;
serial_in = 1; #10;
serial_in = 0; #10;
serial_in = 1; #10;
serial_in = 1; #10;
serial_in = 0; #20;
$stop;
end
endmodule
PISO:
`timescale 1ns/1ps
module piso(
input clk,
input rst,
input load,
input [3:0] parallel_in,
output serial_out
);
reg [3:0] temp;
always @(posedge clk or posedge rst) begin
if (rst)
temp <= 4'b0000;
else if (load)
temp <= parallel_in;
else
temp <= {1'b0, temp[3:1]}; // Shift right
end
assign serial_out = temp[0];
endmodule
`timescale 1ns/1ps
module piso_tb;
reg clk, rst, load;
reg [3:0] parallel_in;
wire serial_out;
piso uut(.clk(clk), .rst(rst), .load(load), .parallel_in(parallel_in), .serial_out(serial_out));
always #5 clk = ~clk;
initial begin
clk = 0; rst = 1; load = 0; parallel_in = 4'b1011;
#10 rst = 0;
load = 1; #10;
load = 0; #50;
$stop;
end
endmodule
PIPO:
`timescale 1ns/1ps
module pipo(
input clk,
input rst,
input [3:0] parallel_in,
output reg [3:0] parallel_out
);
always @(posedge clk or posedge rst) begin
if (rst)
parallel_out <= 4'b0000;
else
parallel_out <= parallel_in;
end
endmodule
`timescale 1ns/1ps
module pipo_tb;
reg clk, rst;
reg [3:0] parallel_in;
wire [3:0] parallel_out;
pipo uut(.clk(clk), .rst(rst), .parallel_in(parallel_in), .parallel_out(parallel_out));
always #5 clk = ~clk;
initial begin
clk = 0; rst = 1; parallel_in = 4'b0000;
#10 rst = 0;
parallel_in = 4'b1010; #10;
parallel_in = 4'b1111; #10;
parallel_in = 4'b0101; #10;
parallel_in = 4'b0011; #10;
$stop;
end
endmodule
USR:
module mux4to1(
output y,
input i0, i1, i2, i3,
input s1, s0
);
assign y = (s1 == 0 && s0 == 0) ? i0 :
(s1 == 0 && s0 == 1) ? i1 :
(s1 == 1 && s0 == 0) ? i2 :
i3;
endmodule
module dff(output reg q, input d, input clk);
always @(posedge clk)
q <= d;
endmodule
`timescale 1ns/1ps
module universal_shift_reg(
output [3:0] q,
input clk,
input s1, s0,
input [3:0] pl,
input rin,
input lin
);
wire [3:0] d;
mux4to1 m0(d[0], q[0], q[1], lin, pl[0], s1, s0);
mux4to1 m1(d[1], q[1], q[2], q[0], pl[1], s1, s0);
mux4to1 m2(d[2], q[2], q[3], q[1], pl[2], s1, s0);
mux4to1 m3(d[3], q[3], rin, q[2], pl[3], s1, s0);
dff f0(q[0], d[0], clk);
dff f1(q[1], d[1], clk);
dff f2(q[2], d[2], clk);
dff f3(q[3], d[3], clk);
endmodule
`timescale 1ns/1ps
module universal_shift_reg_tb;
reg clk, s1, s0, rin, lin;
reg [3:0] pl;
wire [3:0] q;
universal_shift_reg uut(q, clk, s1, s0, pl, rin, lin);
always #5 clk = ~clk;
initial begin
clk = 0;
// Parallel Load
pl = 4'b1010; rin = 0; lin = 0;
s1 = 1; s0 = 1; #10;
// Hold
s1 = 0; s0 = 0; #10;
// Shift Right
s1 = 0; s0 = 1; rin = 1; #10;
// Shift Left
s1 = 1; s0 = 0; lin = 0; #10;
$stop;
end
endmodule
Single Port RAM by General Method:
`timescale 1ns/1ps
module single_port_ram(
input clk,
input reset,
input we,
input [5:0] addr,
input [7:0] d_in,
output reg [7:0] d_out
);
reg [7:0] mem [63:0]; // 64 x 8 RAM
integer i;
always @(posedge clk) begin
if (reset) begin
// Clear all memory locations
for (i = 0; i < 64; i = i + 1)
mem[i] <= 8'b00000000;
end
else begin
if (we)
mem[addr] <= d_in; // WRITE
else
d_out <= mem[addr]; // READ
end
end
endmodule
`timescale 1ns/1ps
module tb_single_port_ram();
reg clk;
reg reset;
reg we;
reg [5:0] addr;
reg [7:0] d_in;
wire [7:8] d_out;
single_port_ram dut(clk, reset, we, addr, d_in, d_out);
// Clock generation
always #40 clk = ~clk;
initial begin
clk = 0;
reset = 1;
we = 0;
addr = 0;
d_in = 0;
// Hold reset for some time
#160 reset = 0;
// WRITE operation 1
#80 we = 1; d_in = 8'b10101010; addr = 6'b101101;
// READ from same address
#80 we = 0; addr = 6'b101101;
// WRITE operation 2
#80 we = 1; d_in = 8'b11101110; addr = 6'b001101;
// READ from same address
#80 we = 0; addr = 6'b001101;
#200 $stop;
end
endmodule