Examination
MC
last name, first name: Matr.-Nummer:
permitted ruler, pen (no red, please)
Part 1: closed notes and books, no calculators
Part 2: open notes (printed or self-composed, slides),
simple hand-held calculator
not permitted computers / laptops, mobile communication devices
communication with other examinees
rules Do not detach any pages!
Write your answers clearly (legibly) in the spaces (lines, boxes, plots, tables)
provided.
If you need more space use clear pages in this booklet (at the end of each
part), do not use your own paper.
Your solutions must be traceable (reasoning, calculation details).
Start of exam: turn this sheet only when official start is announced.
End of exam: return your exam papers to the examiner immediately when
instructed to do so. Your examiner will give an indication 5 minutes before the
official end.
score
Part 1 Part 2
Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Note
10 10 10 10 3 22 15 10 10 100
PART 1
closed book, closed notes, 45 minutes
QUESTION 1: MEMORY
POINTER OPERATIONS [6P]
Provide the content of arr after executing the code below.
unsigned int arr[6] = { 0xA, 0xB, 0xC, 0xD, 0xE, 0xF };
unsigned int * p = &arr[1];
unsigned int i;
for (i = 0; i < 3; ++i)
{
p[0] = *(p - 1);
p += 2;
}
arr[0] arr[1] arr[2] arr[3] arr[4] arr[5]
QUESTION 2 [10P]: ADDRESS DECODING
Consider the following module and its address decoder.
Figure 1: Address decoder
Is 0x3A0 a valid start address of the module? Explain your answer.
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PART 2
open book, open notes, 90 minutes
last name, first name: Matr.-Nummer:
Converter from UART to a parallel output
INTRODUCTION
Figure 2: System architecture
The 24MHz clocked TIVA TM4C1294 Microcontroller (μC) shall be operated as the converter between
UART and the serial output (GPIO port B).
The bit pattern on pins PB1 bis PB3 of the GPIO port is given by the content of incoming UART frames
(7/E/2) received on the pin PB0 of the same port. In the frames, only the 3 least significant bits (D0-D2)
matter. Bit D0 defines the pin PB1, D1 the pin PB2, etc.
Additionally, the pin PB7 shall generate a clock signal with period of 30ms and 50% duty cycle.
The states of the output pins (PB1 to PB3 und PB7) should be set in the ISR of the Timer 5B (16 bit mode).
The function should be executed every 15ms. Furthermore, the states of the pins PB1 to PB3 are allowed
to change only at the falling edge of the clock signal (PB7) and only when a new UART frame has been
received. Initially, after reset, all output pins should be low.
There are no further interrupts. The entire software operation is interrupt based. The main program
consists of a configuration part and an empty while(1); loop only.
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QUESTION 5 [3P]: PIN CONFIGURATION
List all UART modules of the TIVA TM4C1294 µC which can be used in the configuration described above.
Justify your answer in one sentence.
QUESTION 7 [15P]: TIMER
The timer should be operated in down, periodic, and 16 it mode. The ISR should be executed upon time-
out every 15ms.
PRESCALER [3P]
For which CPU frequencies there would be no need for a prescaler?
HW CONFIGURATION [6P]
Configure the following registers of the timer module following the overall system description and the
comments below. Remember that certain registers might be used by other applications running on the µC.
Not relevant bits should stay unchanged.
SYSCTL_RCGCTIMER_R |= (1<<5); // clock
while (!(SYSCTL_PRTIMER_R & (1<<5))); // „busy-wait“ for the activation
_______________________________________________________; // disable timer
TIMER5_CFG_R = 0x04; // 16-Bit
TIMER5_TBMR_R = 0x2; // periodic, down, no match
TIMER5_TBPR_R = ______________________________________; // prescaler register
TIMER5_TBILR_R = ______________________________________; // load register
_______________________________________________________; // enable timer
IRQ CONFIGURATION [6P]
Configure further necessary registers (in module nd NVIC) such that the time-out leads to the IRQ.
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QUESTION 9 [10P]: ISR (BIT-BANGING)
Implement the ISR which handles the interrupts requested by the Timer 5B time-outs.
The ISR controls the states of the GPIO port B output pins, including the generated clock (PB7) and the
parallel output (PB1-PB3). Read carefully the task description concerning the timing of the pin state
changes!
Note that the ISR muss process (read) the incoming UART1 frames.
A hint. Use the global variable iterationId (it keeps its value between the executions of ISR) to generate
the clock on PB7 and decide if the pins PB1-PB3 can change. Increment the variable in every ISR execution.
One can implement the ISR functionality also without global variables.
In order to avoid unnecessary glitches, the register GPIO_PORTB_DATA_R should be written to only once
during every ISR execution. You will get an extra point if produce such a solution.
Comment you code and make your solution understandable and traceable!
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uint32_t iterationId = 0; // global variable
void timerIsr(void) {
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