Gaddam Rishithaa
21110063
EE-626 Microfabrication and Semiconductor Processes
Assignment-2
Layout of the P-type MOS-Capacitance
Q1) C-V graph of given MOS-Capacitance at different frequencies:
Observations:
● The accumulation → depletion dip → return to high capacitance in inversion (≈
CoxC_{ox}Cox) is depicted by the low-frequency (1 Hz) curve.
● The accumulation → depletion dip → no rebound in inversion is displayed by the
high-frequency (1 MHz) curve, which stays at the lower series value.
● The depletion region where CdepC_{dep}Cdepis highest in impedance (i.e., smallest
capacitance) is where the capacitance minimum occurs.
● Minority-carrier response is directly measured by the difference between LF and HF in
inversion: Compared to the HF signal, the big difference ⇒ inversion layer is slow and
dynamic.
The inversion capacitance returns to C ox at lower frequencies (0.01–10⁻⁴ Hz), however the
observed C–V does not show the anticipated low-frequency inversion recovery at 1 Hz.
This suggests that the inversion response is governed by an effective carrier/trap time constant
that is greater than ~1 s (i.e., 𝑓𝑐<1 f c).
less than 1 Hz). For the system to achieve quasi-static equilibrium, frequencies ≪1/(2π\tau) are
consequently necessary. Slow SRH generation–recombination lifetimes, deep/slow interface
traps, or measurement RC restrictions are some potential reasons. The corner frequency can be
found via a frequency sweep of C(f) with a given inversion bias, which also enables quantitative
extraction of τ.
2Q) (C_g: Gate capacitance, C_ox: Oxide capacitance, C_d: Depletion capacitance, W_max: Maximum depletion width, N_a:
Acceptor doping concentration, V_g: Gate voltage, V_fb: Flatband voltage, V_t: Threshold voltage, φ_b: Bulk potential, φ_ms:
Metal-semiconductor work function difference, Q_ox: Oxide charge, ε_si: Silicon permittivity, q: Electron charge, n_i: Intrinsic
carrier concentration)
(I) C-V graphs with P-well doping variation
Observations:
MOS capacitor properties on a P-well at 0.01 Hz are displayed on the C-V graph with doping
levels of 1e15 cm⁻³ (red), 1e16 cm⁻³ (green), 1e17 cm⁻³ (blue), and 1e18 cm⁻³ (cyan). The
characteristic low-frequency p-type MOS behavior is shown by the capacitance (C[gg], ~0 to
2e-15 F) vs. gate voltage (V[g], ~ -1.8 to 1.8 V): high capacitance in accumulation, a minimum
in depletion, and high capacitance in inversion.
● C_min Increases with Doping: C_min rises from ~0 F (1e15 cm⁻³) to ~1e-15 F (1e18
cm⁻³), C_total = C_ox * C_d / (C_ox + C_d); higher N_a reduces depletion width,
increasing C_d.
● Depletion Width Expands with Doping: Narrow dip (1e15 cm⁻³), broader (1e18 cm⁻³),
higher N_a widens the voltage range via the √N_a term.
● Transition Steepness Decreases: Sharp for 1e15 cm⁻³, gradual for 1e18 cm⁻³,
dC_g/dV_g ∝ 1/√N_a; higher N_a spreads ΔC_g over wider ΔV_g.
● C_min and Transition Shift: C_min shifts from ~0.5 V (1e15 cm⁻³) to ~-0.2 V (1e18
cm⁻³).
● Noise in Curves: Oscillations in 1e15 cm⁻³ and 1e16 cm⁻³.
(II) C-V graphs with Different Oxide Thickness:(X-axis: Voltage(Vg), Y-axis:
Capacitance(Cgg))
Observations:
● C_max Decreases with Thicker Oxide: Because C_ox = ε_ox / t_ox, where higher t_ox
reduces capacitance, C_max decreases from ~2e-15 F (2 nm) to ~1.5e-15 F (3.5 nm).
● Thinner Oxide Increases C_min: Thinner t_ox increases C_ox, which is why C_min is
lowest (~0.5e-15 F) for 3.5 nm and greatest (~1e-15 F) for 2 nm.
● Transition Steepness Increases: At 2 nm, transitions are sharper, but at 3.5 nm, changes
are more gradual and driven by greater C_ox.
● No Significant Voltage Shift: Because V_fb and V_t, not t_ox, depend on doping,
transitions take place at comparable V_g across thicknesses.
● Consistent U-Shape: Although the magnitude varies with t_ox, all curves maintain the
common low-frequency C-V shape.
(III) C-V graphs with Fixed Oxide charges in SiO2 (-1e12 cm−2, 0 ,1e12 cm−2 ):
Observations:
● The maximum capacitance (C_max) decreases from ~2e-15 F (2 nm) to ~1.5e-15 F (3.5
nm) due to C_ox = ε_ox / t_ox, where a thicker oxide layer (t_ox) reduces capacitance.
● The minimum capacitance (C_min) increases from ~0.5e-15 F (3.5 nm) to ~1e-15 F (2
nm) as thinner oxides enhance C_ox, improving the total capacitance (C_total = C_ox *
C_d / (C_ox + C_d)).
● The transition steepness increases with thinner oxides, with sharper shifts for 2 nm
compared to gradual transitions for 3.5 nm, driven by higher C_ox affecting dC_g/dV_g.
● No significant voltage shift occurs with thickness variations, as V_fb and V_t are
determined by doping rather than t_ox.
● All curves retain the characteristic U-shape typical of low-frequency C-V behavior.
(IV) C-V graphs with Varying Temperature (250K, 300K, 350K).
Observations:
● Temperature-Related Shift in the C-V Curve: As the temperature rises from 250 K to
350 K, the curve slightly moves to the right, signifying a voltage offset. φ_b = (kT/q)
ln(N_a / n_i) affects V_fb and V_t. As temperature rises, n_i decreases φ_b and shifts the
curve in a positive direction.
● C_min and C_max Not Affected: C_min ~0.5e-15 F and C_max ~2e-15 F are the least
and maximum, respectively. Since oxide thickness and doping are the key determinants
of C_ox and C_d, capacitances stay comparable.
● Transition Steepness Increases: Because of increased carrier production, transitions
from depletion to inversion grow steeper as temperatures rise.
● Variation in Inversion Onset: Because of the larger intrinsic carrier concentration at
higher temperatures (350 K), inversion starts at a more positive V_g.
● At 250 K, the curve is positioned leftward compared to higher temperatures, reflecting a
more negative V_fb and V_t due to φ_b = (kT/q) ln(N_a / n_i), where a lower
temperature reduces n_i, increasing φ_b and shifting the curve negatively. The maximum
(C_max ~2e-15 F) and minimum (C_min ~0.5e-15 F) capacitances remain similar across
all temperatures, as C_ox and C_d are determined by oxide thickness and doping, while
transition steepness from depletion to inversion is less pronounced at 250 K due to
reduced carrier generation compared to 350 K. Inversion begins at more negative V_g for
250 K due to the lower intrinsic carrier concentration. These observations highlight that a
temperature of 250 K shifts the C-V curve leftward with gentler transitions, impacting
MOSFET performance in integrated circuits under low-temperature conditions.
(V) C-V graphs with Change poly doping type to N+ Poly:
Observations:
The given C-V curve for N+ poly gate doping at 0.01 Hz, detailing capacitance (C_g, ~0 to
2e-15 F) against gate voltage (V_g, ~ -1.5 to 1.5 V), illustrates traits that correspond with the
anticipated behavior during the transition from P-type to N-type poly gate doping, although some
distinctions are evident. As anticipated, the curve changes polarity: significant capacitance is
observed in accumulation at positive V_g (~1 V) and in inversion at negative V_g (~ -1 V), with
the lowest capacitance (C_min ~0.5e-15 F) occurring close to 0 V_g, indicating the N+ gate's
work function (φ_m ≈ 4.1 eV) which favors electron accumulation and hole inversion,
contrasting with the P-type gate's inclination towards hole accumulation. The flatband voltage
(V_fb) and threshold voltage (V_t) display a more negative shift, which aligns with the
difference in φ_m; however, the precise shift varies based on substrate doping and oxide charge.
The graph shows considerable fluctuations, especially in the inversion (negative V_g) and
accumulation (positive V_g) areas, which surpass the usual noise anticipated from interface
states, potentially suggesting simulation artifacts or an excessively high N+ doping
concentration. The U-shape continues to be asymmetric, featuring a sharper increase in
accumulation compared to inversion, consistent with the anticipated doping mismatch but more
evident than expected, indicating possible gate-substrate interaction influences. In general, the
graph validates the polarity reversal and voltage shift, yet the increased noise and asymmetry
indicate deviations potentially resulting from experimental or simulation conditions
“SDE-CODE”
(sdegeo:create-rectangle (position 0 0 0) (position 2.28 0.5 0) "Silicon" "PSubsrtate_region")
(sdegeo:create-rectangle (position 0 0.5 0) (position 2.28 5.5 0) "Silicon" "PWell_region")
(sdegeo:create-rectangle (position 0 5 0) (position 0.5 5.5 0) "Silicon" "Pbody_region")
(sde:define-parameter "fillet-radius" 0.5 )
(sdegeo:fillet-2d (list (car (find-vertex-id (position 0.5 5 0)))) 0.5)
(sdegeo:create-rectangle (position 0.5 5 0) (position 1.1 5.5 0) "SiO2" "STI_region")
(sdegeo:move-vertex (car (find-vertex-id (position 0.5 5 0))) (position 0.55 5 0))
(sdegeo:move-vertex (car (find-vertex-id (position 1.1 5 0))) (position 1.05 5 0))
(sdegeo:create-rectangle (position 1.6 5.5 0) (position 1.78 5.503 0) "SiO2"
"GateOxide_region")
(sdegeo:create-rectangle (position 1.6 5.503 0) (position 1.78 5.513 0) "PolySi"
"PolyGate_region")
(sdegeo:define-contact-set "Oxide_Contact" 4 (color:rgb 1 0 0 ) "##")
(sdegeo:define-contact-set "Gate_Contact" 4 (color:rgb 1 1 0 ) "##")
(sdegeo:set-current-contact-set "Oxide_Contact")
(sdegeo:set-contact (list (car (find-edge-id (position 0.25 5.5 0)))) "Oxide_Contact")
(sdegeo:set-current-contact-set "Gate_Contact")
(sdegeo:set-contact (list (car (find-edge-id (position 1.69 5.513 0)))) "Gate_Contact")
(sdedr:define-constant-profile "Psubstrate" "BoronActiveConcentration" 1e15)
(sdedr:define-constant-profile-region "PSubstrate_placement" "Psubstrate" "PSubsrtate_region")
(sdedr:define-constant-profile "Psubstrate1" "BoronActiveConcentration" 1e+16)
(sdedr:define-constant-profile-region "Pwell_placement" "Psubstrate1" "PWell_region")
(sdedr:define-constant-profile "Body" "BoronActiveConcentration" 5e+20)
(sdedr:define-constant-profile-region "Pbody_placement" "Body" "Pbody_region")
(sdedr:define-constant-profile "Pgate" "BoronActiveConcentration" 5e20)
(sdedr:define-constant-profile-region "PGate_placement" "Pgate" "PolyGate_region")
(sdedr:define-refeval-window "WellOxide_Mesh" "Rectangle" (position 1.58 5.46 0) (position
1.8 .502 0))
(sdedr:define-refinement-size "RefinementDefinition_1" 0.03 0.03 0.02 0.02 )
(sdedr:define-refinement-placement "RefinementPlacement_1" "RefinementDefinition_1" (list
"window" "WellOxide_Mesh" ) )
(sdedr:define-refeval-window "OxideGate_mesh" "Rectangle" (position 1.58 5.502 0) (position
1.8 5.515 0))
(sdedr:define-refinement-size "RefinementDefinition_2" 0.02 0.02 0.01 0.01 )
(sdedr:define-refinement-placement "RefinementPlacement_2" "RefinementDefinition_2" (list
"window" "OxideGate_mesh" ) )
(sdedr:define-refeval-window "BigMesh" "Rectangle" (position -0.6637 6.3743 0) (position
2.6576 -0.6457 0))
(sdedr:define-refinement-size "RefinementDefinition_3" 0.08 0.08 0.05 0.05 )
(sdedr:define-refinement-placement "RefinementPlacement_3" "RefinementDefinition_3" (list
"window" "BigMesh" ) )
(sde:build-mesh "-AI" "n@node@_msh")
“sdevice-CODE”
#setdep @previous@
Device "MOS" {
File {
Grid = "@tdr@"
Plot = "@tdrdat@"
*Parameter = "@parameter@"
Current = "@plot@"
* Note: No "Output=" here!
}
Electrode {
{ Name="Oxide_Contact" Voltage=0.0 }
{ Name="Gate_Contact" Voltage=0.0 }
Physics {
Fermi
EffectiveIntrinsicDensity( OldSlotboom )
Mobility(
DopingDep
eHighFieldsaturation( GradQuasiFermi )
hHighFieldsaturation( GradQuasiFermi )
Enormal
)
Recombination(
SRH( DopingDep TempDependence )
)
}
} * End of Device{}
Plot {
*--Density and Currents, etc
eDensity hDensity
TotalCurrent/Vector eCurrent/Vector hCurrent/Vector
eMobility hMobility
eVelocity hVelocity
eQuasiFermi hQuasiFermi
*--Temperature
eTemperature Temperature * hTemperature
*--Fields and charges
ElectricField/Vector Potential SpaceCharge
*--Doping Profiles
Doping DonorConcentration AcceptorConcentration
*--Generation/Recombination
SRH Band2BandGeneration * Auger
ImpactIonization eImpactIonization hImpactIonization
*--Driving forces
eGradQuasiFermi/Vector hGradQuasiFermi/Vector
eEparallel hEparallel eENormal hENormal
*--Band structure/Composition
BandGap
BandGapNarrowing
Affinity
ConductionBand ValenceBand
eQuantumPotential
}
Math {
RelErrControl
Digits=5 * (default)
ErrRef(electron)=1.e10 * (default)
ErrRef(hole)=1.e10 * (default)
Iterations=20
Notdamped=100
Method=Blocked
SubMethod=Super
ACMethod=Blocked
ACSubMethod=Super
}
File {
Output = "@log@"
ACExtract = "@acplot@"
}
System {
*-Physical devices:
MOS nmos1 ( "Gate_Contact"=g "Oxide_Contact"=b )
*-Lumped elements:
Vsource_pset vg (g 0) { dc = 0.0 }
Vsource_pset vb (b 0) { dc = 0.0 }
}
Solve {
NewCurrentPrefix="init_"
Coupled(Iterations=100){ Poisson }
Coupled{ Poisson Electron Hole }
Quasistationary (
InitialStep=0.1 Increment=1.3
MaxStep=0.5 Minstep=1.e-5
Goal { Parameter=[Link] Voltage=-1.80 }
){ Coupled { Poisson Electron Hole } }
NewCurrentPrefix=""
Quasistationary (
InitialStep=0.01 Increment=1.3
MaxStep=0.05 Minstep=1.e-5
Goal { Parameter=[Link] Voltage=1.8 }
){ ACCoupled (
StartFrequency=@f@ EndFrequency=@f@ NumberOfPoints=1 Decade
Node(g b) Exclude(vg vb)
ACCompute (Time = (Range = (0 1) Intervals = 40))
){ Poisson Electron Hole }
}
}