Sidi Mohammed Ben Abdellah University

National School of Applied Sciences of Fes - ENSAF

2020/2021

Computer science
Industrial

6809 Microprocessor Course

1eraGMSA and GinD year

Mr. EL AFOU Youssef 1
03/06/2021
Introduction to the microprocessor
A microprocessor is a complex integrated circuit characterized
through a very large integration and endowed with faculties
of interpretation and execution of a program's instructions.
He is responsible for organizing the tasks outlined by the program and
to ensure its execution. It must also take into account the
external information to the system and ensure their processing.
It is the brain of the system. At present, a microprocessor
brings together features on a few square millimeters
always more complex. Their power continues to increase and
their clutter is regularly decreasing while always respecting,
for the moment, the famous Moore's law.

2
 Introduction to the microprocessor
Von Neumann Architecture

In a Harvard architecture, the

data and instructions circulate on
two different buses.

The first microprocessors were based on

a Von Neumann architecture while some
processors requiring more power
calculations were based on a Harvard architecture.
For a few years now, we have noticed that the
Microprocessors leverage the strengths of both.
architectures.
3
 Introduction to the microprocessor
Operation of a Von Neumann architecture

To automatically access a memory cell, a counter must be used.

This counter is considered a special register: the CO (Ordinal Counter).
The value of this counter will indicate the memory cell containing the next instruction.
to load: this corresponds to the address of the next instruction. The counter
ordinal contains an address, but the processor usually contains others
records that allow storing other addresses used within our
Assembler program. These registers are called address registers.
4
Introduction to the microprocessor
Basic elements of a microprocessor system:

03/06/2021 5
Introduction to the microprocessor
Basic elements of a microprocessor system:
The microprocessor:
Often called Central Processing Unit "CPU" which takes care of the
elementary arithmetic/logical calculations and tests.
The memory unit:
Including both RAM "RAM" and
dead memory "ROM, EPROM, ..."
This section receives the program and the data, the latter being
modified as the process unfolds.
This section also serves to memorize values
intermediate values and final values of the calculations carried out during
the execution of the program.

03/06/2021 6
Introduction to the microprocessor
Basic elements of a microprocessor system:
Input/Output interfacing:
consists of two modules: input module and output module.
The input module: contains all the devices used for sampling.

The output module: brings together all the elements that we have planned.
to transfer data and information from the computer to the
the control unit to send stored data in memory or

the different displays, the different indicators, the screens of

visualization, printers, floppy disk or disk drives
hard, Digital-to-Analog Converters 'DAC', etc.

03/06/2021 7
Introduction to the microprocessor
Elements of a microprocessor-based system:
the buses
A data bus:
Allowing the transfer of information over a bundle of several
parallel conductors. The number of wires is one of the characteristics
essentials of the UC. In principle, the width of the data bus is equal to the
size of words manipulated by the microprocessor (8 bits, 16 bits, ...).
The bus is one-way for the following three connections:
Dead Memory Microprocessor
Microprocessor Output Unit,
Entry Unit Microprocessor
The bus is bidirectional for communication with the microprocessor
with the RAM.

03/06/2021 8
Introduction to the microprocessor
Basic elements of a microprocessor system:
the buses
A bus of addresses:
a set of unidirectional parallel ducts allowing to
point all the memory addresses addressable by the computer
digital. The number of lines of this bus determines the size
maximum of memory.

example: If the number of rows of this bus is 16, the field

The memory that can be addressed is 64 Kilobytes.

03/06/2021 9
 Introduction to the microprocessor
Basic elements of a microprocessor system:
the buses
A command and control bus:

Behavioral:
Lines that allow the CPU to specify to the RAM or to
input and output ports if she wants to make a write or a
lecture.
Lines used by the CPU to respond to the peripherals, by
acceptance of a request for interruption or access
direct memory, ...

Note: The number of lines depends on the type of microprocessor used!

03/06/2021 10
 Introduction to the microprocessor
Basic elements of a microprocessor system:

03/06/2021 11
 Introduction to the microprocessor
Definition and evolution of microprocessors:
Definition:
A µP is generally a programmable integrated chip.

He is responsible for the following functions:

Take charge of instructions and data in memory.

Transfer data between memory and devices
Entry/Exit and vice versa.

React to the command signals produced by the I/O such as the

initialization signal (Reset), the corresponding signals to
interruptions, ...

03/06/2021 12
 Introduction to the microprocessor
Definition and evolution of microprocessors:
Evolution:

the first microprocessor was invented in 1971 by Intel

the first microprocessor that was marketed, on November 15
1971 is the Intel 4004 (4-bit).
the main characteristics of microprocessors manufactured by
Intel.

03/06/2021 13
 Introduction to the microprocessor
Components of a microprocessor:
The three elements
An arithmetic and logic unit (ALU).
A control unit (CU).
The registers.

These three elements are connected

between them by an internal bus,
this one allowing exchanges
of Data between the different
parts of the microprocessor.

03/06/2021 14
 Introduction to the microprocessor
Components of a microprocessor:
The UAL:
It allows you to perform arithmetic operations (+, -, *, /) and
logics (OR, AND, XOR).

Example of circuit: 74LS181, 4-bit UAL

This circuit performs arithmetic functions and
logics on A and B, with the result in F.
The operation is determined by M and by the
selection entries S0, S1, S2, and S3:
–M=1 : 16 logical functions
-M=0 : 16 arithmetic functions

03/06/2021 15
 Introduction to the microprocessor
Components of a microprocessor:
The control unit
It allows to 'sequence' the execution of instructions.
She performs the retrieval in memory of the instruction,
decoding, execution and preparation of the instruction
next. The control unit generates all the signals of
internal or external synchronization (command bus) to
microprocessor.

His role is:

to send control signals to connect the
registered on the bus;
to supervise the operation of the UAL;
to provide clock signals to the entire µP.

03/06/2021 16
 Introduction to the microprocessor
Components of a microprocessor:
The registers:

Registers are small-sized memories.

(a few bytes), fast enough for the UAL
can manipulate their content at each cycle of the clock.

Two types of registers:

the accumulators.
address registers (pointers).

03/06/2021 17
 Introduction to the microprocessor
Components of a microprocessor:
The registers:

the accumulators:

This register is used to store the data

being processed by the UAL
These are fast memories, inside the
microprocessor, which allows the ALU to
manipulate data at high speed.
Without a collector, it would be necessary
to write the results of operations directly
in memory to read them again by the
suite. (performance)

03/06/2021 18
 Introduction to the microprocessor
Components of a microprocessor:
The registers:

03/06/2021 19
 Introduction to the microprocessor
Components of a microprocessor:
The registers:
State registry:

that the different bits of this register are

the instruction register (IR):

03/06/2021 20
Introduction to the microprocessor
Components of a microprocessor:
The registers:

We can mention as a register:

. The ordinal counter (program pointer PC).
.

These are registers connected to the address bus.

03/06/2021 21
 Introduction to the microprocessor
Components of a microprocessor:
The registers:
The program counter (PC pointer):
It contains the address of the instruction to be searched in memory. The unit of

Example:
(PC)=10000H ; it points to the memory that contains the instruction MOV C,B which is
coded on two bytes (89 D9H); the control unit will increment by two
the content of the PC: (PC) =10002H (memory will be assumed to be organized
in bytes).

03/06/2021 22
 Introduction to the microprocessor
Components of a microprocessor:
The registers:
The stack pointer (SP):

memory, it allows to store information (the

and subprograms.
The stack is managed in LIFO: (Last IN First Out) last entered
first released. The operation is identical to a battery
of the plate.
The stack pointer SP points to the top of the stack, it is
decremented before each stacking, and incremented afterwards
each unstacking.
There are two instructions for pushing and popping: PUSH and
POP.

03/06/2021 23
 Introduction to the microprocessor
Components of a microprocessor:
The registers:
The stack pointer (SP):
example:
PUSH A will push the register A and POP A will pop it.

03/06/2021 24
 The 6809 microprocessor

03/06/2021 25
 The 6809 microprocessor
Introduction to the 6809 processor:
Motorola's 6809 microprocessor is an 8-bit microprocessor and the
Great successor of the 6800 whose internal organization is oriented 16 bits.
It has 59 instructions (more than 1460 instructions with all the

It includes:
An 8-bit Data bus;

Two 8-bit accumulators "A" and "B" convertible into 1

Two 16-bit index registers 'X' and 'Y'

Two stack pointer registers "U" and "S";
A 8-bit page pointer "DP" used for direct addressing of the
memory;
An "CC" status register on 8 bits;
Le compteur de programme sur 16 bits "PC" pointant toujours sur
the address of the next instruction that the microprocessor must
execute.

03/06/2021 26
 The 6809 microprocessor
Presentation of the 6809 processor:
There are two versions of this processor, the 6809 and the 6809E. Their pinout
differs as well as their signals but their instruction set is identical.
The Le6809 has an internal clock.
The Le6809E requires an external clock.
The 6809 has 9 addressing modes:
Inherent addressing
Immediate addressing
The direct addressing
Extended addressing
Extended indirect addressing
The short relative address
Long relative addressing
Indexed addressing
Indirect indexed addressing

03/06/2021 27
 The 6809 microprocessor
Organization of the 6809 processor

The microprocessor, manufactured in N Channel MOS technology, contains 40

He has 3 independent buses:

03/06/2021 28
 The 6809 microprocessor
External organization of the 6809 processor:
The corresponding circuit has 40 pins in the form of a casing.
DIL (Dual Inline Package)

03/06/2021 29
 The 6809 microprocessor
Organization of the 6809 processor:
two versions: 6809 and 6809E.
The 6809 is timed by an internal clock (f=1 MHz, 1.5 MHz and

The 6809E is driven by an external clock. It is suitable for

multiprocessor applications.

03/06/2021 30
 The 6809 microprocessor
Control bus:
Read/Write line (R/W):

Bus status lines: BA (Bus Available) – BS (Bus State)

Information that allows you to know the status of the microprocessor at all times.
moment. Four possible combinations:

03/06/2021 31
 The 6809 microprocessor
Control bus:
Bus status lines: BA (Bus Available) - BS (Bus State)
1st case: The microprocessor is operating normally, it manages the
address and data bus.

2ème cas :Le microprocesseur est en phase de reconnaissance

interruption for two cycles. This state corresponds to the research
interrupt vectors: Reset, NMI, IRQ, SW1, 2 and 3.

3rd case: This signal appears when the microprocessor encounters

The external synchronization instruction (low level on SYNC). It waits
So this synchronization on one of the interrupt lines. The buses are
in high impedance during this time.

Last case: Corresponds to the microprocessor stop (low level on

HALT). The microprocessor leaves the management of data buses and
addresses to an auxiliary circuit (DMA controller). The buses are high
impedance. The BA line at a high level indicates that the buses are in
high impedance.

03/06/2021 32
 The 6809 microprocessor
Control bus:
Line Halt: (Microprocessor Stop)
Input line for the µP, when it is at a high level, the
6809 works normally. But if by an electric signal,
we set it to '0' and as long as we keep it there, we stop the
operation of the microprocessor. The latter completes
the current instruction then sets: BA (BusAvailable) and
BS (Bus Status) set to 1.

The operation resumes as soon as the Halt pin is at 1 and without

are invalidated: Reset and NMI are valid but their

The processing will only take place upon the release of the 6809. The clocks
are not affected.

03/06/2021 33
 The 6809 microprocessor
Control bus:
RESET line: (complete initialization of the microprocessor)

It is an entry that allows initializing the mP.

•SiReset = 0
the current instruction is stopped,
the page register is reset to zero,
the IRQ and FIRQ interrupts are masked and
The unmasked NMI interrupt is disabled.

03/06/2021 34
 The 6809 microprocessor
Control bus:
Interrupt lines: (NMI, IRQ, FIRQ)
NMI: (Non Maskable Interrupt)

It is a non-maskable interrupt input line, active at

low level. It allows to execute an interrupt routine

This line is invalidated by Reset. The content of the entirety of

the 6809 registers are saved in the system stack.

03/06/2021 35
 The 6809 microprocessor
Control bus:
Interrupt lines: (NMI, IRQ, FIRQ)
IRQ: (Interrupt ReQuest)
It is a line to enter requests for maskable interruptions,
active in the low state. It works like on the 6802. It has its
vector in $FFF8-$FFF9.

It is conditioned by bit 1 of the CCR register and all the registers.

are saved. The execution of the routine can be interrupted
by FIRQ or NMI.

FIRQ: (Fast Interrupt ReQuest)

It is an input line. It is masked or not depending on the state of the
bit F of the CCR register. The registers of the 6809 are only saved
partially.

03/06/2021 36
 The 6809 microprocessor
Control bus:
ClockXtal and EXtal input lines:
These are two input connections for the internal oscillator to an external quartz of 4, 6 or

The EXTAL pin can be used as a TTL level input for a clock.
external by grounding XTAL.
Clock output lines E and Q:
E: It is a clock output for bus timing (synchronization with the

Q: It is a clock output in quadrature with 'E'. The addresses on the bus will be

MRDY : (Memory Ready)

it is a command input that allows for the extension of the duration of the signal "E" and
This is to use the slow memories.
DMA/BREQ: (Direct Memory Address/Bus Request)
sThis line is at a low level, which allows the bus to be freed up for access.

03/06/2021 37
 The 6809 microprocessor
Internal architecture:
The 6809 microprocessor is composed of nine internal registers:
Accumulators A and B: are two registers of size 8 bits.
the concatenation of registers A and B gives birth to
Accumulator D. The accumulator A representing the high bits and B
low weights.
The DP (Direct Page) register is an 8-bit register. It forms the

The index registers X and Y: They are 16 bits in size. Other

they allow addressing the entire memory space with additionally the
ability to be pre-decremented or post-decremented (which facilitates
the processing of variables in tables).

03/06/2021 38
 The 6809 microprocessor
Internal architecture:

03/06/2021 39
 The 6809 microprocessor
Internal architecture:

03/06/2021 40
 The 6809 microprocessor
Internal architecture:
The program counter (Program Counter - PC) is a
16-bit register. It can point to all memory locations. It
contains the address of the next instruction to be executed.

The stack pointers U and S: These are two 16-bit registers that
both operate identically. They function in 'LIFO' mode.
These two registers can occasionally serve as an index register.
with all the possibilities of X and Y. The register S (System) is
used by the 6809 for all backup operations in case

The U (User) register is fully reserved for the user.

03/06/2021
 The 6809 microprocessor
Internal architecture:
The State Register (ConditionRegister Code - CCR):
This register defines the state of the µP at all times resulting from a

for jump or conditional branching instructions.

03/06/2021 42
 The 6809 microprocessor
Internal architecture:
The state register (ConditionRegister Code - CCR):
Carry: This bit takes the value 1 each time the

we have a retention. This retention can be considered as

the 9th bit for accumulators A and B.
Note: "C" will remain zero in other cases!
Example 1:
ADCA #$2C

Example 2:
SUBA #$22

03/06/2021 43
 The 6809 microprocessor
Internal architecture:
The state register (ConditionRegister Code - CCR):
"V" Overflow: It's an overflow bit. It's set to 1 if
the result (in 2's complement) of an arithmetic operation
overflows, that is to say exceeds the byte. Otherwise, it remains at 0.

Example 1:
LDA #$12 loading the accumulator A with the value $12

Example 2:
ADD #$A0 adds the content of register A and the value
$A0

03/06/2021 44
 The 6809 microprocessor
Internal architecture:
The state register (ConditionRegister Code - CCR):
"Z" Zero: It is a bit that simply indicates whether the result
an instruction or operation is null. In this case, it is

Example 1:
AND #$C4; Logical AND between the content of Acc A ($3B) and

Example 2:
AND #$C3; logical ET between the content of Acc A ($3B) and
the value C3, the result in A.

03/06/2021 45
 The 6809 microprocessor
Internal architecture:
The state register (Condition Register Code - CCR):
"N" Negative: It is a sign indicator. It is positioned
if the result of an instruction or an operation is negative.
Otherwise, it remains at 0. It contains exactly the most significant bit of
the byte resulting from the previous operation. A negative result
for a two's complement operation, set N to 1.

Example:
LDA #$C1 loading A with the value $C1

03/06/2021 46
 The 6809 microprocessor
Internal architecture:
The state register (ConditionRegister Code - CCR):

Half Carry: It is a half-holding indicator. When

During an operation, the µP processes the bytes bit by bit. If when processing the
4th bit of the byte, it must carry over to bit 4. It has
the obligation to notify us by setting H to 1.

"I" Interrupt mask: It is an interruption indicator. It is

initiative of the microprocessor. This is the mask for the socket.

03/06/2021 47
The 6809 microprocessor
Internal architecture:
The state register (ConditionRegister Code - CCR):

It is at zero after a reset and in this case, FIRQ is valid. If

the user forces it to 0, FIRQ is processed.

The bit informs us about the number of

03/06/2021 48
 The 6809 microprocessor
Addressing modes:

Definition:
The term 'addressing mode' refers to the way in which the data is

an architecture governs the way instructions in language

machines identify their operands.
A addressing mode specifies how the address is calculated.

in the machine.

03/06/2021 49
 The 6809 microprocessor
The addressing modes:
The mP6809 has 59 'basic' instructions.
Combined with the different addressing modes, they offer

The size of the instruction is variable. An instruction

behaves from 1 to 5 bytes. Generally, the first byte
indicate the action to be taken, the following specify the
operands or on some registers this action will act.
Instruction:

(1 or 2 octets) (1 or 2 octets)

03/06/2021 50
 The 6809 microprocessor
The addressing modes:

The 6809 has 9 addressing modes:

Inherent addressing
Immediate addressing
Direct addressing
Extended addressing
Extended indirect addressing
Short relative addressing
Long relative addressing
Indexed addressing
Indirect indexed addressing

03/06/2021 51
 The 6809 microprocessor
Addressing modes:
Inherent addressing:

Inherent addressing is used by instructions that act

There are two types of inherent addressing modes:

Simple inherent addressing
Inherent parameterized addressing

03/06/2021 52
 The 6809 microprocessor
The addressing modes:
Simple inherent addressing:
The operation code contains all the information necessary for execution.

example:

INCB, incrementing accumulator B by 1.

03/06/2021 53
 The 6809 microprocessor
The addressing modes:
The inherent parameterized addressing:
The instruction includes an additional byte to specify the
operands involved in the instruction. the presence of this byte
supplementary is essential for instructions of the type:
Exchange and transfer of records.
Access instructions for the pile.
Waiting for interruption.
exchange and transfer of register: the first byte determines the code
pure operational, the second the source and destination registers.
TFR U,S transfer from U to S
Access instruction to the stacks: the first byte determines the operation code
pure, the post-byte, the registers involved in accessing the stack.
PSHS A, B, X save in stack of A, B, X
Waiting for an interrupt: the first byte is associated with the instruction
CWAY,le second sert à masquer ou à valider les interruptions.
CWAY#$FF waiting for NMI interruption (masked IRQ and FIRQ)

03/06/2021 54
 The 6809 microprocessor
The addressing modes:
Immediate addressing:
In this addressing mode, the operation code is followed by a
value that is the operand of the instruction (on one or two
octets). This allows loading the internal registers of the µP with
the value of the operand.
Example: LDA #$80, Loading A with the value
hexadecimal 80.

03/06/2021 55
 The 6809 microprocessor
The addressing modes:
Immediate addressing:
There are three types of instructions in this addressing mode:
Instruction on two bytes:
The first byte contains the opcode, the second the 8-bit constant.
This type of instruction is reserved for working on 8-bit registers.
Load Accumulator with #$43 load the value $43 into accumulator A.

Instruction on three bytes:

The first byte contains the opcode, the second the constant in 16 bits. This
This type of instruction is reserved for working with 16-bit registers.
ADD #$1981 addition of the content of accumulator D and $1981
Instruction on four bytes:
The operating code uses two memory bytes, the constants as well.
LDY #$1623 load index Y with the hexadecimal value $1623

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 The 6809 microprocessor
The addressing modes:
Direct addressing:
This addressing mode has the advantage of requiring only 2
octets to access data located across the entire
the memory space of the µP. The first byte defines the code
operational, the second represents the 8 least significant bits of
the effective address whose 8 most significant bits are located in
the page register of the µP (DPR).
It is therefore enough to initialize the page register (DPR) in order to
work in direct addressing on 256 bytes of the selected page;
Beyond that, it is necessary to access the DPR again.
Upon power-up, the page register is set to zero. We
has access to the 256 bytes of page 0.

03/06/2021 57
 The 6809 microprocessor
The addressing modes:
Direct addressing:
Example:
If the page register is $D3:
the LDA instruction <$42 will load
the accumulator 'A' by the content of
the memory cell $ D342 which is $7F.

Note:
the direct addressing will be specified by the
the sign " < " placed before the operand,
in assembly language syntax.

03/06/2021 58
The 6809 microprocessor
The addressing modes:
Direct addressing:
There are two types of instructions in this addressing mode:
Instruction on two bytes:
The first byte defines the opcode, the second the low weights of
the effective address
Example:
LDA $37ouLDA <$37 loading accumulator A with the content
of $D437 (DPR =$D4).
Instruction on three bytes:
The operational code is defined by the first two bytes. The third byte
Specify the reliable points of the effective address. The first octet is only
necessary for the instructions that operate on the stack pointer S, the register
of index Y and on the comparison instructions CMP operating on 16 bits
LDY $17 or LDY <$17 loading register Y with the content of $
2317 and $2318

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The 6809 microprocessor
The addressing modes:
Extended addressing:
The extended absolute addressing allows to find
data in memory.
The operation code (8 bits) is followed by 2 bytes.
constituting the effective address of the operand.
The symbol " > " is an assembler directive that
force extended addressing.
There are two types of instructions in this mode
of addressing:
Instructions on three bytes.
Instructions on four bytes.

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The 6809 microprocessor
The addressing modes:
Extended addressing:

oInstructions on three octets:

The first byte (opcode) is followed by address 16

bits specifying the location of the operand (8 or 16 bits).

Example:
LDA $21C0 or LDA >$21C0 loading of
the accumulator A with the content of address $21C0.
In this case, the operand is the accumulator A.

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The 6809 microprocessor
Addressing modes:
Extended addressing:

oInstructions on four bytes:

The operation code is defined by the first two bytes. The

The 3rd and 4th octets constitute the effective address. The
the first byte is only necessary for the instructions
who operate on the pointers S and Y and on the instructions of
comparison CMPU, CMPD.
Example:
LDY $347B or LDY > $347B Loading the Y register
with the content of $347B.

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The 6809 microprocessor
Addressing modes:
Extended Indirect Addressing:

This addressing mode is identical to the addressing mode

extended but it also has an indirection.
One accesses an effective address by "transiting" through a
intermediate address.
Extended indirect addressing is coded with an operation code.
identical to that of the indexed addressing followed by a post-byte.
The assembly notation "[ ]" enforces extended addressing.
indirect.
There are two types of instructions in this addressing mode:
Instruction on four bytes.
oInstruction in five bytes.

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The 6809 microprocessor
The addressing modes:
Extended indirect addressing:
Instruction on four bytes:

The first two bytes determine the operation code of

indexed addressing followed by a determining post-byte
the indirection. The 3rd and 4th octets represent the address of
transit.

Example:
LDA [$2000] charging of accumulator A with the
content whose address is located at $2000 and $2001.

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The 6809 microprocessor
Addressing Modes:
Extended indirect addressing:
Instruction on five bytes:

For certain instructions, it is necessary to add a pre-

octet. This is necessary for instructions operating on the
pointers S and Y ($10) and for the comparison instructions
CMPU and CMPD ($11).
The rest of the coding is identical to that of the instructions
over four bytes.

Example:
LDY [$2000] loading the Y index register with the
content whose address is located at $2000 and $2001.

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The 6809 microprocessor
The addressing modes:
Short relative addressing:
This addressing mode is reserved for instructions of
connection
The branch instruction operating in short relative addressing does
call for a format of only two bytes:
The first byte determines the operation code which specifies the
connection type at the same time as the corresponding test.
The second octet is the displacement value that can be
positive or negative.
In short relative addressing mode, the displacement is encoded on a
octet, we can move back by 128 octets and 127 octets
forward concerning the value of the ordinal counter (PC) at the end
of processing the connection instruction.

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The 6809 microprocessor
Addressing modes:
Long relative addressing:
Identical to the short relative addressing mode, it is always reserved
to the connections.
The essential difference between short relative addressing and relative addressing
how long the displacement is coded on 16 bits in the second case.
Instructions are encoded on four bytes, the first two
déterminent le code opération, les 3éme et 4éme octets donnent la
signed displacement value.
One can move forward by +32767 ($7FFF) bytes and
-32768($8000) backward, in relation to the value of the counter
ordinal (PC) at the end of the branch instruction processing.
At the machine code level, a pre-byte of value is added.
constant ($10) in the operation code to indicate addressing
relatively long.

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The 6809 microprocessor
The addressing modes:
Indexed addressing:
principle:
The instruction specifies a base (index) plus an offset relative to it.
base.
Effective address = base + displacement

For the 6809, the base can be:

One of the two index registers (X and Y).
One of the two stack pointers (U and S).
The program counter (a special case of relative addressing)
For the movement, it can be:
Null.
Encoded on 5, 8, or 16 bits.
Variable (in the case of using an accumulator A, B, or D)
Indexed addressing offers possibilities of auto-increment and auto-
decrementing by 1 or 2.

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The 6809 microprocessor
Addressing modes:
Indexed addressing:
All these options will be selected by the post-octet that follows the code.
operative.

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The 6809 microprocessor
Addressing modes:
Indexed addressing:
Remarks:
The bits 5 and 6 of the post-byte allow to define the base.

Bit 7 defines the role of bit 4:

b7 = 0 b4 = sign bit
b7 = 1 b4 = choice of direct mode (b4 = 0) or indirect (b4 = 1)
If b4 = 1, the mode can operate directly or indirectly.
Bits 0 to 3 define the addressing mode field.

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Addressing modes:
Indexed addressing: No displacement.
In this mode, the selected pointer register contains the address
effective data to be used by the instruction.
There are two types of instruction:
Instruction on two bytes: the opcode is followed by
post-octet specifying the options chosen for the instruction in
course.
Example:
LDA ,X loading of accumulator A with the value of which
The address is the content in X.
Instruction on three bytes: for certain registers of
microprocessor, it is necessary to add a pre-byte to both
operational octets.
Example:
Load the Y register with the value of the X register Loading the Y index with the value whose address
is the content of X.

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Addressing modes:
Indexed addressing: auto-increment/decrement.

In this mode, we can obtain pre-increment of 1 or 2.

and post-increment by 1 or 2.
Mode facilitating the management of a table.

The selected pointer register contains the effective address of the

data used by the instruction.
The symbols " + ", " ++ ", " - " and " -- " placed before or after
the base defines the type Auto-increment / auto-
decrement

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Addressing modes:
Indexed addressing: auto-increment/decrement.

oInstruction on two bytes:

Example:
loading A with the value at the address
Load Accumulator, X plus
the content of X, post-incrementing X by 1.

oInstruction on three bytes:

Example:
LDY , - - X loading Y with the value whose address
The base is the content of X–2.

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Addressing modes:
Indexed addressing: Constant displacement.

In this addressing mode, the effective address of the operand is the

sum of the displacement (in two's complement) and the content of
register constituting the basis.
The base register retains its value without any modification.
There are three forms of indexed addressing with constant displacement,
according to the value of this constant.
Movement on ±4 bits.
Movement on ±7 bits.
Displacement on ±15 bits.

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Addressing modes:
Indexed addressing: Constant displacement.
Movement on ±4 bits:

This coded displacement on five bits (in two's complement) presents

the advantage of being contained in the post-octet of indexing. What
allows for memory space saving and faster execution of
this instruction.
The bits 0 to 4 of the post-byte determine the displacement value.
who can be -16 in the back (1 0000) and +15 in the front
(0 1111).
The bit 7 constantly at zero initializes bit 4 as a bit of
sign.

Example:
ADDB - 3, Y addition of the content of memory address Y -3 to
content of the accumulator B, the result is in the accumulator B.

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Addressing modes:
Indexed addressing: Constant displacement.
Movement on ±7 bits:

This displacement coded on eight bits (in two's complement) is

content in a single byte placed after the opcode
strictly speaking and the post-byte indexing.
The possible movements are therefore between -128 and
+127 bytes.

Example:
loading the Y pointer with the content
Load the value from address $65 into register U
memory whose base address is the content of U + $65.

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The addressing modes:
Adressage indexé: Déplacement constant.
Displacement on ±15 bits:

This shift coded on 16 bits (in two's complement) is

content in two bytes placed after those of
the instruction (operational code + post-octet of indexing).
The possible movements are therefore between -32768
and + 32767 bytes

Example:
Load Accumulator with the value at memory address $2000 plus the content of register X. charging of the accumulator A with the
content memory address X + $2000.

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Addressing modes:
Indexed addressing: Accumulator displacement.

This addressing mode is similar to indexed addressing.

constant movement except for the movement that
is no longer coded on specific bytes but contained in
the accumulators A, B or D of the microprocessor.
The effective address is therefore the sum of the pointer register and
accumulators specified in the instruction mnemonic.
The content of the pointer and user registers (A, B or D)
remains unchanged after the addition.
Each instruction is coded on two bytes, the post-byte
specify the name of the pointer and that of the accumulator
movement.

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The 6809 microprocessor
The addressing modes:
Indexed addressing: Accumulator displacement.
Shift on ±7 bits accumulator A or B.

Example:
Load A, X loading accumulator A with the content
memory whose address is X + B.

Displacement on ±15 bits accumulator A or B.

Example:
LEAY D, X loading the Y index of the effective address
given by the sum D + X.

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Addressing modes:
Indexed addressing: Base = program counter.

This addressing mode uses the program counter PC.

as an indexing base.

The use of PC as a base imposes restrictions on the

types of movements, only movements on 8 or 16
bits (in two's complement) can be used.

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The addressing modes:
Indexed addressing: Base = program counter.

Constant shift over ±7 bits:

The effective address is equal to the current program counter
plus a movement coded on 8 bits.
The instruction is encoded on 3 bytes, two bytes are reserved for
the instruction (operational code + post-byte), the last byte
contains the displacement.
Example:
LDA $F0, PC charging of accumulator A with the
memory content at the address which is the value of PC + $F0.

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The addressing modes:
Indexed addressing: Base = program counter.

Constant displacement over ±15 bits:

The effective address is equal to the current program counter.

plus a coded displacement over two bytes.
This addressing mode has the advantage of allowing for
movements across the entire memory space of the microprocessor.

Example:
ADD $9000, PC addition of the memory content whose address
is the current value of PC +$9000 and of the accumulator A, the
result is in A.

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Addressing modes:
Adressage indexé: Base = compteur programme.

Localized etiquette:
The assembly syntax does not directly use a
movement but a localized label located at ±128 of
the following instruction (move on 8 bits) or anywhere
on the memory space of the microprocessor ( displacement on 16
bits) .
The effective address is equal to the program counter.
current plus a displacement encoded on 8 or 16 bits. The instruction
is encoded on three or four bytes.
the assembly syntax contains the mnemonic of the instruction,
the name of the localized label plus the base. The assembler
calculate the value of displacement based on the position of
the label.

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The 6809 microprocessor
The addressing modes:
Indexed addressing: Base = program counter.

Localized Etiquette:

Example:

LEAX ETIQ, PCR loading the index register X with

the actual address that is given by the position of the label by
report on the current program counter.

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Addressing modes:
Indirect indexed addressing:

This indexed addressing mode has the advantage of being able to

work indirectly. In this case, we access the address
effective by passing through an intermediate address.
Effective address = memory content whose base address is
the sum of the index + displacement.
All indexed addressing modes can work in
indirection except for auto-increment/auto-
decrement and the constant movement mode coded on ±5
bits.

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the instruction set of the 6809

In the instruction set of the 6809, we find the different

instruction groups available on a computer.

Instructions for data processing.

Data transfer instructions.
Test and connection instructions.
Instructions operating on pointers.
Instructions for handling interruptions.

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the instruction set of the 6809
data processing instructions

Data processing instructions are divided into

four categories:

Arithmetic instructions.
The rotation and shifting instructions.
The logical instructions.
The increment instructions/
decrementing, resetting and
supplementation.

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the instruction set of the 6809
data processing instructions

The arithmetic instructions:

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The 6809 microprocessor
the instruction set of the 6809
data processing instructions

The rotation and shift instructions:

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 The 6809 microprocessor
the instruction set of the 6809
processing instructions of
data
The logical instructions:

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the instruction set of the 6809
data processing instructions
The increment/decrement instructions,
reset, complementation:

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the instruction set of the 6809
data transfer instructions
Data transfer instructions can be classified into
three categories:

Instructions operating on the internal registers and the

memory.
Transfer instructions operating on pointers.
Instructions operating on internal registers of the
µP.

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the instruction set of the 6809
data transfer instructions
Instructions operating on internal registers and memory:

Transfer instructions operating on pointers:

Instructions operating on the internal registers of the microprocessor:

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the instruction set of the 6809
test and connection instructions
These instructions can be divided into three categories
distinct:

The test and comparison instructions.

Testing and connection instructions.
Jump and branch instructions.

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 The 6809 microprocessor
the instruction set of the 6809
test and connection instructions
The test and comparison instructions:

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 The 6809 microprocessor
the instruction set of the 6809
test and connection instructions
The test and wiring instructions:

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 The 6809 microprocessor
the instruction set of the 6809
testing and connection instructions
The jump and branch instructions:

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the instruction set of the 6809
instruction operating on pointers
The 6809 has a single instruction of this type that offers
to the user several possibilities. The processor calculates
an effective address based on the addressing mode
specific (always indexed) then load this value into
the pointer (U,Y,S or U).

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the instruction set of the 6809
instruction operating on interrupts
These are the instructions related to the
interruptions of the 6809. There are three on the 6809.
software interruptions and three hardware interruptions.

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The interruptions
Generalities

The microprocessor in its environment is designed to process some.

real-time information. The application is linked to the world
outdoors, through the frequent exchange of signals at non
foreseen.

In response to the demands of the external environment, the

the microprocessor is required to change state based on
the relative priorities of the ongoing operation and those that are
requested. It interrupts or does not interrupt the normal course of
program according to an external request.
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The interruptions
Definition
An interrupt is a signal triggered by an internal event.
external event, causing the interruption of a running program
at the end of the current operation, in favor of a more
priority called interruption program. Then, the program
interrupted resumes execution at the place where it had been
interrupted.

There are two types of interrupts:

Material interruptions.
Software interruptions.

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The Interrupts of the 6809

The 6809 microprocessor has four lines for this purpose, called
material interruption entries that are prioritized.

oRESET Microprocessor reset.

oNMI No Maskable Interrupt.
oFIRQ Fast Interrupt Request.
oIRQ Interrupt Request.

These entries are active for a 'low' level.

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The interrupts of the 6809

Aside from hardware interrupt requests, there are other ones.

causes of program interruption. These are the interruptions
"soft" software.

They translate into instructions in full that we place

in the programs. So, they represent events
deterministic

it lists three software interruptions:

oSWI Software Interrupt
oSWI2 Software Interrupt No. 2
oSWI3 Software Interrupt No. 3

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The interruptions of the 6809

the two forms of interruptions present similarities:

the main program is interrupted after execution of

the ongoing instruction.
The microprocessor must save all or part of
context of the microprocessor in the stack.
The microprocessor executes a privileged sequence, reflection
of the interrupt treatment type.

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The interrupts of the 6809

The complete means of handling interruption of

microprocessor brings forth the concept of priorities.
Generally, this priority is related to the hardware structure.
even from the microprocessor.

During an interruption, the microprocessor positions itself

automatically to a memory address whose content
represents the address of the interrupt handling program
appropriate. These addresses correspond to the interrupt vectors
which are all located at the top of the memory addressable space by the
microprocessor.

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The interrupts of the 6809

6809 Interrupt Vectors:

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The hardware interrupts of the 6809

The 6809 microprocessor has three hardware interrupts.

executable during the execution of an application plus one
initialization sequence (RESET) that is treated like the interrupt
the highest priority of the system.
A low level on the RESET input allows for a complete reset
of the microprocessor:
The instruction in progress is stopped.
the page register is positioned at 0.
Hardware interrupts are masked. Signals on
IRQ and FIRQ have no influence.
The NMI interruption is disabled.

This microprocessor initialization sequence lasts about a

ten cycles of clocks and of course there is no access to the batteries.
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The hardware interrupts of the 6809

NMI (Non-Maskable Interrupt)

A descending front on this entry leads to a sequence

non-masquerable interruption. This interruption is the highest priority.
of all those of the microprocessor. It cannot be masked by
program.

The treatment sequence of NMIdure takes about twenty cycles.

processor.

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The hardware interrupts of the 6809

Non-Maskable Interrupt (NMI)

Different phases of work of the microprocessor before execution
NMI interrupt handling program:

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The hardware interrupts of the 6809

NMI (Non-Maskable Interrupt)

Different phases of the microprocessor's work before execution of
NMI interrupt handling program:

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The hardware interrupts of the 6809

The FIRQ: (Fast Interrupt Request)

In some cases, the right microprocessor handles interruptions very

quickly this creates a problem with traditional interruptions
where the total context backup of the microprocessor takes a certain amount of time (1
clock cycles per byte saved.
The quick interrupt only saves the program counter.
(PC) and the register condition codes (CCR), which makes 3 bytes instead of
12 hence the time savings of 9 clock cycles.
This FIRQ interrupt is maskable, through bit 6 of
CCR. It is more priority than the IRQ interruption.
The processing sequence of this interrupt lasts about 11 cycles.
of the clock.

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The hardware interrupts of the 6809

The FIRQ: (Fast Interrupt Request)

Different phases of the microprocessor's work before execution of
FIRQ interrupt handling program:

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The hardware interrupts of the 6809

The IRQ interruption: (Interrupt Request)

This interrupt is the least priority of the hardware interrupts.

the 6809.

It can be masked through bit I of the code register.

conditions (CCR).

The IRQ interrupt processing sequence lasts about 20 cycles.

of the clock. This interruption is the most commonly used of the interruptions.
material.

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The hardware interrupts of the 6809

The IRQ (Interrupt Request) interrupt

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The hardware interrupts of the 6809

The IRQ (Interrupt Request) interruption

Different working phases of the microprocessor before execution
FIRQ interrupt handling program:

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The hardware interrupts of the 6809

The IRQ interruption: (Interrupt Request)

Different working phases of the microprocessor before execution
FIRQ interrupt handling program:

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The software interrupts of the 6809

The SWI interruption: (Software Request)

The 6809 microprocessor has three software interrupts (SWI,

SWI2, SWI3)

The SWI instruction in a program imposes the stop of execution of

this one. The microprocessor carries out a certain number of sequences
internal then execute an appropriate processing program for
the SWI interruption.

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The software interrupts of the 6809

The SWI interruption: (Software Request)

Different phases of the microprocessor's work before execution
SWI interrupt handling program:

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 The 6809 microprocessor
The interfaces of the 6809

Generalities:
Interfaces ensure communication (unidirectional / bidirectional)
between the microprocessor and the external environment
(devices).

Two main families of interfaces associated with the same central unit:
Passive interfaces.
Active interfaces.
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The interfaces of the 6809

Passive interfaces:
Their main characteristic lies in the fact that it is the
application microprocessor that has the task of management of
transfer.

Advantages:
Ease of implementation.
Ease of use.
Disadvantages:
The processor time used for managing exchanges with the
peripheral.

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The interfaces of the 6809

Active interfaces:
the interface itself manages exchanges with the device (thanks to a
slave processor to the central processor.

Advantages:
Management autonomy of exchanges.

Disadvantage:
The hardware architecture of the application is more complex.

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The interfaces of the 6809
According to the process of information transmission between the
microprocessor and the peripheral(s), we distinguish:

Parallel interfaces.
Serial interfaces.

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 The 6809 microprocessor
PIA 6821
Parallel input/output interface: PIA 6821

The PIA 6821 (Peripheral Interface Adapter) is the coupler of

device that allows for parallel connection between the
6809 microprocessor and its peripherals.
The PIA communicates with the microprocessor through the
data bus (8 bits), address (5 lines) and control.
The dialogues with the peripheral are ensured by two 8-bit buses.
bidirectional.

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PIA 6821
Parallel Input/Output Interface: PIA 6821

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Internal and external organization of the PIA 6821

Internal organization:

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Internal and external organization of the PIA 6821

External organization:
The PIA is presented in the form of a 40-pin mono DIL package.
tension (0.5V).

Connections with the microprocessor:

Data bus (D0 to D7)
Bus of addresses:
CS0, CS1, CS2 (Chip Select Line).
RS0, RS1 (register Select Line).
Control bus:
E: activation signal for exchanges.
RESET: initialization of the PIA.
R/W: read and write.
IRQA, IRQB: related to IRQ, FIRQ or NMI.

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Internal and external organization of the PIA 6821

External organization:
Liaisons with the periphery:

Transfer lines PA0-PA7 and PB0-PB7: these 8 pins

allow to transmit or receive an 8-bit word
according to the DDR schedule.
Ex : DDRA3= 0 PA3 is in input.
DDRA3= 1 PA3 is out.

Lignes de dialogue CA1, CA2, CB1 et CB2.

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Programming of the PIA 6821

The control registers (CRA and CRB):

8-bit registers that contain the operating parameters:

This register concerns the programming of the special pins CA1, CA2 for the
portAet CB1, CB2 for the port to B.
b7 and b6: The status indicators accessible for reading, it's the PIA that will provide
day these bits according to the activity on the pins Cx1 and Cx2.
b5 to b0: The operating parameters accessible for reading and writing.
129
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The 6809 microprocessor
Programming of the PIA 6821

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 The 6809 microprocessor
Programming of the PIA 6821

Programme d’initialisation du PIA:

(port A as input, port B as output).

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Programming of the PIA 6821

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Programming of the PIA 6821
8000 DDRA and ORA
8001 CRA
8002 DDRB and ORB
8003 CRB
[Link] #$00 Access to DDRB Write a value
[Link]$8003 or CLR $8003 in port B
[Link] #$FF Port B output
[Link]$8002
[Link] #$04 Access to ORB
[Link]$8003
[Link] #$E0 1110 0000 on PortB
[Link]$8002 03/06/2021 133
 The 6809 microprocessor
Programming of the PIA 6821

DDRA EQU $8000

ORA EQU $8000
CRA EQU $8001
Load Accumulator with $00
Write a value
STA CRA in port A
LDA #$FF
STA DDRA
Load accumulator with #$04

STA CRA
LDB #$80

STB NOW
END
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 The 6809 microprocessor
Programming the PIA 6821

DDRA EQU $8000

ORA EQU $8000 Read a value from
CRA EQU $8001
ORG $FC00
port A and the
CLRA
STACRA
to transmit to
STADDRA
Load Accumulator with #$04
the address 0100
STACRA
LDA NOW
STA$0100
END

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 The 6809 microprocessor
Programming the PIA 6821
PIACRA EQU $8001
PIACRB EQU $8003
EQU STONE $8000
PIADRB EQU $8002
PIAORA EQU $8000
PIAORB EQU $8002 Copy a value
CLRA from port A and
STAPIACRA
STAPIACRB transmit to the port
STAPIADRA
COMA B
STAPIADRB
STAPIACRA
STAPIACRB
AGAIN:
LDA PIAORA
STAPIAORB
GOOD AGAIN
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 The 6809 microprocessor
Programming the PIA 6821

Exercises

◦ 1) Create a binary counter in port B

◦ 2) Shift a lit bit to the left
right.
◦ 3) Shift a lit bit to the left inversely
to the left.

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The 6809 microprocessor

Thank you for your

attention
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