MODULE 2

Multiplexers and Demultiplexers

One common communication channel

Sender end
Receiver end
Many to one
One to Many
MUX
A MUX (Multiplexer) is a combinational circuit that has 2n communication lines and a single
output line.

Basic Function: Combines multiple input signals into a single output signal.

Input/Output Configuration: Multiple inputs, one output.

Select Lines: Used to select which input will be transmitted to the output.
Typical Applications: Data aggregation, signal multiplexing in telecommunications, and data
compression.

Signal Flow: Many-to-One

Depending on the binary values of A and B, one
source is selected.
For example, if selection lines are B=1 and A=0,
then the Satellite input (D2) will be connected to
the output.
Real-Life Analogy

Think of a Multiplexer like a TV remote input selector:

● You press a button to choose whether the TV shows HDMI1, HDMI2, USB, or AV input.

● Only one input is displayed at a time, but multiple devices are connected.

Similarly, the MUX selects one input signal and sends it to a single output device.
 Implementing Function using MUX

Using a 4×1 Multiplexer:

● Selection lines: S₁ = A, S₀ = B
001 010 101 111
● Inputs: I₀, I₁, I₂, I₃ depend on C

A B
Types of Multiplexers (MUX)
A multiplexer is represented as n:1,

where n = number of inputs and 1 = single output.

Formula Reminder:

● Inputs = 2n Type of Number of Number of Number of Selection Lines

● Selection lines = n MUX Inputs Outputs
● Output = always 1
2:1 2 1 1

4:1 4 1 2

8:1 8 1 3

16:1 16 1 4
DEMUX (Demultiplexer)
A DEMUX takes one input and sends it to one of many outputs.
Which output is chosen depends on the selection lines.

It is the reverse operation of a multiplexer (MUX).

Also known as a data distributor, since it takes a single input and distributes it to one of many outputs based on selection lines.

Basic Function: Splits a single input signal into multiple output signals.

Input/Output Configuration: One input, multiple outputs.

Selection line:Used to select which output will receive the input signal.

Signal Flow: One-to-Many

Typical Applications:Data distribution, signal demultiplexing in communication systems, and serial-to-parallel conversion.
Simple Analogy

Think of DEMUX like a post office clerk:

● There is one letter (input).

● The clerk looks at the address (selection line).

● Then delivers the letter to the correct house (output line).

DEMUX = Post office clerk

Input signal = Letter

Selection line = Address The DEMUX has selection lines that decide
which output line will carry the input.
Output line = House
Types of DEMUX
A demultiplexer is represented as 1:n,

where 1 = single input and n = number of outputs.

Formula Reminder:

Input = always 1 Type of Input Outputs Selection

Outputs = 2ⁿ DEMUX Lines
Selection lines = n
1:2 1 2 1

1:4 1 4 2

1:8 1 8 3

1:16 1 16 4
 Which output is chosen depends on the
selector lines (A, B).

If the selector lines are 00, the computer’s

data goes to the B/W Laser Printer.

If the selector lines are 01, the data is sent to

the Fax Machine.

The computer is the single If the selector lines are 10, the data is sent to
input (data source). the Color Inkjet Printer.

If the selector lines are 11, the data is sent to

the Pen Plotter.
ENCODER
An encoder is a combinational circuit that performs the reverse operation of a
decoder.

An encoder is a device that converts information from one format into another. In
digital electronics, encoders are logic circuits that convert a set of input signals into a
coded output, often a binary code.

It is a multiple-input and multiple-output device.

Types of Encoders

There are different types of Encoders which are mentioned below.

● 4 to 2 Encoder
● Octal to Binary Encoder (8 to 3 Encoder)
● Decimal to BCD Encoder
● Priority Encoder
Encoder
Purpose: Converts 2ⁿ input lines into n output lines (binary form).

Main Use:

○ To reduce multiple inputs into a smaller number of bits for efficient data representation.

○ Used in digital circuits to convert information (like keys pressed on a keyboard) into a binary code.

○ Saves hardware wiring by encoding large input sets into compact binary outputs.

Example: A Decimal-to-Binary Encoder converts 10 decimal inputs into a 4-bit binary output.
Decoder
A decoder is a combinational logic circuit that converts coded binary input data
into a set of unique output signals. Essentially, it translates binary information from
a smaller number of input lines into a larger number of output lines.

Depending on the input (00, 01, 10, or 11),

A 2-bit decoder has 2 inputs and 4 outputs (2² = 4). only one output line will turn ON, and all
A 4-bit decoder has 4 inputs and 16 outputs (2⁴ = 16). others will stay OFF.
Decoder
Decoder – Main Use

Purpose: Converts n input lines into 2ⁿ output lines.

Main Use:

○ To decode binary information into a specific output line.

○ Used in memory address decoding, where the binary address selects a particular memory location.

○ Helps in activating specific devices based on binary input signals.

Example: A Binary-to-Decimal Decoder takes 4 input bits and activates one of the 16 output lines.
Register Transfer Language (RTL)
In symbolic notation, RTL is used to describe how data (micro-operations) is transferred from one register to
another.
Register Transfer:
When information is moved from one register to another, it is shown in symbolic form using the replacement
operator. This process is called register transfer.

Replacement Operator :
In the statement, R2 <- R1, <- acts as a replacement operator.

Example:
R1 ← R2
This means the contents of register R2 are copied into register R1.
Micro-operations
Micro-operations are the smallest basic operations performed on the data stored inside registers of a
computer.

• Register transfer micro-operations:

Types of Micro-operations The micro-operations that transfer the
1. Register Transfer Micro-operations information from one register to
another.
○ Moving data from one register to another.
○ Example: R1 ← R2 (contents of R2 copied into R1).
• Arithmetic micro-operations: The
2. Arithmetic Micro-operations micro-operations that perform
○ Perform arithmetic calculations. arithmetic operations on numeric data
○ Example: R3 ← R1 + R2 (add contents of R1 and R2, store in R3).
stored in registers.
3. Logic Micro-operations
○ Perform bitwise logical operations (AND, OR, NOT, XOR). • Logic micro-operation: the
○ Example: R1 ← R1 AND R2. micro-operations that perform bit
4. Shift Micro-operations
manipulation operations.
○ Shift the bits of a register left or right.
○ Example: R1 ← shl(R1) (shift left contents of R1). • Shift micro-operations: The
micro-operations that perform shift
operations on data stored in registers.
TASK
● R2 <- R1, Identify source and Destination register.
● Write micro-operation sequence to perform addition of two
numbers.
BLOCK DIAGRAM OF REGISTER

H : High bit, L: Low bit

Two pair register
 REGISTER TRANSFER OPERATIONS

Simple (Unconditional) Transfer

● Data is always transferred from one register to another.

● It happens without any condition.

● Example:
R1 ← R2 EXAMPLE
(Contents of R2 are copied into R1 always).
Simple Transfer : R2 <- R1
The content of R1 are copied into
R2 without affecting the content of
R1. It is an unconditional type of
transfer operation.
 Conditional Transfer
● Data is transferred only if a certain condition is true.

● The condition is usually based on status flags (Zero, Carry, Sign, etc.).

● Example:
If (P = 1) then R1 ← R2
(Contents of R2 are copied into R1 only if condition P = 1 is satisfied).

Example:

If (Z = 1) then R3 ← R4

● Here, Z = Zero flag (it becomes 1 if the result of an operation is zero).

● This means:
○ If the last operation result was zero, then copy the contents of R4 into R3.
○ Otherwise, do nothing.
Conditional Transfer Control Circuit:

Registers (R1 and R2): ● Generates the control signal (T).

● Decides whether the transfer should happen or
Data is stored in registers.
not.
Here, contents of R1 are transferred to R2.
Control Variable (T):
n (No. of bits):
Shows how many bits of data are being moved from R1 to R2. ● T = 1 → transfer happens (R2 ← R1).
● T = 0 → transfer does not happen.

Load Input of R2:

R2 Load input that is
● Activated by the control signal.
activated by control n : No of bits ● It allows new data to enter R2 only when the
variable.
control signal is ON (T=1).

Clock Signal Clock Signal:

● Ensures the transfer happens in sync with the

clock pulse.
● Without the clock, data won’t move.
T is used as a control variable.

Notation (T : R2 ← R1):

● This means: “If T = 1, then copy the contents of

This block diagram shows how data from R1 is copied into R2 only
R1 into R2 on the clock pulse.”
when the control signal (T) = 1 and the clock pulse arrives.
Timing Diagram
● Clock goes up and down.

● Falling edge of clock = moment to check transfer.

● If Load = 1 → data moves from R1 to R2.

● If Load = 0 → no transfer happens.

Transfer occurs only at falling edge + Load = 1.

Timing Diagram ● At time T1 → The value inside Register A goes into Register R1.

● At time T2 → The value inside Register B goes into Register R1.

This means R1 gets updated two times:

● First with A’s data.

● Later (at a different clock/timing), with B’s data.

Key Point:

● Even though the destination (R1) is the same,

T1: R1<-A ● The source is different (A first, then B).

● The time is also different (T1 vs T2).

T2:R1<-B So, there is no conflict—because both assignments don’t happen at the

same moment.
It means:

● At time T1, data from Register A is

copied into Register R1.

● At time T2, data from Register B is

copied into Register R1.

So, R1 is the same destination, but at

different times it receives data from different
sources.

This shows that timing (T1, T2) controls

which register’s data gets transferred to R1.
MOST COMMON REGISTERS IN
COMPUTER
 1. Program Counter (PC) [11 bits]
○ Holds the address of the next instruction to be executed.
○ Increases step by step as program runs.
2. Address Register (AR) [11 bits]
○ Stores the memory address where data/instruction will be fetched from or stored to.
3. Instruction Register (IR) [16 bits]
○ Holds the current instruction that the CPU is decoding and executing.
4. Temporary Register (TR) [16 bits]
○ A helper register for storing data temporarily during operations.
5. Data Register (DR) [16 bits]
○ Holds the data fetched from memory or the data that will be written into memory.
6. Accumulator (AC) [16 bits]
○ A special register where all arithmetic and logic results are stored.
○ Example: If you add 5 + 3, the result (8) is stored in AC.
7. INPR (Input Register) [8 bits]
○ Holds the character or data from input devices (like keyboard).
8. OUTR (Output Register) [8 bits]
○ Holds the character or data to be sent to output devices (like display).
9. Processor (CPU) [16-bit]
○ The “brain” that controls everything, executes instructions using these registers.

10. Memory (4046 words × 16 bits)

● Stores both instructions and data.
● Each word is 16 bits wide.
POINTS TO REMEMBER: (MCQ)

The Program Counter tells which instruction to fetch.

The Address Register helps point to memory.

The Instruction Register holds the fetched instruction.

The Data Register + Accumulator handle the actual data operations.

Temporary Register is used as a helper.

INPR/OUTR are used for communication with input/output devices.

Memory stores everything.

The CPU coordinates all transfers between these blocks.

MOST COMMON REGISTERS IN
COMPUTER/CLASSIFICATION OF
COMPUTER REGISTERS
TYPES OF INSTRUCTIONS
TYPES
Opcode: Operation code First byte = Opcode.

Second + Third byte = 16-bit Address or

Data.

Example: LDA 2050H (load contents from

memory location 2050H into A).

Needs 3 bytes: one for instruction, two for full

address.

First byte = Opcode (operation).

Second byte = Data (8-bit immediate).

Example: MVI A, 32H (move 32H directly

into A).
What Are Combinational Circuits?

A combinational circuit is a type of digital logic circuit where the output depends only on the current
inputs—not on any previous input or stored data. That means it has no memory and no feedback loops.

Key Characteristics:
•Output is determined solely by present input values.
•No clock signal is needed.
•No storage or memory element involved.
•Built using basic logic gates like AND, OR, NOT, NAND, NOR, XOR.
EXAMPLE
SYMBOLIC NOTATION FOR SHIFT
OPERATION
SYMBOLIC NOTATION FOR SHIFT OPERATION
LOGICAL SHIFT

It transfers the 0 zero through the serial

input. We use the symbols ‘<<‘ for the
logical left shift and ‘>>‘ for the logical right
shift.
CIRCULAR SHIFT
Arithmetic Left Shift (Same as Logical shift):
In this shift, each bit is moved to the
left one by one. The empty least
significant bit (LSB) is filled with zero
and the most significant bit (MSB) is
rejected. Same as the Left Logical
Shift.

Arithmetic Right Shift:

In this shift, each bit is moved to the
right one by one and the least
significant(LSB) bit is rejected and
the empty most significant bit(MSB)
is filled with the value of the
previous MSB.
Boolean Algebra
Boolean Algebra is a branch of mathematics that deals with logic values – only two states:

○ 1 (True / High / ON)

○ 0 (False / Low / OFF)

It is the foundation of digital circuits (used in computers).

 Basic Operations
Basic Operations

1. AND (·)

○ Output is 1 only if both inputs are 1.

○ Example: A·B

Truth Table:
Basic Operations
OR (+)

● Output is 1 if at least one input is 1.

● Example: A + B

● Truth Table:
Basic Operations
NOT (’)

● Flips the value (1 → 0, 0 → 1).

● Example: A’

● Truth Table:
Boolean Algebra Rules (Simplification)

AND .

OR +
Logic Gate Symbols

And waveform behavior in time as follows:

Complementing Functions
Use DeMorgan's Theorem:

Interchange AND and OR operators

Precedence Rules
Example Expression:

A + B’C

Step-by-Step (Using Precedence Rules)

1. Complement first (NOT):

○ Take B’ (opposite of B).

2. AND next:
○ Multiply (AND) B’ with C → B’·C.

3. OR last:
○ Add (OR) A with the result → A + (B’·C).

order of precedence (NOT → AND → OR).

Evaluate logic function
F(X,Y,Z)=XY+YZ’
Difference between Combinational Circuit and Sequential Circuit

Feature Combinational Circuit Sequential Circuit

Output depends only on the present Output depends on present input

Definition input. + past history (memory).

Has memory (Flip-Flops). Can

Memory No memory. Cannot store data. store data.
Needs a clock signal for
Clock Does not need a clock. operation.

Adders, Subtractors, Multiplexers,

Examples Decoders. Flip-Flops, Counters, Registers.

Slower (depends on clock and

Speed Faster (no delay of memory). memory).

For simple calculations and data For storing values, synchronizing,

Use transfer. and control.
FLIP FLOPS
What is a Flip-Flop?

● A Flip-Flop is the basic sequential logic circuit used to store 1 bit of data (either 0 or 1).

● It has two stable states → so it’s also called a bistable device. (It has two stable states → ON (1) or OFF
(0).)

● A Flip-Flop is a small memory unit.

● It can store only 1 bit (either 0 or 1).

● It changes state only when a clock signal comes.

● Used in:

a. Registers (to hold data temporarily)

b. Counters (to count pulses/events)

c. Control circuits (to synchronize operations with the clock)

Types of Flip-Flops

1. SR Flip-Flop (Set-Reset)

○ Two inputs: S (set) and R (reset).

○ Used to store one bit, but has an invalid state when S=R=1.
○ Two outputs: Q and Q̅ (complement of Q).

2. JK Flip-Flop

○ Modified SR flip-flop (no invalid state).

○ Inputs: J and K.

○ If J=K=1, the output toggles (changes state).

3. D Flip-Flop (Data/Delay)

○ Has only one input D.

○ Output Q follows input D at the next clock pulse.

○ Widely used in registers and memory.

4. T Flip-Flop (Toggle)

○ Has single input T.

○ If T=1, output toggles; if T=0, output remains same.

○ Used in counters.
 S = 1, R = 0 → Set → Output becomes 1.

S = 0, R = 1 → Reset → Output becomes 0.

S = 0, R = 0 → No change → Output remains same as before.

S = 1, R = 1 → Invalid (both set and reset at the same time).

● Rising edge (↑) = 0 → 1 (positive edge).

● Falling edge (↓) = 1 → 0 (negative edge).
● Depending on design, a flip-flop can work on either rising or falling
The symbol ↑ means a edge.
rising edge of the clock
signal.

CLK ON
Output remains same as before.
VALUE : 1

Invalid (both set and reset at the same time).

TRUTH TABLE SR CURRENT & NEXT STATE
S R Qn (Current State) Qn+1 (Next State)

0 0 0 0 (No Change)
0 0 1 1 (No Change)
0 1 0 0 (Reset → stays 0)
0 (Reset →
0 1 1
becomes 0)
1 (Set → becomes
1 0 0
1)
1 0 1 1 (Set → stays 1)
1 1 0 Invalid
1 1 1 Invalid
 CLK ON

VALUE : 1

J K Q(n+1) (Next State)

0 0 No Change (Qn)
0 1 0
1 0 1
1 1 Toggle (¬Qn)
● J = 0, K = 0 → Output stays the same (No Change).

● J = 0, K = 1 → Output becomes 0 (Reset).

● J = 1, K = 0 → Output becomes 1 (Set).

● J = 1, K = 1 → Output toggles (changes from 0 → 1 or

1 → 0).
 The D Flip-Flop gives the same value at output (Q) as you give at input (D)
after the clock pulse.

That’s why it is called a Data Flip-Flop.

Simply: Output = Input.

CLK ON

VALUE : 1

D (Input) Qn+1 (Next State)

D (Input) Qn (Current State) Qn+1 (Next State)
0 0
0 0 0 (stays 0)
1 1
0 1 0 (changes to 0)

1 0 1 (changes to 1)
1 1 1 (stays 1)
 T Qn (Current State) Qn+1 (Next State)
0 0 0 (No Change)
CLK ON
0 1 1 (No Change)
1 0 1 (Toggle) VALUE : 1
1 1 0 (Toggle)

T = 0 → no change

T = 1 → Toggle (switch state)

Current State (Qn)

● It is the present value stored in the flip-flop.

● Example: If a flip-flop is storing 1 right now → its current state = 1.

Next State (Qn+1)

● It is the future value (what the output will become) after the next clock
pulse, depending on inputs and the current state.
● Example: If D = 0 and clock comes → the next state = 0, even if current
state was 1.
TWO WAYS TO CONSTRUCT THE BUS

1) BY USING MULTIPLEXERS
2) BY THREE STATE BUFFER
R1

R2←R1

b = a;
8 wires
For 32 bits?
Expensive

R2
 A0
A1 Register A
0,0 A2
A3
A3 A0
A2 A1
4 I/P, 1 O/P

Bus <- A
B<- Bus
 A0
A1 Register A
0,0 A2
A3
A3 A0
A2 A1
4 I/P, 1 O/P

Bus <- A
Load Signal
C<- Bus
LOAD = 0
LOAD of C = 1 (Active) LOAD = 0
LOAD = 0
Control Signal
Memory Read
R ← M[AR]
// Read: data from memory at address AR goes into register R

Memory Write
M[AR] ← R
// Write: data from register R goes into memory at address AR
NOTE
Number of multiplexers required = Number of bits in a register

● If register size = 8 bits → 8 multiplexers required (one multiplexer per bit line).

• If number of bits 4, _______ MULTIPLEXERS Required.

• Number of input in Multiplexers = No. of Registers ( If number of registers = N → Each multiplexer has N
inputs)

MCQ
If number of bits = 8 → 8 multiplexers required

If number of registers = N → Each multiplexer has N inputs

One way of constructing a common bus system is with multiplexers. The multiplexers select the source register whose
binary information is then placed on the bus. The construction of a bus system for four registers is shown in Fig. below.
Each register has four bits, numbered 0 through 3.

The bus consists of four 4 x 1 multiplexers each having four data inputs, 0 through 3, and two selection inputs, S1 and
S0. In order not to complicate the diagram with 16 lines crossing each other, we use labels to show the connections from
the outputs of the registers to the inputs of the multiplexers.

For example, output 1 of register A is connected to input 0 of MUX 1 because this input is labelled A1. The diagram
shows that the bits in the same significant position in each register are connected to the data inputs of one multiplexer to
form one line of the bus.

Thus MUX 0 multiplexes the four 0 bits of the registers, MUX 1 multiplexes the four 1 bits of the registers, and
similarly for the other two bits.
The two selection lines S1 and S0 are connected to the selection inputs of all four multiplexers.

The selection lines choose the four bits of one register and transfer them into the four-line common bus. When S1S0 =
00, the 0 data inputs of all four multiplexers are selected and applied to the outputs that form the bus.

This causes the bus lines to receive the content of register A since the outputs of this register are connected to the 0 data
inputs of the multiplexers. Similarly, register B is selected if S1S0 = 01, and so on. Table below shows the register that
is selected by the bus for each of the four possible binary value of the selection lines.
In general, a bus system will multiplex k registers of n bits each to produce an n-line common bus. The number
of multiplexers needed to construct the bus is equal to n, the number of bits in each register. The size of each
multiplexer must be k x 1 since it multiplexes k data lines.

For example, a common bus for eight registers of 16 bits each requires 16 multiplexers, one for each line in the
bus. Each multiplexer must have eight data input lines and three selection lines to multiplex one significant bit in
the eight registers.

The transfer of information from a bus into one of many destination registers can be accomplished by
connecting the bus lines to the inputs of all destination registers and activating the load control of the particular
destination register selected.

The symbolic statement for a bus transfer may mention the bus or its presence may be implied in the statement.
When the bus is includes in the statement, the register transfer is symbolized as follows: BUS ← C, R1 ← BUS

The content of register C is placed on the bus, and the content of the bus is loaded into register R 1 by
activating its load control input. If the bus is known to exist in the system, it may be convenient just to show the
direct transfer. R1 ← C

From this statement the designer knows which control signals must be activated to produce the transfer
through the bus.
 A buffer is often a set of flip-flops or

DIGITAL BUFFER register that temporarily stores data before it

is used.

The digital buffer is important in data transmission, translating voltage pulses between connected
systems.

Buffers are used in registers (data storage device) and buses (data transferring device).

10 1
0

High impedance – It doesn’t produce any output. O/P

is disconnected from the circuit.
 A bus system can be constructed with
three-state gates instead of multiplexers.
3 STATE BUFFER
1 1
To form a single bus line, all the outputs of the 4
buffers are connected together.

The control input will now decide which of the 4

normal inputs will communicate with the bus line.

The decoder is used to ensure that only one control

input is active at a time.
ACTIVE/CONTROL INPUT – 1
CONTROL INPUT 1 – PRODUCES THE OUTPUT
ENABLE – 1 (ACTIVE),0
0
SELECT – S0, S1 DEACTIVE/CONTROL
0
INPUTS - 0
2 – INPUT, 4 OUTPUT
0 1
1
2
3
A bus system can be constructed with three-state gates
instead of multiplexers.

A three-state gate is a digital circuit that exhibits three states.

Two of the states are signals equivalent to logic 1 and 0 as in
a conventional gate.

The third state is a high-impedance state. The

high-impedance state behaves like an open circuit, which
means that the output is disconnected
 STORE MEMORY – DATA +
INSTRUCTION

COMMON BUS SYSTEM To Read from memory

Read – Active

0
E – EXTENDED BIT (To store the
Extra bit, Example : Carry)
MEMORY
4096 SLOTS, 16 Bits
Data
INPUT FROM INPUT DEVICE(Keyboard)

PC
AR
MEMORY UNIT
BUS
 COMMON BUS SYSTEM
Basic Computer Registers connected to a common BUS.

• 4 registers DR, AC, IR (Instruction R – Holds Instruction code) and TR (Temporary R – Holds
Temporary data) have 16 bits and 2 registers AR and PC have 12 bits. The INPR and OUTR have 8
bits each.

• The INPR receives character from input device and delivers it to the AC while the OUTR receives
character from AC and transfers it to the output device.

• 5 registers have 3 control inputs LD (load), INR (increment) and CLR (clear).
 Abbreviation Register name
COMMON BUS SYSTEM OUTR Output register
• A typical digital computer has many registers, and paths
Temporary
must be provided to transfer information from one TR
register to another.
register

• A more efficient scheme for transferring information

Instruction
IR
between registers in a multiple-register configuration is a register
common bus system.
INPR Input register
• A bus structure consists of a set of common lines, one for
each bit of a register, through which binary information is AC Accumulator
transferred one at a time.
DR Data register
• Control signals determine which register is selected by
the bus during each particular register transfer. PC Program counter

• Note : The content of any register can be placed on the AR Address register
common bus and an operation can be performed in the
adder and logic circuit during the same clock cycle.
• The adder and logic circuit provides the 16 inputs of AC. This circuit has 3
sets of inputs. One set comes from the outputs of AC which implements
register micro operations. The other set comes from the DR (data register)
which are used to perform arithmetic and logic micro operations. The result
of these operations is sent to AC while the end around carry is stored in E
as shown in diagram. The third set of inputs is from INPR.

• Connections: The outputs of all the registers except the OUTR (output
register) are connected to the common bus. The output selected depends
upon the binary value of variables S2, S1 and S0. The lines from common
bus are connected to the inputs of the registers and memory. A register
receives the information from the bus when its LD (load) input is activated
while in case of memory the Write input must be enabled to receive the
information. The contents of memory are placed onto the bus when its
Read input is activated.