ELECTRONICS I

Dr. Aslı TAŞÇI

CHAPTER 3

THE FIELD EFFECT TRANSISTOR

Contents are created from Microelectronics Circuit Analysis and Design by Donald A. Neamen 1
In this chapter, we will:
❖Study and understand the operation and characteristics of the various types of
MOSFETs
❖Understand and become familiar with the DC analysis and design techniques of
MOSFET circuits
❖Examine three applications of MOSFET circuits
❖Investigate current source biasing of MOSFET circuits, such as those used in
integrated circuits
❖Analyze the DC biasing of multistage or multi-transistor circuits

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 Basic Structure of MOS Capacitor

The heart of the MOSFET is the metal-oxide-semiconductor

capacitor shown in Figure l. The metal may be aluminum or some
other type of metal. In most cases, the metal is replaced by a
high-conductivity polycrystalline silicon layer deposited on the oxide.

𝑡𝑜𝑥 = Thickness of the oxide

𝜀𝑜𝑥 = Oxide permittivity

Figure 1: The basic MOS capacitor structure

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MOS Capacitor Under Bias:
Electric Field and Charge

Figure 2: (a) A parallel-plate capacitor, showing the electric field and conductor charges,
(b) a corresponding MOS capacitor with a negative gate bias, showing the electric
field and charge flow, and (c) the MOS capacitor with an accumulation layer of holes

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 MOS Capacitor Under Bias

Figure 3: The MOS capacitor with p-type substrate: (a) effect of positive gate bias, showing the electric field
and charge flow, (b) the MOS capacitor with an induced space-charge region due to a moderate positive
gate bias, and (c) the MOS capacitor with an induced space-charge region and electron inversion layer
due to a larger positive gate bias
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 MOS Capacitor Under Bias

Figure 4: The MOS capacitor with n-type substrate: (a) effect of a positive gate bias and the formation of an electron
accumulation layer, (b) the MOS capacitor with an induced space-charge region due to a moderate negative
gate bias, and (c) the MOS capacitor with an induced space-charge region and hole inversion layer due to
a larger negative gate bias

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Schematic of n-Channel Enhancement Mode
MOSFET

Figure 5: (a) Schematic diagram of an n-channel enhancement-mode MOSFET and

(b) an n-channel MOSFET, showing the field oxide and polysilicon gate

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Basic Transistor Operation
Before electron inversion After electron inversion
layer is formed layer is formed

Figure 6: (a) Cross section of the n-channel MOSFET prior to the formation of an electron inversion layer,
(b) equivalent back-to-back diodes between source and drain when the transistor is in cutoff, and
(c) cross section after the formation of an electron inversion layer

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Basic Transistor Operation

Figure 7: The n-channel enhancement-mode MOSFET (a) with an applied gate voltage vGS < VT N , and
(b) with an applied gate voltage vGS > VT N

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Current vs. Voltage Characteristics:
Enhancement-Mode NMOS

Figure 8: Plot of iD versus vDS characteristic for small values of vDS at three vGS voltages

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Family of iD vs. vDS Curves:
Enhancement-Mode nMOSFET

Figure 9: Family of iD versus vDS curves for an n-channel enhancement-mode MOSFET.

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Symbols for n-Channel Enhancement-Mode
MOSFET

Figure 10: The n-channel enhancement-mode MOSFET: (a) conventional circuit symbol,
(b) circuit symbol that will be used in this text, and (c) a simplified circuit symbol
used in more advanced texts
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n-Channel Depletion-Mode MOSFET

Figure 11: Cross section of an n-channel depletion mode MOSFET for: (a) vGS = 0, (b) vGS < 0, and (c) vGS > 0

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Family of iD vs. vDS Curves:
Depletion-Mode nMOSFET

Figure 12: Family of iD versus vDS curves Figure 13: The n-channel depletion-mode MOSFET:
for an n-channel depletion-mode (a) conventional circuit symbol and
MOSFET. (b) simplified circuit symbol

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Summary of I-V Relationships
Table 1: Current – voltage relationship of n-channel MOSFET
Region NMOS

Nonsaturation vDS<vDS(sat)

Saturation vDS>vDS(sat)

Transition Pt. vDS(sat) = vGS - VTN

Enhancement Mode VTN > 0V
Depletion Mode VTN < 0V

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p-Channel Enhancement-Mode MOSFET

Figure 14: Cross section of p-channel enhancement-mode MOSFET. The device is cut off for vSG = 0.
The dimension W extends into the plane of the page.

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Symbols for p-Channel Enhancement-Mode
MOSFET

Figure 15: The p-channel enhancement-mode MOSFET: (a) conventional circuit symbol,
(b) circuit symbol that will be used in this text, and (c) a simplified circuit symbol
used in more advanced texts

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 p-Channel Depletion-Mode
MOSFET

Figure 17: The p-channel depletion mode

MOSFET: (a) conventional circuit
Figure 16: Cross section of p-channel depletion-mode MOSFET symbol and (b) simplified circuit
showing the p-channel under the oxide at zero gate voltage symbol
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Summary of I-V Relationships
Table 2: Current – voltage relationship of p-channel MOSFET

Region PMOS

vSD<vSD(sat)
Nonsaturation

vSD>vSD(sat)
Saturation

Transition Pt. vSD(sat) = vSG + VTN

Enhancement Mode VTP < 0V

Depletion Mode VTP > 0V

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Complementary MOSFETS (CMOS)

Figure 18: Cross sections of n-channel and p-channel transistors fabricated with a p-well CMOS technology

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Channel Length Modulation:
Early Voltage

Figure 19: Family of iD versus vDS curves showing the effect of channel length modulation
producing a finite output resistance

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 Body Effect

Figure 20: Two n-channel MOSFETs fabricated in series in Figure 21: An n-channel enhancement-mode
the same substrate. The source terminal, S2, of the MOSFET with a substrate voltage
transistor M2 is more than likely not at ground potential.

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 Subthreshold Condition

Figure 22: Plot of 𝑖𝐷 vs. vGS for a MOSFET biased in the saturation region showing subthreshold conduction.
Experimentally, a subthreshold current exists even for vGS < VTN

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Figure 23: An NMOS common-source circuit Figure 24: The DC equivalent circuit of the NMOS
common-source circuit

NMOS Common-Source Circuit

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Ex.3.3: NMOS enhancement mode DC
analysis
Calculate ID and VDS for
the circuit parameters given below;

R1 = 30 kΩ,
R2 = 20 kΩ,
RD = 20 kΩ,
VDD = 5 V,
VTN = 1 V,
Kn = 0.1 mA/V2 .

Figure 35: An NMOS commonsource circuit

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Load Line and Modes of Operation:
NMOS Common-Source Circuit

Figure 25: Transistor characteristics, vDS(sat) curve, load line, and Q-point for the NMOS common-source circuit.

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PMOS Common-Source Circuit

Figure 26: DC equivalent circuit of a PMOS common-source circuit

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Ex.3.4: PMOS enhancement mode DC
analysis
Calculate ID and VSD for
the circuit parameters given below;

R1 = R2 = 50 kΩ,
RD = 7.5 kΩ,
VDD = 5 V,
VTP = -0.8 V,
Kp = 0.2 mA/V2 .

Figure 36: A PMOS common-source circuit

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Problem-Solving Technique:
NMOSFET DC Analysis
1. Assume the transistor is in saturation.
a. VGS > VTN, ID > 0, & VDS ≥ VDS(sat)

2. Analyze circuit using saturation I-V relations.

3. Evaluate resulting bias condition of transistor.
a. If VGS < VTN, transistor is likely in cutoff
b. If VDS < VDS(sat), transistor is likely in nonsaturation region

4. If initial assumption is proven incorrect, make new assumption and repeat Steps 2 and 3.

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 Enhancement Load Device

Figure 27: Enhancementmode NMOS device Figure 28: Current–voltage characteristic of an

with the gate connected to the drain enhancement load device
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Circuit with Enhancement Load Device and
NMOS Driver

ML is always in saturation.

MD can be biased either in

saturation or nonsaturation
region.

Figure 29: Circuit with enhancement-load

device and NMOS driver
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Voltage Transfer Characteristics: NMOS
Inverter with Enhancement Load Device

Figure 30: Voltage transfer characteristics of NMOS

inverter with enhancement load device
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NMOS Inverter with Depletion Load Device

Figure 31: Circuit with depletion-load Figure 32: Voltage transfer characteristics of NMOS
device and NMOS driver inverter with depletion load device

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CMOS Inverter

Figure 33: Example of CMOS inverter Figure 34: Voltage transfer characteristics of CMOS inverter

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NMOS Inverter
The MOSFET can be used as a switch in a wide
variety of electronic applications. The transistor
switch provides an advantage over mechanical
switches in both speed and reliability.

Figure 37: NMOS inverter circuit

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Two-Input NMOS NOR Logic Gate

Table 3: NMOS NOR logic circuit response

V1 (V) V2 (V) VO (V)

0 0 High
5 0 Low
0 5 Low
5 5 Low

Figure 38: A two-input NMOS NOR logic gate

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MOSFET Small-Signal Amplifier

Figure 39: (a) An NMOS common-source circuit with a time-varying signal coupled to the gate and
(b) transistor characteristics, load line, and superimposed sinusoidal signals
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Constant
Current Biasing

Figure 40: (a) NMOS current mirror and (b) PMOS current mirror
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Two-Stage Cascade Amplifier

Source follower

Common-source
Figure 41: Common-source amplifier in cascade with source follower

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NMOS
Cascode Circuit

Figure 42: NMOS cascode circuit

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 Design example 3.17

Transistor parameters:
Kn1 = 500 µA/V2
Kn2 = 200 µA/V2
VTN1 =VTN2 = 1.2 V
λ1 = λ2 = 0

Design the circuit such that

IDQ1 = 0.2 mA
IDQ2 = 0.5 mA
VDSQ1 = VDSQ2 = 6 V
Ri = 100 kΩ and Rsi = 4 kΩ
Figure 43: Common-source amplifier in cascade with source follower

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Design example 3.18

Transistor parameters:
Kn1 = Kn2 = 0.8 mA/V2
VTN1 =VTN2 = 1.2 V
λ1 = λ2 = 0
Let
R1 + R2 + R3 = 300 kΩ
RS = 10 kΩ
Design the circuit such that
IDQ = 0.4 mA
VDSQ1 = VDSQ2 = 2.5 V

Figure 44: NMOS cascode circuit

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