EE 324: Microcontroller and Interfacing

Chapter 4
Timing Interfaces

Hafsa Qamar EE-324: Microcontrollers and Interfacing 1

 Content

• Basics of Timing Interfaces

• Clocking a Microcontroller (Phase Locked Loop)

• TM4C123 Clock Configuration

• Counters/Timers

• TM4C123 Timing Interfaces

a. Systick Timer
b. Timer as Input Device
c. Timer as Output Device
d. General Purpose Timer

• Configuration Examples

• PWM

Hafsa Qamar EE-324: Microcontrollers and Interfacing 2

 Basics of Timing Interfaces

Timing Interfaces

System Clock Timer

To operate uC Peripheral Module:

at desired • Counting events
• Making delays
frequency
• Measuring time b/w 2 events

Sources: Modes:
• Internal RC Oscillator • One-shot mode
• External Crystal Oscillator • Periodic mode
• PLL • Capture mode
• Low-Frequency Internal Oscillator • PWM mode

Hafsa Qamar EE-324: Microcontrollers and Interfacing 3

 Clocking a Microcontroller

Clocking Mechanisms

Crystal
RC Oscillator PLL
Oscillator

• Fast startup (µs) • Generates flexible

• High accuracy system clocks
• Cheap (often on-chip,
• Very stable across no external • Requires reference
temperature/voltage components) source (crystal/RC)

• Slower startup (ms • Low accuracy • Supports high-

range) (affected by VDD & performance
temperature) operation
• Needs external
crystal/resonator • Good for low-cost, • Allows dynamic
general timing frequency scaling
Hafsa Qamar EE-324: Microcontrollers and Interfacing 4
 Clocking a Microcontroller

Illustration of different clock sources in Cortex-M based microcontroller

Hafsa Qamar EE-324: Microcontrollers and Interfacing 5

 Phase Lock Loop (PLL)

• Ensures output remains synchronized (locked) to reference input

• Main Components:
1. Phase Comparator
▪ Compares phase of input frequency (𝑓𝑖 ) with output (𝑓𝑜 )
▪ Produces an error signal if not aligned

2. Loop Filter
▪ Smooths the error signal to remove high-frequency noise
▪ Provides stable control voltage

3. Voltage Controller Oscillator (VCO)

▪ Generates output frequency (𝑓𝑜 ) based on control voltage
▪ Adjust frequency until 𝑓𝑜 is phase-locked to 𝑓𝑖

Block diagram of PLL

Hafsa Qamar EE-324: Microcontrollers and Interfacing 6
 PLL as a Frequency Multiplier

• Generates higher-frequency system clock from a lower-frequency reference input

• Main Components:
1. Phase Comparator
2. Loop Filter
3. Voltage Controller Oscillator (VCO)

4. Counter 𝑁1 (Feedback divider)

𝑓𝑜
▪ Divides VCO output before comparison = 𝑓𝑖 : 𝑓𝑜 = 𝑁1 𝑓𝑖
𝑁1

5. Counter 𝑁2 (Post-scaler)
𝑓𝑜 𝑁1
▪ Further divides 𝑓𝑜 to generate system clock 𝑓𝑠 = 𝑓𝑠 : 𝑓𝑠 = 𝑓
𝑁2 𝑁2 𝑖

PLL as a frequency multiplier

Hafsa Qamar EE-324: Microcontrollers and Interfacing 7
 PLL as a Frequency Multiplier – Practice Problem

A Cortex-M microcontroller uses a 16 MHz crystal oscillator as the reference input (𝑓𝑖 )
to its PLL
• The PLL has a feedback divider 𝑁1 = 25
• The PLL has a post-divider 𝑁2 = 5 before feeding the system clock

Questions:
1. What is the VCO output frequency 𝑓𝑜 ?
2. What is the system clock frequency 𝑓𝑠 after the post-divider?
3. If the system requires a 40 MHz clock, suggest a valid new pair of (𝑁1 , 𝑁2 ) values?
Solution:
1. 𝑓𝑜 = 𝑁1 𝑓𝑖 = 25*16 MHz = 400 MHz
𝑓 400
2. 𝑓𝑠 = 𝑁𝑜 = 5
MHz = 80 MHz
2

𝑁1 𝑁1 𝑁1
3. For 40 MHz system clock: 𝑓𝑠 = 𝑓 → 40 = .16 → = 2.5
𝑁2 𝑖 𝑁2 𝑁2

Possible solutions:
𝑁1 = 25, 𝑁2 = 10
𝑁1 = 5, 𝑁2 = 2

Hafsa Qamar EE-324: Microcontrollers and Interfacing 8

 TM4C123 Clock
• System Configuration at Startup
✓ User program can configure clock, power, reset during initialization

• Two Main Components

✓ Clock Source Selection (Internal RC, External Crystal, etc.)
✓ Clock Frequency Setting (direct or via PLL)

• Default Behavior
✓ After reset, MCU runs at default clock source & frequency
✓ If sufficient → no user reconfiguration needed

• When Reconfiguration is Needed

✓ Application requires different performance
✓ Dynamic scaling for power saving or heat management

• Registers Used
✓ RCC (Run-Mode Clock Configuration)
✓ RCC2 (Run-Mode Clock Configuration 2)
✓ Control clock source, PLL enable, and frequency dividers

• PLL Behavior
✓ Generates fixed 400 MHz output
✓ Divided internally to required system frequency. Provides high-performance clocking
Hafsa Qamar EE-324: Microcontrollers and Interfacing 9
 Counters/Timers

• Flips Flops to create up/down counters

• Up-counter:
✓ Begins counting from zero and its value increases on each clock until is reaches its
maximum value
✓ Overflows and rolls over to zero in next clock

0 1 2 255 0
Overflow = 0 Overflow = 0 Overflow = 0 Overflow = 1 Overflow = 0

8-bit Up-Counter Stages

• Down-counter:
✓ Begins counting from its maximum value and decreases on each clock until is reaches 0
✓ Overflows and rolls over to maximum value in next clock

255 254 1 0 255

Underflow = 0 Underflow = 0 Underflow = 0 Underflow = 1 Underflow = 0

8-bit Down-Counter Stages

Hafsa Qamar EE-324: Microcontrollers and Interfacing 10
 Counters Usage

• Counters usages:
✓ Counting events
✓ Making delays
✓ Measuring time between two events

1. Counting events
✓ Example: Count the number of cars going through a street → Up counters

2. Making Delays
✓ Using counter as a timer
✓ Example: Run a microwave oven for 60 seconds

1 Hz
Clock
Up Counter 60
generator

Compare
It sets after 60 seconds
Using counter as a timer

Hafsa Qamar EE-324: Microcontrollers and Interfacing 11

 Counters Usage (Cont’d)

3. Measuring the time between two events:

✓ Example: Amount of time it takes a marathon runner to go from the start to finish point
✓ Counter is cleared at start
✓ Increases on each clock pulse
✓ Value of counter is loaded into another register when the runner passes the finish line.

1 Hz
Clock
Up Counter Start signal
generator

Finish signal Register

Using counter to measure the time between two events

Hafsa Qamar EE-324: Microcontrollers and Interfacing 12

 Timer/Counter

• Timer: If the clock to the timer comes from internal sources such as
PLL, crystal oscillator or RC oscillator

• Counter: If the clock source comes from external source such as

pulses fed to the CPU pin (input)
✓ Example: increments once every time an external digital signal connected
to a specific input pin transitions

Hafsa Qamar EE-324: Microcontrollers and Interfacing 13

 Timers as Input/Output Device

Use of Timers

As Output As Input
Device Device

Delays Time PWM Counters (captures

based
external events)
interrupts

Hafsa Qamar EE-324: Microcontrollers and Interfacing 14

 Systick Timer

• Systick timer allows the system to initiate an action on a periodic basis

• This action is performed internally at a fixed rare without an external signal

• Widely used by OS so that system software may interrupt the application software
periodically to monitor and control the systems operations

• Systick Timer is a 24-bit down counter driven by either the system clock or the
internal oscillator
CLK_SRC

PIOSC /4 STRELOAD
0
Count
STCURRENTload
Flag
System clock 1 Enable

Systick timer internal structure

Hafsa Qamar EE-324: Microcontrollers and Interfacing 15

 Systick Registers

• Systick Registers:
1. Systick Control Register (STCRTL)
2. Systick Reload Value Register (STRELOAD)
3. Systick Current Value Register (STCURRENT)

CLK_SRC

PIOSC /4 STRELOAD
0
Count
STCURRENTload
Flag
System clock 1 Enable

Systick timer internal structure

Hafsa Qamar EE-324: Microcontrollers and Interfacing 16

 Systick Registers

1. Systick Control Register (STCRTL)

Bit field allocation of systick control register

Hafsa Qamar EE-324: Microcontrollers and Interfacing 17

 Systick Registers

1. Systick Reload Value Register (STRELOAD)

▪ STRELOAD is used to program the start value of Systick down counter
▪ N − 1 for an N-tick period (because counter counts down to zero)
▪ Highest value: 0xFFFFFF (32-bit register, only lower 24 bits are used)

Bit field allocation of Systick reload value register

2. Systick Current Value Register (STCURRENT)

▪ Shows the live down-count value (remaining ticks)

Bit field allocation of Systick current value register

Hafsa Qamar EE-324: Microcontrollers and Interfacing 18

 Systick Registers – Practice Problem

In an ARM microcontroller system clock = 16 MHz. Calculate the delay which is

made by the following function.

void delay()
{
SysTick->LOAD = 9;
SysTick->CTRL = 5; /*Enable the timer and choose system clock
as clock source*/

While((SysTick->CTRL &0x10000)==0) /*Wait until count flag is

set*/
{}
SysTick->CTRL = 0; /*Stop the timer (Enable = 0) */
}

Since system clock is chosen as clock source, each clock lasts

1 1
= 𝑠𝑦𝑠𝑐𝑙𝑘 = 16 𝑀𝐻𝑧 = 0.0625 𝑢𝑠

So program makes a delay of 10 x 0.0625 𝑢𝑠 = 625 𝑛𝑠

Hafsa Qamar EE-324: Microcontrollers and Interfacing 19

 Systick Registers – Practice Problem

What should be the value of SysTick->LOAD that makes a delay of 1 ms. Assume
sysclk = 16 MHz? Delay = N+1/sysclk

N+1 = delay x sysclk

N+1 = 1ms x 16 MHz
N+1 = 16000
N = 15999

The value in SysTick->LOAD is 15999

Hafsa Qamar EE-324: Microcontrollers and Interfacing 20

 Timer as Output Device - Generating Delays

Time delays can be created using timers by using the following registers:

1. Run mode Clock Gating Control Timer (RCGCTimer)

2. GPTM Timer Value (GPTMTnV)

3. GPTM Timer A Match Register (GPTMTAMATCHR)

4. GPTM Raw Interrupt Status (GPTMRIS)

5. GPTM Control Register (GPTMCTL)

6. GPTM Configuration Register (GPTMCFG)

7. GPTM Timer A Mode Selection (GPTMTAMR)

8. GPTM Timer n Interval Load (GPTMTnILR)

9. Prescaler Register

Hafsa Qamar EE-324: Microcontrollers and Interfacing 21

 Generating Delays Using Timers

1. Run mode Clock Gating Control Timer (RCGCTimer)

Bit field allocation of Run mode Clock Gating Control Timer (RCGCTimer)

Bit Name Description

0 R0 Timer 0 clock control (0: clock disabled, 1: clock enabled)
1 R1 Timer 1 clock control (0: clock disabled, 1: clock enabled)
2 R2 Timer 2 clock control (0: clock disabled, 1: clock enabled)
3 R3 Timer 3 clock control (0: clock disabled, 1: clock enabled)
4 R4 Timer 4 clock control (0: clock disabled, 1: clock enabled)
5 R5 Timer 5 clock control (0: clock disabled, 1: clock enabled)

SYSCTL_RCGCTIMER_R |= (1 << 0); // Enable clock for Timer 0

while((SYSCTL_PRTIMER_R & (1 << 0)) == 0); // Wait for the

clock to stabilize
Hafsa Qamar EE-324: Microcontrollers and Interfacing 22
 Generating Delays Using Timers

2. GPTM Timer Value (GPTMTnV)

• It holds the current count value of the timer → what the timer is currently
counting down to or up to depending on the mode

• n → Timer letter (A or B): GPTMTAV (Timer A value register), GPTMTBV (Timer

B value register)

• When timer is in 16-bit mode, GPTMTAV & GPTMTBV work as 2 separate

counters. In 32-bit mode, they are cascaded to form a 32-bit counter

• When counting down, GPTMTnV decreases from GPTMTnILR (the load value)
down to 0, when counting up, GPTMTnV increases from 0 up to GPTMTnILR.

• You can read it anytime to check the current timer count.

• Read-only register → allows to check elapsed time or remaining time

while(1)
{
uint32_t value = TIMER0->TAV;// Read GPTMTnV (Timer A Value)
// 'value' shows how much time remains before timeout
}
Hafsa Qamar EE-324: Microcontrollers and Interfacing 23
 Generating Delays Using Timers

3. GPTM Timer A Match Register (GPTMTAMATCHR)

• Holds the match value to compare with the current timer count (GPTMTAV)

• When a match occurs → can toggle output (generally in PWM) & trigger an
interrupt

• When current timer A count (GPTMTAV) and Timer A Match Register

(GPTMTAMATCHR) match:
✓ TAMRIS (Timer A Match Raw Interrupt) Flag goes up indicating a match
✓ Bit 4 of GPTM Raw Interrupt Status (GPTMRIS) belongs to this flag

• Used to generate early interrupts before timeout.

Hafsa Qamar EE-324: Microcontrollers and Interfacing 24

 Generating Delays Using Timers

4. GPTM Raw Interrupt Status (GPTMRIS)

• Shows raw interrupt flags for Timer A and Timer B events
• Each bit corresponds to a specific interrupt source.

Bit field allocation of GPTM Raw Interrupt Status (GPTMRIS)

Bit Name Description
0 TATORIS Timer A Timeout Raw Interrupt (0: no, 1: yes)
1 CAMRIS Timer A Capture Match Raw Interrupt (0: no, 1: yes)
2 CAERIS Timer A Capture Event Raw Interrupt (0: no, 1: yes)
3 RTCRIS RTC Raw Interrupt (0: no, 1: yes) → Real time clock
4 TAMRIS Timer A Match Raw Interrupt (0: no, 1: yes)
8 TBTORIS Timer B Timeout Raw Interrupt (0: no, 1: yes)
9 CBMRIS Timer B Capture Match Raw Interrupt (0: no, 1: yes)
10 CBERIS Timer B Capture Event Raw Interrupt (0: no, 1: yes)
11 TBMRIS Timer B Match Raw Interrupt (0: no, 1: yes)
16 WUERIS 32/64-bit GPTM Write Update Error Interrupt (0: no, 1: yes)
Hafsa Qamar EE-324: Microcontrollers and Interfacing 25
 Generating Delays Using Timers

5. GPTM Control Register (GPTMCTL)

• Timers must be disabled during initialization → Modifying the configuration of
running timers can cause unpredictable results

Bit field allocation of GPTM Control Register (GPTMCTL)

Bit Name Description

0 TAEN Timer A Enable (0: disabled, 1: enabled)
1 TASTALL Timer A Stall (debug use) → 0: Continues counting if CPU halted, 1: Stops
counting if CPU halted
2&3 TAEVENT Timer A Event Mode (0: positive edge, 1: negative edge, 2: reserved, 3: both
edges)
4 RTCEN RTC Stall Enable (debug use) → 0: RTC stalls if CPU halted, 1: RTC continues
counting
5 TAOTE Timer A Output Trigger Enable (0: ADC trigger disabled, 1: enabled)
6 TAPWML Timer A Wait-on-Trigger → 0: Begins counting when enabled, 1: Waits for
trigger input
Hafsa Qamar EE-324: Microcontrollers and Interfacing 26
 Generating Delays Using Timers

6. GPTM Configuration Register (GPTMCFG)

• To configure timer as 16-bit or 32-bit mode, GPTMCFG is used

Bit field allocation of GPTM Configuration Register (GPTMCFG)

Bit 0,1,2 Mode

000 32-bit mode
100 16-bit mode

Hafsa Qamar EE-324: Microcontrollers and Interfacing 27

 Generating Delays Using Timers

7. GPTM Timer A Mode Register (GPTMTAMR)

Bit field allocation of GPTM Timer A Mode Register (GPTMTAMR)

Bit Name Description

0&1 TAMR Timer A Mode
2 TACMR Timer A Capture Mode (0: Edge Count, 1: Edge Time)
3 TAAMS Timer A Alternate Mode Select (0: Capture/Compare, 1: PWM mode)
Bit Bit Mode
4 TACDIR Timer A Count Direction (0: Down, 1: Up) → default down count 1 0
5 TAMIE Timer A Match Interrupt Enable (0: Disabled, 1: Enabled)
0 0 Reserved
6 TAWOT Timer A Wait-on-Trigger (0: Begins counting when enabled, 1: Waits
0 1 One-shot
for trigger)
7 TASNAPS Timer A Snap-Shot Mode (0: Disabled) 1 0 Periodic
8 TAILD Timer A Interval Load Write 1 1 Capture
9 TAPWMIE Timer A PWM Interrupt Enable (0: Disabled, 1: Enabled)
10 TAMRSU Timer A Match Register Update
11 TAPLO Timer A PWM Legacy Operation

Hafsa Qamar EE-324: Microcontrollers and Interfacing 28

 Generating Delays Using Timers

8. GPTM Timer n Interval Load (GPTMTnILR)

Timer in Count Down Mode:
• When timer is counting down → counter begins counting from GPTMTnILR and
goes down to zero
• Counter is reloaded with value from GPTMTnILR and TnTORIS flag of GPTMRIS
is raised
Timer in Count Up Mode:
• Timer begins from zero and goes up to GPTMTnILR.
• Timer is cleared to zero and TnTORIS flag of GPTMRIS is raised

Timer value Timer value

TnTORIS = 1 TnTORIS = 1
GPTMTnILR GPTMTnILR

time time
0 0 TnTORIS = 1 TnTORIS = 1

Down Counting Up Counting

Hafsa Qamar EE-324: Microcontrollers and Interfacing 29

 Practice Problem

Assume GPTMTAILR = 5 and Timer A is counting up. Explain when the TATORIS
flag is raised.

Solution:

The timer counts up with the passing of each clock provided by the crystal
oscillator. As the timer counts up, it goes through states 0,1,2,3,4 and 5.
One more clock rolls it to 0, raising TATORIS.

0 1 2 3 4 5 0

TATORIS = 0 TATORIS = 0 TATORIS = 0 TATORIS = 0 TATORIS = 0 TATORIS = 0 TATORIS = 1

Hafsa Qamar EE-324: Microcontrollers and Interfacing 30

 Generating Delays Using Timers

9. Prescaler Register
• Extends the 16-bit timer to 24-bit resolution.

• Enables creation of longer time delays beyond the 4.096 ms limit. To achieve
longer delays, use the 8-bit prescaler register (GPTMTAPR).

• Prescaler range: 0x00 → 0xFF (1 to 256)

• Available only in down-count mode

Hafsa Qamar EE-324: Microcontrollers and Interfacing 31

 Generating Delays Using Timers – Program Code

Use of TimerA of Timer0 to generate delay of 500 milliseconds in periodic, down count mode:
#include "TM4C123GH6PM.h"

void timer0A_delayMs(int ttime);

int main(void)
{
/* Enable clock to GPIOF at clock gating control register */
SYSCTL->RCGCGPIO |= 0x20;

/* Enable the GPIO pins for the red LED (PF1) as output */
GPIOF->DIR |= 0x02;

/* Enable the GPIO pins for digital function */

GPIOF->DEN |= 0x02;

while(1)
{
GPIOF->DATA = 2; /* Turn ON red LED (PF1) */
timer0A_delayMs(500); /* 500 ms delay */

GPIOF->DATA = 0; /* Turn OFF red LED */

timer0A_delayMs(500); /* 500 ms delay */
}
Hafsa Qamar EE-324: Microcontrollers and Interfacing 32
 Generating Delays Using Timers – Program Code (Cont’d)
void timer0A_delayMs(int ttime)
{
int i;

SYSCTL->RCGCTIMER |= 1; /* Enable clock to Timer Block 0 */

TIMER0->CTL = 0; /* Disable TimerA before initialization */

TIMER0->CFG = 0x04; /* Configure for 16-bit timer mode */
TIMER0->TAMR = 0x02; /* Periodic mode and down-counter */
TIMER0->TAILR = 16000 - 1; /* TimerA interval load value for 1 ms @16 MHz */
TIMER0->ICR = 0x1; /* Clear TimerA timeout flag */
TIMER0->CTL |= 0x01; /* Enable TimerA after initialization */

for(i = 0; i < ttime; i++)

{
while((TIMER0->RIS & 0x1) == 0); /* Wait for TimerA timeout flag (TATORIS)*/
TIMER0->ICR = 0x1; /* Clear TimerA timeout flag */
}
}

Hafsa Qamar EE-324: Microcontrollers and Interfacing 33

 Generating Delays Using Timers – Practice Problem

For CPU frequency = 16 MHz, calculate the largest delay size using
a) 16-bit timer A without Prescaler
b) 16-bit timer A with Prescaler

Period of clock pulse = 1/16MHz = 62.5 ns

a) Delay = 65536 x 65.5 ns = 4.096 ms

b) Delay = 65536 x 65.5 ns x 256 = 1.0485 s

Hafsa Qamar EE-324: Microcontrollers and Interfacing 34

 Timer as Input Device

• When timer works as an input device, it captures external events

• External events are captured either in edge-count mode or edge-time

mode

Feature Edge-Count Mode Edge-Time Mode

Counts number of external Measures time between signal
Purpose
pulses/events edges
Increments count each time an Captures the timer value at
What Timer Does
edge occurs each edge
Time interval or frequency of
Output / Result Total number of pulses
signal
Counting revolutions, object Measuring pulse width, period,
Use Case
detection, event counting or frequency
Count how many times a Measure duration of high pulse
Example
button is pressed in a PWM signal

Hafsa Qamar EE-324: Microcontrollers and Interfacing 36

 Edge-Time Capturing

• The timer can record the exact time when an input signal changes (rising
or falling edge).

• When an edge occurs, the current timer value is saved in a capture

register, but the timer keeps running.

• The saved values can be used to find the time difference between two
edges.

• This helps measure pulse width, signal period, or frequency.

• To set Capture mode with Edge Time,

▪ In GPTMTAMR register, TnMR = 3 (0b11 → Capture mode)
▪ TnCMR (Timer A Capture Mode ) = 1 → edge time

• The timer can capture on rising, falling, or both edges.

• The TnEVENT bits in GPTMCTL register decide which edge is captured.

Hafsa Qamar EE-324: Microcontrollers and Interfacing 37

 Edge-Time Capturing: GPTMTAMR & GPTMCTL
GPTM Timer A Mode Register (GPTMTAMR)
Bit Name Description
0&1 TAMR Timer A Mode
2 TACMR Timer A Capture Mode (0: Edge Count, 1: Edge Time)
3 TAAMS Timer A Alternate Mode Select (0: Capture/Compare, 1: PWM mode) Bit Bit Mode
1 0
4 TACDIR Timer A Count Direction (0: Down, 1: Up) → default down count
5 TAMIE Timer A Match Interrupt Enable (0: Disabled, 1: Enabled) 0 0 Reserved

6 TAWOT Timer A Wait-on-Trigger (0: Begins counting when enabled, 1: Waits 0 1 One-shot
for trigger) 1 0 Periodic
7 TASNAPS Timer A Snap-Shot Mode (0: Disabled) 1 1 Capture
8 TAILD Timer A Interval Load Write
9 TAPWMIE Timer A PWM Interrupt Enable (0: Disabled, 1: Enabled)
10 TAMRSU Timer A Match Register Update
11 TAPLO Timer A PWM Legacy Operation

GPTM Control Register (GPTMCTL)

Bit Name Description
0 TAEN Timer A Enable (0: disabled, 1: enabled)
1 TASTALL Timer A Stall (debug use) → 0: Continues counting if CPU halted, 1: Stops counting if CPU
halted
2&3 TAEVENT Timer A Event Mode (0: positive edge, 1: negative edge, 2: reserved, 3: both edges)
4 RTCEN RTC Stall Enable (debug use) → 0: RTC stalls if CPU halted, 1: RTC continues counting
5 TAOTE Timer A Output Trigger Enable (0: ADC trigger disabled, 1: enabled)
6 TAPWML Timer A Wait-on-Trigger → 0: Begins counting when enabled, 1: Waits for trigger input

Hafsa Qamar EE-324: Microcontrollers and Interfacing 38

 Edge-Time Capturing

T T
V (Volts)

time
V (Volts)

time
Measuring period in terms of number of clocks counted by the timer

Pulse width
V (Volts)

time
V (Volts)

time
Measuring pulse width in terms of number of clocks counted by the timer

Hafsa Qamar EE-324: Microcontrollers and Interfacing 39

 Edge-Count Capturing

• Timer works as a counter when TAMR bits of GPTMTAMR are configured to

capture mode and TACMR bit is cleared
GPTM Timer A Mode Register (GPTMTAMR)
Bit Name Description
0&1 TAMR Timer A Mode
2 TACMR Timer A Capture Mode (0: Edge Count, 1: Edge Time)
3 TAAMS Timer A Alternate Mode Select (0: Capture/Compare, 1: PWM mode) Bit Bit Mode
4 TACDIR Timer A Count Direction (0: Down, 1: Up) → default down count 1 0
5 TAMIE Timer A Match Interrupt Enable (0: Disabled, 1: Enabled) 0 0 Reserved
6 TAWOT Timer A Wait-on-Trigger (0: Begins counting when enabled, 1: Waits 0 1 One-shot
for trigger)
1 0 Periodic
7 TASNAPS Timer A Snap-Shot Mode (0: Disabled)
8 TAILD Timer A Interval Load Write 1 1 Capture
9 TAPWMIE Timer A PWM Interrupt Enable (0: Disabled, 1: Enabled)
10 TAMRSU Timer A Match Register Update
11 TAPLO Timer A PWM Legacy Operation

• To determine the type of edge that is counted, TnEVENT bits of GPTMCTL

register are initialized

Hafsa Qamar EE-324: Microcontrollers and Interfacing 40

 LUMS Online Course Evaluation – Mid Semester Feedback

• Scan the QR Code

• Login using your

LUMS credentials

• Provide a detailed
feedback regarding
EE324 Course

Hafsa Qamar EE-324: Microcontrollers and Interfacing 41