DEPARTMENT OF ELECTRONICS &

COMMUNICATION

Date: - __ /___ /____ ---------

Enrolment no.:-………………. Signature of Professor

Experiment No. 1

Simulation using all the modeling styles and Synthesis of all the
logic gates using VHDL

AIM:
Perform Zero Delay Simulation of all the logic gates written in behavioral,
dataflow and structural modeling style in VHDL using a Test bench. Then,
Synthesize each one of them on Xilinx 8.1 Project Navigator.

Electronics Design Automation Tools used:

i) Xilinx Project Navigator 8.1 (Includes all the steps in the design flow from
Simulation to Implementation to download onto FPGA).

Block Diagram:

A And, Nand,
Or, Nor, C
Xor, Xnor
B

Truth table:
And Gate: Or Gate:
A B Y A B Y
0 0 0 0 0 0
0 1 0 0 1 1
1 0 0 1 0 1
1 1 1 1 1 1

Nand Gate: Nor Gate:

A B Y A B Y
0 0 1 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 0

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Xor Gate: Xnor Gate:
A B Y A B Y
0 0 0 0 0 1
0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 1

Boolean Equation:

And Gate: Y = (A.B) Or Gate: Y = (A + B)

Nand Gate: Y = (A.B)‟ Nor Gate: Y = (A+B)‟
Xor Gate: Y = A.B‟ + A‟.B Xnor Gate: Y = A.B + A‟.B‟

VHDL Code (In different modeling styles):

And Gate (In Dataflow, behavioral Modeling):

library ieee;
use ieee.std_logic_1164.all;

entity andg is
port (a,b : in std_logic;
c : out std_logic
);
end andg;

architecture andg_df of andg is -- simple dataflow modeling

begin
c <= a and b;
end andg_df;

architecture andg_beh of andg is -- behavioral modeling using simple process

begin
process(a,b)
begin
c <= a and b;
end process;
end andg_beh;

Or gate(Dataflow, behavioral modeling):

library ieee;
use ieee.std_logic_1164.all;

entity org is
port (a,b : in std_logic;
c : out std_logic

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);
end org;

architecture org_df of org is -- dataflow modeling using when …. else

begin
c <= '0' when a = '0' and b = '0' else
'1' when a = '0' and b = '1' else
'1' when a = '1' and b = '0' else
'1' when a = '1' and b = '1' else
'Z';
end org_df;

architecture org_beh of org is -- behavioral modeling using if …. else

begin
process(a,b)
begin
if (a = '0' and b = '0') then
c <= '0';
elsif (a = '0' and b = '1') then
c <= '1';
elsif (a = '1' and b = '0') then
c <= '1';
elsif (a = '1' and b = '1') then
c <= '1';
end if;
end process;
end org_beh;

Nand Gate (In Dataflow, behavioral Modeling):

library ieee;
use ieee.std_logic_1164.all;

entity nandg is
port (a,b : in std_logic;
c : out std_logic
);
end nandg;

architecture nandg_df of Nandg is -- dataflow modeling using with …… select

signal sel : std_logic_vector(1 downto 0);
begin
sel <= a & b;
with sel select
c <= '1' when "00",
'1' when "01",
'1' when "10",
'0' when "11",
'Z' when others;
end nandg_df;

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architecture nandg_beh of nandg is -- behavioral modeling using case … end case
begin

process(a,b)
variable v : std_logic_vector(1 downto 0);
begin
v := a & b;
case v is
when "00" => c <= '1';
when "01" => c <= '1';
when "10" => c <= '1';
when "11" => c <= '0';
when others => c <= 'Z';
end case;
end process;
end nandg_beh;

Nor Gate (In Dataflow, behavioral Modeling):

library ieee;
use ieee.std_logic_1164.all;

entity norg is
port (a,b : in std_logic;
c : out std_logic
);
end norg;

architecture norg_df of norg is -- dataflow modeling using with …… select

signal sel : std_logic_vector(1 downto 0);
begin
sel <= a & b;
with sel select
c <= '1' when "00",
'0' when "01",
'0' when "10",
'0' when "11",
'Z' when others;
end norg_df;

architecture norg_beh of norg is -- behavioral modeling using case … end case

begin

process(a,b)
variable v : std_logic_vector(1 downto 0);
begin
v := a & b;
case v is
when "00" => c <= '1';
when "01" => c <= '0';
when "10" => c <= '0';
when "11" => c <= '0';
when others => c <= 'Z';

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 end case;
end process;
end norg_beh;

Xor gate(Dataflow, behavioral modeling):

library ieee;
use ieee.std_logic_1164.all;

entity xorg is
port (a,b : in std_logic;
c : out std_logic
);
end xorg;

architecture xorg_df of xorg is -- simple dataflow

modeling begin
c <= (a and (not b)) or ((not a) and b);
end xorg_df;

architecture xorg_df1 of xorg is -- dataflow modeling using when …. else

begin
c <= '0' when a = '0' and b = '0' else
'1' when a = '0' and b = '1' else
'1' when a = '1' and b = '0' else
'1' when a = '1' and b = '1' else
'Z';
end xorg_df1;

architecture xorg_beh of xorg is -- behavioral modeling using if …. else

begin
process (a,b)
begin
if (a = '0' and b = '0') then
c <= '0';
elsif (a = '0' and b = '1') then
c <= '1';
elsif (a = '1' and b = '0') then
c <= '1';
elsif (a = '1' and b = '1') then
c <= '0';
end if;
end process;
end xorg_beh;

Xnor Gate (In Dataflow, behavioral Modeling):

library ieee;
use ieee.std_logic_1164.all;

entity Xnorg is
port (a,b : in std_logic;

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 c : out std_logic
);
end Xnorg;

architecture Xnorg_df of Xnorg is -- dataflow modeling using with …… select

signal sel : std_logic_vector(1 downto 0);
begin
sel <= a & b;
with sel select
c <= „1‟ when “00”,
„0‟ when “01”,
„0‟ when “10”,
„1‟ when “11”,
„Z‟ when others;
end Xnorg_df;

architecture Xnorg_beh of Xnorg is -- behavioral modeling using case … end case

begin

process(a,b)
variable v : std_logic_vector(1 downto 0);
begin
v := a & b;
case v is
when “00” => c <= „1‟;
when “01” => c <= „0‟;
when “10” => c <= „0‟;
when “11” => c <= „1‟;
when others => c <= „Z‟;
end case;
end process;
end Xnorg_beh;

Test Bench (Applicable to all the logic gates):

library ieee;
use ieee.std_logic_1164.all;

entity nandg_tst is -- test bench for a nand gate.

end nandg_tst;

architecture nandg_tst_a of nandg_tst is

component Nandg
port (a,b : in std_logic;
c : out std_logic
);
end component;

signal a_i ,b_i, c_i : std_logic;

begin

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nandg_i : nandg port map ( a => a_i,
b => b_i,
c => c_i
);
process
begin
a_i <= '0';
b_i <= '0';
wait for 100 ns;
a_i <= '0';
b_i <= '1';
wait for 100 ns;
a_i <= '1';
b_i <= '0';
wait for 100 ns;
a_i <= '1';
b_i <= '1';
wait for 100 ns;
end process;
end nandg_tst_a;

Simulation Waveform:
Nand Gate:

Nor Gate:

And Gate:

Or Gate:

Xor Gate:

Xnor Gate:

Simulation Waveform:

Synthesis:

EDA Tool Name: Xilinx Project Navigator – 8.1

Synthesis Report (Xilinx project Navigator):

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 DEPARTMENT OF ELECTRONICS &
COMMUNICATION

Date: - __ /___ /____ ---------

Enrolment no.:-………………. Signature of Professor

Experiment No. 2

Simulation using all the modeling styles and Synthesis of 1-bit half
adder and 1-bit Full adder using VHDL

AIM:
Perform Zero Delay Simulation of 1-bit half adder and 1-bit Full adder written in
behavioral, dataflow and structural modeling style in VHDL using a Test bench. Then,
Synthesize each one of them on Xilinx 8.1 Project Navigator.

Electronics Design Automation Tools used:

i) Xilinx Project Navigator 8.1 (Includes all the steps in the design flow from
Simulation to Implementation to download onto FPGA).

Block Diagram:
1-bit Half Adder:

A Half Adder Sum

(1-bit)
B Carry

1-bit Full Adder:

A
Full Adder Sum
B (1-bit) Cout
Cin
Truth table:
Half Adder:
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

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 Full Adder:
A B Cin Sum Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Boolean Equation:

Half Adder:
Sum = A B
Carry = A.B
Full Adder:
Sum = A B Cin
Cout = A.B + [Link] + [Link]

VHDL Code:
Half Adder (Using dataflow, Behavioral Modeling):

library ieee;
use ieee.std_logic_1164.all;

entity ha_1b is
port ( a, b : in std_logic;
sum, carry : out std_logic
);
end ha_1b;

architecture ha_1b_df of ha_1b is -- dataflow modeling using with select

signal s : std_logic_vector(1 downto 0); begin

s <= a & b;
with s select
sum <= '0' when "00",
'1' when "01",
'1' when "10",
'0' when "11",
'Z' when others;
with s select
carry <= '0' when "00",
'0' when "01",

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 '0' when "10",
'1' when "11",
'0' when others;
end ha_1b_df;

architecture ha_1b_df1 of ha_1b is -- simple dataflow modeling using Boolean equation

begin
sum <= a xor b;
carry <= a and b;
end ha_1b_df1;

architecture ha_1b_beh of ha_1b is -- behavioral modeling using if …. else

begin
process (a,b)
begin
if (a = '0' and b = '0') then
sum <= '0';
carry <= '0';
elsif (a = '0' and b = '1') then
sum <= '1';
carry <= '0';
elsif (a = '1' and b = '0') then
sum <= '1';
carry <= '0';
elsif (a = '1' and b = '1') then
sum <= '0';
carry <= '1';
end if;
end process;
end ha_1b_beh;

Full Adder (Using dataflow, Behavioral Modeling, Structural Modeling):

library ieee;
use ieee.std_logic_1164.all;

entity fa_1b is
port ( a, b, cin : in std_logic;
sum, cout : out std_logic
);
end fa_1b;

architecture fa_1b_df1 of fa_1b is -- simple dataflow modeling using Boolean equation

begin

sum <= a xor b xor cin;

cout <= (a and b) or (a and cin) or (b and cin);
end fa_1b_df1;

architecture fa_1b_beh of fa_1b is -- behavioral modeling using case … end case

begin

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 process (a,b)
variable v : std_logic_vector(2 downto 0);
begin
v := a & b & cin;
case v is
when "000" =>
sum <= '0';
cout <= '0';
when "001" =>
sum <= '1';
cout <= '0';
when "010" =>
sum <= '1';
cout <= '0';
when "011" =>
sum <= '0';
cout <= '1';
when "100" =>
sum <= '1';
cout <= '0';
when "101" =>
sum <= '0';
cout <= '1';
when "110" =>
sum <= '0';
cout <= '1';
when "111" =>
sum <= '1';
cout <= '1';
when others =>
sum <= 'Z';
cout <= 'Z';
end case;
end process;
end fa_1b_beh;

architecture fa_1b_str of fa_1b is

component ha_1b
port (a,b : in std_logic;
sum, carry: out std_logic
);
end component;
component org
port (a,b : in std_logic;
c : out std_logic
);
end component;

signal s1,s2,s3 : std_logic;

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begin
ha_1b_i1 : ha_1b port map ( a => a ,
b => b ,
sum => s1 ,
carry => s2
);

ha_1b_i2 : ha_1b port map ( a => s1 ,

b => cin ,
sum => sum ,
carry => s3
);

Org_i : org port map ( a => s3,

b => s2,
c => cout
);
end fa_1b_str;

architecture fa_1b_mixed of fa_1b is

component ha_1b
port (a,b : in std_logic;
sum, carry: out std_logic
);
end component;
signal s1,s2,s3 : std_logic;

begin

ha_1b_i : ha_1b port map ( a => a , --structural modeling

b => b ,
sum => s1 ,
carry => s2
);

process (s1,cin) -- behavioral modeling

begin
sum <= s1 xor cin;
s3 <= s1 and cin;
end process;

cout <= s2 or s3; -- dataflow modeling

end fa_1b_mixed;

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 VHDL Test Bench:

Half Adder:

library ieee;
use ieee.std_logic_1164.all;
entity ha_1b_tst is -- test bench for a 1-bit Half adder.
end ha_1b_tst;

architecture ha_1b_tst_a of ha_1b_tst is

component ha_1b
port (a, b : in std_logic;
sum, carry : out std_logic
);
end component;

signal a_i ,b_i, sum_i,carry_i : std_logic;

begin
nandg_i : ha_1b port map ( a => a_i,
b => b_i,
sum => sum_i,
carry => carry_i
);
process
begin
a_i <= '0';
b_i <= '0';
wait for 100 ns;
a_i <= '0';
b_i <= '1';
wait for 100 ns;
a_i <= '1';
b_i <= '0';
wait for 100 ns;
a_i <= '1';
b_i <= '1';
wait for 100 ns;
end process;

end ha_1b_tst_a;

Full Adder:

library ieee;
use ieee.std_logic_1164.all;

entity fa_1b_tst is -- test bench for a 1-bit Full adder

end fa_1b_tst;

architecture fa_1b_tst_a of fa_1b_tst is

component fa_1b
port ( a, b, cin: in std_logic;
sum, cout : out std_logic
);
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 end component;

signal a_i ,b_i, cin_i, sum_i,carry_i : std_logic;

begin

fa_1b_i : fa_1b port map ( a => a_i,

b => b_i,
cin => cin_i,
sum => sum_i,
cout => carry_i
);

process
begin
a_i <= '0';
b_i <= '0';
cin_i <= '0';
wait for 100 ns;
a_i <= '0';
b_i <= '0';
cin_i <= '1';
wait for 100 ns;
a_i <= '0';
b_i <= '1';
cin_i <= '0';
wait for 100 ns;
a_i <= '0';
b_i <= '1';
cin_i <= '1';
wait for 100 ns;
a_i <= '1';
b_i <= '0';
cin_i <= '0';
wait for 100 ns;
a_i <= '1';
b_i <= '0';
cin_i <= '1';
wait for 100 ns;
a_i <= '1';
b_i <= '1';
cin_i <= '0';
wait for 100 ns;
a_i <= '1';
b_i <= '1';
cin_i <= '1';
wait for 100 ns;
end process;

end fa_1b_tst_a;

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 Simulation Waveform:
Half Adder:

Full Adder:

Synthesis:

Half Adder:

EDA Tool Name: Xilinx Project Navigator – 8.1

Full Adder:

EDA Tool Name: FPGA Advantage 3.1 – Leonardo spectrum

EDA Tool Name: Xilinx Project Navigator – 8.1

Synthesis Report (Xilinx Project Navigator):

Full Adder:

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 DEPARTMENT OF ELECTRONICS &
COMMUNICATION

Date: - __ /___ /____ ---------

Enrolment no.:-………………. Signature of Professor
Experiment No. 3

Simulation using all the modeling styles and Synthesis of 2:1

Multiplexer and 4:1 Multiplexer using VHDL

Aim:
Perform Zero Delay Simulation of 2:1 Multiplexer and 4:1 Multiplexer written in
behavioral, dataflow and structural modeling style in VHDL using a Test bench. Then,
Synthesize each one of them on Xilinx 8.1 Project Navigator.

Electronics Design Automation Tools used:

i) Xilinx Project Navigator 8.1 (Includes all the steps in the design flow from
Simulation to Implementation to download onto FPGA).

Block Diagram:

2:1 Multiplexer:

A
2:1
Y
B Multiplexer

4:1 Multiplexer:
A
4:1
B
Multiplexer Y
C

S1 S0

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 Truth table:
2:1 Multiplexer:

S A B Y
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1

4:1 Multiplexer:

A B Y
0 0 A
0 1 B
1 0 C
1 1 D

Boolean Equation:
2:1 Multiplexer:
Y = A.S‟ + B.S
4:1 Multiplexer:
Y = A.S1‟.S0‟ + B.S1‟.S0 + C.S1.S0‟ + D.S1.S0

VHDL Code:
2:1 Multiplexer ( in dataflow and behavioral modeling style) :

library ieee;
use ieee.std_logic_1164.all;

entity mux21 is
port ( a,b,s : in std_logic;
y : out std_logic
);
end mux21;

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architecture mux21_df of mux21 is -- simple dataflow modeling using Boolean
equation

begin
y <= (((not s) and a) or (s and b));
end mux21_df;

architecture mux21_beh of mux21 is -- behavioral modeling using case … end case

begin
process (a,b,s)
begin
case s is
when '0' =>
y <= a;
when '1' =>
y <= b;
when others =>
y <= 'Z';
end case;
end process;
end mux21_beh;

architecture mux21_df of mux21 is -- simple dataflow modeling using Boolean

begin -- equation
y <= a when s = '0' else
b;
end mux21_df;

configuration mux21_c of mux21 is

for mux21_beh
end for;
end mux21_c;

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4:1 Multiplexer( in behavioral, dataflow and structural modeling styles):

library ieee;
use ieee.std_logic_1164.all;

entity mux41 is
port ( a,b,c,d,s1,s0 : in std_logic;
y : out std_logic);
end mux41;

architecture mux41_beh of mux41 is -- simple behavioral modeling using Boolean

equation
begin
process (a,b,c,d,s1,s0)
begin
y <= ((not s1) and (not s1) and a) or ((not s1) and s0 and b) or (s1 and (not s0)
and c) or (s1 and s0 and d);
end process;
end mux41_beh;

architecture mux41_beh1 of mux41 is -- behavioral modeling using if …elsif …end if;

begin

process (a,b,c,d,s1,s0)
begin
if (s1 = '0' and s0 = '0') then
y <= a;
elsif (s1 = '0' and s0 = '1') then
y <= b;
elsif (s1 = '1' and s0 = '0') then
y <= c;
elsif (s1 = '1' and s0 = '1') then
y <= d;
else
y<= 'Z';
end if;
end process;
end mux41_beh1;

architecture mux41_df of mux41 is -- dataflow modeling using with … select

signal s : std_logic_vector (1 downto 0);
begin
s <= s1 & s0;
with s select
y <= a when "00",
b when "01",
c when "10",
d when "11",
'Z' when others;
end mux41_df;

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architecture mux41_df1 of mux41 is -- dataflow modeling using when ….. else
signal s : std_logic_vector (1 downto 0);
begin
s <= s1 & s0;
y <= a when s = "00" else
b when s = "01" else
c when s = "10" else
d when s = "11" else
'Z';
end mux41_df1;

architecture mux41_str of mux41 is

component mux21
port ( a,b,s : in std_logic;
y : out std_logic
);
end component;
signal con1, con2 : std_logic;
begin

mux21_i1 : mux21 port map ( a => a ,

b => b ,
s => s1 ,
y => con1
);

mux21_i2 : mux21 port map ( a => c ,

b => d ,
s => s1 ,
y => con2
);

mux21_i3 : mux21 port map ( a => con1 ,

b => con2 ,
s => s0 ,
y => y
);
end mux41_str;

VHDL Test Bench:

2:1 Multiplexer:

library ieee;
use ieee.std_logic_1164.all;

entity mux21_tst is
end mux21_tst;

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 architecture mux21_tst_a of mux21_tst is
component mux21
port (a,b,s : in std_logic;
y : out std_logic
);
End component;
signal a,b,s,y : std_logic;
begin

mux21_i : mux21 port map ( a => a,

b => b,
s => s,
y => y
);
process
begin
a <= '0';
b <= '1';
s <= '0';
wait for 100 ns;
s <= '1';
wait for 100 ns;
end process;
end mux21_tst_a;

4: 1 Multiplexer:

library ieee;
use ieee.std_logic_1164.all;

entity mux41_tst is
end mux41_tst;

architecture mux41_tst_a of mux41_tst is

component mux41
port ( a,b,c,d,s1,s0 : in std_logic;
y : out std_logic
);
end component;
signal a,b,c,d,s1,s0,y : std_logic;
begin
mux41_tst_i : mux41 port map ( a, b, c, d, s1, s0, y ); -- positional association

process
begin
a <= '0';
b <= '1';
c <= '1';
d <= '0';
s1 <= '0';

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 s0 <= '0';
wait for 100 ns;
s1 <= '0';
s0 <= '1';
wait for 100 ns;

s1 <= '1';
s0 <= '0';
wait for 100 ns;
s1 <= '1';
s0 <= '1';
wait for 100 ns;
end process;
end mux41_tst_a;

Simulation Waveform:

Synthesis:
2 :1 Multiplexer:

EDA Tool Name: Xilinx Project Navigator – 8.1

4 :1 Multiplexer:

EDA Tool Name: Xilinx Project Navigator – 8.1

Synthesis Report (Xilinx project Navigator):

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 DEPARTMENT OF ELECTRONICS &
COMMUNICATION

Date: - __ /___ /____ ---------

Enrolment no.:-………………. Signature of Professor

Experiement No. 4

Simulation and Synthesis of 1:4 Demultiplexer using VHDL

Aim:
Perform Zero Delay Simulation 1:4 Demultiplexer in VHDL using a Test bench. Then,
Synthesize on Xilinx 8.1 Project Navigator.

Electronics Design Automation Tools used:

i) Xilinx Project Navigator 8.1 (Includes all the steps in the design flow from
Simulation to Implementation to download onto FPGA).

Block Diagram:

1:4
A Demultiplexer Y

S
Truth Table:
Input Select Output
A 00 Y(0)
B 01 Y(1)
C 10 Y(2)
D 11 Y(3)

Boolean Equation:
Y(3) = A.S.(1)‟.S(0)‟
Y(2) = B.S.(1)‟.S(0)
Y(1) = C.S.(1).S(0)‟
Y(0) = D.S.(1).S(0)

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 VHDL Code:

library ieee;
use ieee.std_logic_1164.all;

entity demux14 is
port ( a : in std_logic;
s : in std_logic_vector(1 downto 0);
y : out std_logic_vector(3 downto 0)
);
end demux14;

architecture demux14_df of demux14 is -- dataflow modeling using when …. else

begin
y <= ( a & '0' & '0' & '0') when s = "00" else
('0' & a & '0' & '0') when s = "01" else
('0' & '0' & a & '0') when s = "10" else
('0' & '0' & '0' & a ) when s = "11" else
"0000";
end demux14_df;

architecture demux14_beh of demux14 is -- behavioral modeling using case ….. end case
begin
process(a,s)
begin
case s is
when "00" => y <= ( a & '0' & '0' & '0');
when "01" => y <= ('0' & a & '0' & '0');
when "10" => y <= ('0' & '0' & a & '0');
when "11" => y <= ('0' & '0' & '0' & a );
when others => y <= "0000";
end case;
end process;
end demux14_beh;

VHDL test bench:

library ieee;
use ieee.std_logic_1164.all;

entity demux14_tst is
end demux14_tst;

architecture demux14_tst_a of demux14_tst is

component demux14
port ( a : in std_logic;
s : in std_logic_vector(1 downto 0);
y : out std_logic_vector(3 downto 0)

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 );
end component;
signal a : std_logic;
signal s : std_logic_vector(1 downto 0);
signal y : std_logic_vector(3 downto 0);
begin
demux14_tst_i : demux14 port map (a,s,y); -- positional association
process
begin
a <= '1';
s <= "00";
wait for 100 ns;
s <= "01";
wait for 100 ns;
s <= "10";
wait for 100 ns;
s <= "11";
wait for 100 ns;
end process;
end demux14_tst_a;

Simulation Waveform:

Synthesis:

EDA Tool Name: Xilinx Project Navigator – 8.1

Synthesis Report (Xilinx project Navigator):

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 DEPARTMENT OF ELECTRONICS &
COMMUNICATION

Date: - __ /___ /____ ---------

Enrolment no.:-………………. Signature of Professor
Experiement No. 5

Simulation and Synthesis of 2:4 Decoder using VHDL

Aim:
Perform Zero Delay Simulation 2:4 Decoder in VHDL using a Test bench. Then, Synthesize on
Xilinx 8.1 Project Navigator.

Electronics Design Automation Tools used:

i) Xilinx Project Navigator 8.1 (Includes all the steps in the design flow from Simulation to
Implementation to download onto FPGA).

Block Diagram:

2:4
A Decoder Y

Truth Table:

A Y
00 0001
01 0010
10 0100
11 1000

Boolean Equation:

Y(0) = A(1)‟. A(0)‟

Y(1) = A(1)‟.A(0)
Y(2) = A(1).A(0)‟
Y(3) = A(1). A(0)

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 VHDL Code:

library ieee;
use ieee.std_logic_1164.all;

entity decod24 is
port ( a : in std_logic_vector(1 downto 0);
y : out std_logic_vector(3 downto 0)
);
end decod24;

architecture decod24_beh of decod24 is -- behavioral modeling using case … end case begin

process(a)
begin
case a is
when "00" => y <= "0001";
when "01" => y <= "0010";
when "10" => y <= "0100";
when "11" => y <= "1000";
when others => y <= "0000";
end case;
end process;
end decod24_beh;
VHDL Test Bench:
library ieee;
use ieee.std_logic_1164.all;

entity decod24_tst is
end decod24_tst;

architecture decod24_tst_a of decod24_tst is

component decod24
port ( a : in std_logic_vector(1 downto 0);
y : out std_logic_vector(3 downto 0)
);
end component;
signal a1 : std_logic_vector(1 downto 0);
signal y1 : std_logic_vector(3 downto 0);

begin

decod24_tst_i : decod24 port map (a1,y1);

process
begin
a1 <= "00";
wait for 100 ns;

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 a1 <= "01";
wait for 100 ns;
a1 <= "10";
wait for 100 ns;
a1 <= "11";
wait for 100 ns;
end process;
end decod24_tst_a;
Simulation Waveform:

Synthesis:

EDA Tool Name: Xilinx Project Navigator – 8.1

Synthesis Report (Xilinx project Navigator):

Department Electronics & Communication

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 DEPARTMENT OF ELECTRONICS &
COMMUNICATION

Date: - __ /___ /____ ---------

Enrolment no.:-………………. Signature of Professor

Experiement No. 6

Simulation and Synthesis of 4:2 Encoder using VHDL

Aim:
Perform Zero Delay Simulation 4:2 Encoder in VHDL using a Test bench. Then, Synthesize on
Xilinx 8.1 Project Navigator.

Electronics Design Automation Tools used:

i) Xilinx Project Navigator 8.1 (Includes all the steps in the design flow from Simulation to
Implementation to download onto FPGA).

Block Diagram:

A 4:2 Y
Encoder

Truth Table:

A Y
1000 00
0100 01
0010 10
0001 11

Boolean Equation:

Y(1) = A(1) + A(0)

Y(0) = A(2) + A(0)

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 VHDL Code:
library ieee;
use ieee.std_logic_1164.all;

entity encod42 is
port (a : in std_logic_vector(3 downto 0);
y : out std_logic_vector(1 downto 0)
);
end encod42;

architecture encod42_df of encod42 is

begin
with a select
y <= "00" when "0001",
"01" when "0010",
"10" when "0100",
"11" when "1000",
"00" when others;
end encod42_df;

VHDL Test Bench:

library ieee;
use ieee.std_logic_1164.all;

entity encod42_tst is
end encod42_tst;

architecture encod42_tst_a of encod42_tst is

component encod42
port (a : in std_logic_vector(3 downto 0);
y : out std_logic_vector(1 downto 0)
);
end component;
signal a1 : std_logic_vector(3 downto 0);
signal y1 : std_logic_vector(1 downto 0);

begin

encod42_i : encod42 port map (a1,y1);

process
begin
a1 <= "0001";
wait for 100 ns;
a1 <= "0010";
wait for 100 ns;
a1 <= "0100";
wait for 100 ns;
a1 <= "1000";
wait for 100 ns;
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end process;
end encod42_tst_a;

Simulation Waveform:

Synthesis:

EDA Tool Name: Xilinx Project Navigator – 8.1

Synthesis Report (Xilinx project Navigator):

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 DEPARTMENT OF ELECTRONICS &
COMMUNICATION
Date: - __ /___ /____ ---------
Enrolment no.:-………………. Signature of Professor
Experiement No. 7

Simulation and Synthesis of 4:2 Priority Encoder using VHDL

Aim:
Perform Zero Delay Simulation 4:2 Priority Encoder in VHDL using a Test bench.
Then, Synthesize on Xilinx 8.1 Project Navigator.

Electronics Design Automation Tools used:

i) Xilinx Project Navigator 8.1 (Includes all the steps in the design flow from Simulation to
Implementation to download onto FPGA).

Block Diagram:

4:2 Y
A Priority
Encoder

Truth Table:

A(3) A(2) A(1) A(0) Y(1) Y(0)

0 0 0 1 0 0
0 0 1 X 0 1
0 1 X X 1 0
1 X X X 1 1

A(3) A(2) A(1) A(0) Y(1) Y(0)

0 0 0 1 0 0
0 0 1 0 0 1
0 0 1 1 0 1
0 1 0 0 1 0
0 1 0 1 1 0
0 1 1 0 1 0
0 1 1 1 1 0
1 0 0 0 1 0
1 0 0 1 1 1
1 0 1 0 1 1

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 1 0 1 1 1 1
1 1 0 0 1 1
1 1 0 1 1 1
1 1 1 0 1 1
1 1 1 1 1 1

Boolean Equation:
Y(1) = A(3) + A(2)
Y (0) = A(2)‟.A(1) + A(3).A(2) + A(3).A(0)

VHDL Code:
library ieee;
use ieee.std_logic_1164.all;

entity pri_encod42 is
port (a : in std_logic_vector(3 downto 0);
y : out std_logic_vector(1 downto 0);
valid : out std_logic
);
end pri_encod42;

architecture pri_encod42_beh of pri_encod42 is

begin
process(a)
begin
if (a(3) = '1') then
y <= "11";
valid <= '1';
elsif (a(2) = '1') then
y <= "10";
valid <= '1';
elsif (a(1) = '1') then
y <= "01";
valid <= '1';
elsif (a(0) = '1') then
y <= "00";
valid <= '1';
else
y <= "XX";
valid <= '0';
end if;
end process;
end pri_encod42_beh;

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 VHDL Test Bench:

library ieee;
use ieee.std_logic_1164.all;

entity pri_encod42_tst is
end pri_encod42_tst;

architecture pri_encod42_tst_a of pri_encod42 is

component pri_encod42
port (a : in std_logic_vector(3 downto 0);
y : out std_logic_vector(1 downto 0)
);
end component;
signal a : std_logic_vector(3 downto 0);
signal y : std_logic_vector3 downto 0);
begin
pri_encod42_i : pri_encod42 port map (a,y);
process
begin
a <= “0000”
wait for 100 ns;
a <= “0001”;
wait for 100 ns;
a <= “0010”;
wait for 100 ns;
a <= “0011”;
wait for 100 ns;
a <= “0100”;
wait for 100 ns;
a <= “0101”;
wait for 100 ns;
a <= “0110”;
wait for 100 ns;
a <= “0111”;
wait for 100 ns;
a <= “1000”;
wait for 100 ns;
a <= “1000”;
wait for 100 ns;
a <= “1001”;
wait for 100 ns;
a <= “1010”;
wait for 100 ns;
a <= “1011”;
wait for 100 ns;
a <= “1100”;

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 wait for 100 ns;

a <= “1101”;
wait for 100 ns;
a <= “1110”;
wait for 100 ns;
a <= “1111”;
wait for 100 ns;
end process;
end pri_encod42_tst_a;

Simulation Waveform:

Synthesis:

EDA Tool Name: Xilinx Project Navigator – 8.1

Synthesis Report (Xilinx project Navigator):

Department Electronics & Communication

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 DEPARTMENT OF ELECTRONICS &
COMMUNICATION
Date: - __ /___ /____ ---------
Enrolment no.:-………………. Signature of Professor

Experiement No. 8

Simulation and Synthesis of magnitude comparator 1-bit using VHDL

Aim:
Perform Zero Delay Simulation of magnitude comparator 1-bit in VHDL using a Test bench.
Then, Synthesize on Xilinx 8.1 Project Navigator.

Electronics Design Automation Tools used:

i) Xilinx Project Navigator 8.1 (Includes all the steps in the design flow from Simulation to
Implementation to download onto FPGA).

Block Diagram:

AgtB
A Magnitude
B Comparator AltB
1-bit AeqB

Truth Table:

A B AgtB AltB AeqB

0 0 0 0 1
0 1 0 1 0
1 0 1 0 0
1 1 0 0 1

Boolean Equation:
AgtB = A.B‟
AltB = A‟.B
AeqB = A‟.B‟ + A.B

VHDL Code:
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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;

use ieee.std_logic_unsigned.all;

entity magcomp1 is
port (a,b : in std_logic;
agtb, aeqb, altb : out boolean
);
end magcomp1;

architecture magcomp1_df of magcomp1 is

begin
agtb <= a > b;
altb <= a < b;
aeqb <= (a = b);
end magcomp1_df;

VHDL Test Bench:

library ieee;
use ieee.std_logic_1164.all;

entity magcomp1_tst is
end magcomp1_tst;

architecture magcomp1_tst_a of magcomp1_tst is

component magcomp1
port (a,b : in std_logic;
agtb, aeqb, altb : out boolean
);
end component;
signal a,b : std_logic;
signal agtb, aeqb, altb : boolean;
begin
magcomp1_i : magcomp1 port map (a,b, agtb, aeqb, altb);
process
begin
a <= '0';
b <= '0';
wait for 100 ns;
a <= '0';
b <= '1';
wait for 100 ns;
a <= '1';
b <= '0';
wait for 100 ns;
a <= '1';
b <= '1';
wait for 100 ns;

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end process;
end magcomp1_tst_a;
Simulation Waveform:

Synthesis:

EDA Tool Name: Xilinx Project Navigator – 8.1

Synthesis Report (Xilinx project Navigator):

Department Electronics & Communication

38
 DEPARTMENT OF ELECTRONICS
& COMMUNICATION
Date: - __ /___ /____ ---------
Enrolment no.:-………………. Signature of Professor

Experiement No. 9

Simulation and Synthesis of D latch and D flip flop using VHDL

Aim:
Perform Zero Delay Simulation of d latch and d flip flop in VHDL using a Test bench.
Then, Synthesize on Xilinx 8.1 Project Navigator.

Electronics Design Automation Tools used:

i) Xilinx Project Navigator 8.1 (Includes all the steps in the design flow from Simulation to
Implementation to download onto FPGA).

VHDL Code:
D-latch:

library ieee;
use ieee.std_logic_1164.all;

entity dlatch is
port (d,en,reset : in std_logic;
q : out std_logic
);
end dlatch;

architecture dlatch_beh of dlatch is

signal s : std_logic;
begin
process(d,en,reset)
begin
if (reset = „1‟) then
s <=‟0‟;
elsif (en = „1‟) then
s <= d;
else
s <= s;
end if;
q <= s;
end process;
end dlatch_beh;

architecture dlatch_beh1 of dlatch is

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 begin

variable s : std_logic;
begin
if (reset = „1‟) then
s :=‟0‟;
elsif (en = „1‟) then
s := d;
else
s := s;
end if;
q <= s;
end process;
end dlatch_beh1;

architecture dlatch_beh2 of dlatch is

begin
process (d,en,reset)
begin
if (reset = „1‟) then
q <= ‟0‟;
elsif (en = „1‟) then
q <= d;
end if;
end process;
end dlatch_beh2;

D-flip flop with asynchronous and synchronous reset:

library ieee;
use ieee.std_logic_1164.all;

entity dff is
port (d,clk,reset : in std_logic;
q : out std_logic
);
end dff;

architecture dff_asyncrst_a of dff is

begin
process(clk,reset)
begin
if (reset = '1') then
q <= '0';
elsif( clk'event and clk = '1') then
q <= d;
end if;
end process;
end dff_asyncrst_a;

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architecture dff_syncrst_a of dff is
begin
process(clk)
begin
if( clk'event and clk = '1') then
if (reset = '1') then
q <= '0';
else
q <= d;
end if;
end if;
end process;
end dff_syncrst_a;

VHDL Test Bench:

Test Bench of D-latch:

library ieee;
use ieee.std_logic_1164.all;

entity dlatch_tst is
end dlatch_tst;

architecture dlatch_tst_a of dlatch_tst is

component dlatch
port (d,en,reset : in std_logic;
q : out std_logic
);
end component;
signal d,en,reset,q : std_logic;
begin
dlatch_i : dlatch port map (d,en,reset,q);

process
begin
reset <= '1';
en <= '0';
d <= '0';
wait for 200 ns;
reset <= '0';
en <= '1';
d <= '1';
wait for 50 ns;
d <= '0';
wait for 30 ns;
d <= '1';
wait for 10 ns;
d <= '0';
wait for 10 ns;
en <= '0';

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wait for 100 ns;
en <= '1';
d <= '1';
wait for 50 ns;
end process;
end dlatch_tst_a;

Test Bench of D flip flop asynchronous/synchronous reset:

library ieee;
use ieee.std_logic_1164.all;
entity dff_tst is
end dff_tst;

architecture dff_tst_a of dff_tst is

component dff
port (d,clk,reset : in std_logic;
q : out std_logic
);
end component;
signal d,reset,q : std_logic;
signal clk : std_logic := „1‟;

begin
dff_i : dff port map ( d,clk,reset,q);

clk <= not clk after 50 ns;

process
begin
reset <= „1‟;
d <= „0‟;
wait for 200 ns;
reset <= „0‟;
d <= „1‟;
wait for 100 ns;
d <= „0‟;
wait for 100 ns;
d <= „1‟;
wait for 100 ns;
d <= „0‟;
end process;
end dff_tst_a;
Simulation Waveform:
Synthesis:

EDA Tool Name: Xilinx Project Navigator – 8.1

Synthesis Report (Xilinx project Navigator):

Department Electronics & Communication
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 DEPARTMENT OF ELECTRONICS &
COMMUNICATION

Date: - __ /___ /____ ---------

Enrolment no.:-………………. Signature of Professor
Experiement No. 10

Simulation and Synthesis of JK, T Flip Flop using VHDL

Aim:
Perform Zero Delay Simulation of JK, T, Flip flop in VHDL using a Test bench. Then,
Synthesize on Xilinx 8.1 Project Navigator.

Electronics Design Automation Tools used:

i) Xilinx Project Navigator 8.1 (Includes all the steps in the design flow from Simulation to
Implementation to download onto FPGA).

VHDL Code:
JK-flip flop:

library ieee;
use ieee.std_logic_1164.all;

entity JKff is
port (j,k,clk,reset : in std_logic;
q : out std_logic
);
end JKff;

architecture JKff_beh of JKff is

signal s : std_logic;
begin
process(clk,reset)
begin
if (reset = '1') then
s <= '0';
elsif (clk'event and clk = '1' ) then
if ( j = '0' and k = '0') then
s <= s;
elsif ( j = '0' and k = '1') then
s <= '0';
elsif ( j = '1' and k = '0') then
s <= '1';
elsif ( j = '1' and k = '1') then
s <= not s;
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 end if;
end if;
end process;
end JKff_beh;

T-flip flop:

library ieee;
use ieee.std_logic_1164.all;

entity tff is
port (t,clk,reset : in std_logic;
q : out std_logic
);
end tff;

architecture tff_beh of tff is

signal s : std_logic;
begin
process(clk,reset)
begin
if (reset = '1') then
s <= '0';
elsif (clk'event and clk = '1' ) then
if ( t = '1') then
s <= not s;
else
s <= s;
end if;
q <= s;
end if;
end process;
end tff_beh;

VHDL Test Bench:

Test Bench of JK flip flop:

library ieee;
use ieee.std_logic_1164.all;

entity JKff_tst is
end JKff_tst;

architecture JKff_tst_a of JKff_tst is

component JKff
port (j,k,clk,reset : in std_logic;

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 q : out std_logic
);
end component;
signal j,k,reset,q : std_logic;
signal clk : std_logic := '1';
begin
JKff_i : JKff port map (j,k,clk,reset,q);

clk <= not clk after 50 ns;

process
begin
reset <= '1';
j <= '0';
k <= '0';
wait for 200 ns;
reset <= '0';
j <= '0';
k <= '1';
wait for 100 ns;
j <= '1';
k <= '0';
wait for 100 ns;
j <= '1';
k <= '1';
wait for 100 ns;
end process;
end jkff_tst_a;

Test Bench of T flip flop:

library ieee;
use ieee.std_logic_1164.all;

entity tff_tst is
end tff_tst;

architecture tff_tst_a of tff_tst is

component tff
port (t,clk,reset : in std_logic;
q : out std_logic
);
end component;
signal t,reset,q : std_logic;
signal clk : std_logic := '1';
begin
tff_i : tff port map ( t,clk,reset,q);

clk <= not clk after 50 ns;

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process
begin
reset <= '1';
t <= '0';
wait for 200 ns;
reset <= '0';
t <= '1';
wait for 100 ns;
t <= '0';
wait for 100 ns;
t <= '1';
wait for 100 ns;
t <= '0';
end process;
end tff_tst_a;

Simulation Waveform:

Synthesis:

EDA Tool Name: Xilinx Project Navigator – 8.1

Synthesis Report (Xilinx project Navigator):

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