RF2513

11 UHF TRANSMITTER

Typical Applications
• Single- or Dual-Channel LO Source • 433/868/915MHz ISM Band Systems
• FM/FSK Transmitter • Wireless Security Systems
• Wireless Data Transmitters

Product Description 0.157

0.0098
0.150
0.0040
The RF2513 is a monolithic integrated circuit intended for
use as a low-cost frequency synthesizer and transmitter. 1

The device is provided in a 24 pin SSOP package and is 0.012

0.008
designed to provide a phased locked frequency source 0.344
0.337
for use in local oscillator or transmitter applications. The
chip can be used in FM or FSK applications in the U.S. 0.025
915MHz ISM band and European 433MHz or 868MHz
ISM band. The integrated VCO, dual-modulus/dual-divide 0.0688
0.2440 0.0532
(128/129 or 64/65) prescaler, and reference oscillator 0.2284
require only the addition of an external crystal to provide 8°MAX
0°MIN
a complete phase-locked oscillator. A second reference
oscillator is available to support two channel applications.
0.050 0.0098
0.016 0.0075

Optimum Technology Matching® Applied Package Style: SSOP-24

ü Si BJT GaAs HBT GaAs MESFET
11
Si Bi-CMOS SiGe HBT Si CMOS Features
• Fully Integrated PLL Circuit

TRANSCEIVERS
VCO TUNE

• 10mW Output Power at 433MHz

LOOP FLT
RESNTR+
RESNTR-
LVL ADJ

OSC B1

OSC B2
VREF P
MOD IN

OSC E

• 2.7V to 5.0V Supply Voltage

7 16 18 20 22 23 13 3 2 1
• Low Current and Power Down Capability
Gain
Control
Phase Ref. • 300MHz to 1000MHz Frequency Range
Detector & Select 24 OSC SEL
TX OUT 8 Charge Pump
12 PRESCL OUT
• Narrowband and Wideband FM
Prescaler 14 MOD CTRL
128/129 or
64/65 15 DIV CTRL

Ordering Information
RF2513 UHF Transmitter
RF2513 PCBA-L Fully Assembled Evaluation Board, 433MHz
RF2513 PCBA-M Fully Assembled Evaluation Board, 868MHz
RF2513 PCBA-H Fully Assembled Evaluation Board, 915MHz

Functional Block Diagram RF Micro Devices, Inc. Tel (336) 664 1233
7625 Thorndike Road Fax (336) 664 0454
Greensboro, NC 27409, USA [Link]

Rev B8 010509 11-23

 RF2513
Absolute Maximum Ratings
Parameter Rating Unit
Supply Voltage -0.5 to +5.5 VDC Caution! ESD sensitive device.
Power Down Voltage (VPD) -0.5 to VCC V
Operating Ambient Temperature -40 to +85 °C RF Micro Devices believes the furnished information is correct and accurate
Storage Temperature -40 to +150 °C at the time of this printing. However, RF Micro Devices reserves the right to
make changes to its products without notice. RF Micro Devices does not
assume responsibility for the use of the described product(s).

Specification
Parameter Unit Condition
Min. Typ. Max.
Overall T=25 °C, VCC =3.6V, Freq=915MHz
Frequency Range 300 to 1000 MHz
Modulation FM/FSK
Modulation Frequency 2 MHz
Maximum FM Deviation 200 kHz Dependent upon Supply Voltage
PLL and Prescaler
Prescaler Divide Ratio 64/65 or 128/129
PLL Lock TIme 4/PLL BW ms The PLL lock time, from power up, is set
externally by the bandwidth of the loop filter.
PLL Phase Noise -72 dBc/Hz 10kHz Offset, 10kHz loop bandwidth
-95 dBc/Hz 100kHz Offset, 10kHz loop bandwidth
Reference Frequency 17 MHz
Max Crystal RS TBD 100 Ω
Charge Pump Current -40 +40 µA
Transmit Section
Maximum Power Level +3 +8 dBm Freq=433MHz
+2 dBm Freq=915MHz
Power Control Range 15 dB
Power Control Sensitivity 10 dB/V
Antenna Port Impedance 50 Ω TX ENABL=“1”
Antenna Port VSWR 1.5:1 TX Mode
Modulation Input Impedance 4 kΩ
11 Harmonics -23 dBc
Spurious dBc Compliant to Part 15.249 and I-ETS 300 220
Power Down Control
TRANSCEIVERS

Logic Controls “ON” 2.0 V Voltage supplied to the input; device is “ON”
Logic Controls “OFF” 1.0 V Voltage supplied to the input; device is “OFF”
Control Input Impedance 25 kΩ
Turn On Time 5 + 4/PLL ms From Change in OSC SEL,7.075MHz XTAL
BW
Turn Off Time 4 ms From Change in OSC SEL,7.075MHz XTAL
Power Supply
Voltage 3.6 V Specifications
2.7 to 5.0 V Operating limits
Current Consumption 27 mA TX Mode, LVL ADJ=3.6V
10 mA TX Mode, LVL ADJ=0V
8 mA PLL Only
1 µA LVL ADJ=0V, PLL ENABL=0V,
TX ENABL=0V, OSC SEL=0V

11-24 Rev B8 010509

 RF2513
Pin Function Description Interface Schematic
1 OSC B2 This pin is connected directly to the reference oscillator transistor base.
The intended reference oscillator configuration is a modified Colpitts. OSC B1 OSC B2
OSC E
An appropriate capacitor as chosen by the customer should be con-
nected between pin 1 and pin 2.

2 OSC E This pin is connected directly to the emitter of the reference oscillator See pin 1.
transistor. An appropriate capacitor as chosen by the customer should
be connected from this pin to ground.
3 OSC B1 This pin is connected directly to the reference oscillator transistor base. See pin 1.
The intended reference oscillator configuration is a modified Colpitts.
An appropriate capacitor as chosen by the customer should be con-
nected between pin 3 and pin 2.
4 PLL ENABL This pin is used to power up or down the VCO and PLL. A logic high
50 kΩ
(PLL ENABL>2.0V) powers up the VCO and PLL electronics. A logic PLL ENABL
low (PLL ENABL<1.0V) powers down the PLL and VCO.

5 GND1 Ground connection for the PA buffer amp. Keep traces physically short
and connect immediately to ground plane for best performance.
6 VCC3 This pin is used to supply DC bias to the transmitter PA. A RF bypass
capacitor should be connected directly to this pin and returned to
ground. A 100pF capacitor is recommended for 915MHz applications.
A 220pF capacitor is recommended for 433MHz applications.
7 LVL ADJ This pin is used to vary the transmitter output power. An output level 40 kΩ
adjustment range greater than 12dB is provided through analog volt- LVL ADJ
age control of this pin. DC current of the transmitter power amp ia also
reduced with output power. This pin MUST be low when the transmitter
is disabled.
400 4 kΩ

8 TX OUT RF output pin for the transmitter electronics. TX OUT output impedance VCC
is a low impedance when the transmitter is enabled. TX OUT is a high
impedance when the transmitter is disabled.

20
11
TX OUT

TRANSCEIVERS
9 GND2 Ground connection for the Tx PA functions. Keep traces physically
short and connect immediately to ground plane for best performance.
10 VCC1 This pin is used to supply DC bias to the PA buffer amp. A RF bypass
capacitor should be connected directly to this pin and returned to
ground. A 100pF capacitor is recommended for 915MHz applications.
A 220pF capacitor is recommended for 433MHz applications.
11 TX ENABL Enables the transmitter circuits. TX ENABL>2.0V powers up all trans- 20 kΩ
mitter functions. TX ENABL<1.0V turns off all transmitter functions TX ENABL
except the PLL functions. 40 kΩ

12 PRESCL Dual-modulus/Dual-divide prescaler output. The output can be inter-

faced to an external PLL IC for additional flexibility in frequency pro-
OUT gramming.
PRESCL
OUT

13 VREF P Bias voltage reference pin for bypassing the prescaler and phase
detector. The bypass capacitor should be of appropriate size to provide
filtering of the reference crystal frequency and be connected directly to
this pin.

Rev B8 010509 11-25

 RF2513
Pin Function Description Interface Schematic
14 MOD CTRL This pin is used to select the prescaler modulus. A logic “high” selects
64 or 128 for the prescaler divisor. A logic “low” selects 65 or 129 for MOD CTL

the prescaler divisor.

15 DIV CTRL This pin is used to select the desired prescaler divisor. A logic “high”
selects the 64/65 divisor. A logic low selects the 128/129 divisor. DIV CTL

16 MOD IN FM analog or digital modulation can be imparted to the VCO through See pin 18.
this pin. The VCO varies in accordance to the voltage level presented
to this pin. To set the deviation to a desired level, a voltage divider refer-
enced to Vcc is the recommended. Because the modulation varactors
are part of the resonator tank, the deviation is slightly dependent upon
the components used in the external tank.
17 VCC2 This pin is used to is supply DC bias to the VCO, prescaler, and PLL.
18 RESNTR- The RESNTR pins are used to supply DC voltage to the VCO, as well RESNTR+ RESNTR-
as to tune the center frequency of the VCO. Equal value inductors
should be connected to this pin and pin 20.

4 kΩ
MOD IN

19 NC Not internally connected.

20 RESNTR+ See pin 18. See pin 18.
21 GND3 GND is the ground shared on chip by the VCO, prescaler, and PLL
electronics. Keep traces physically short and connect immediately to
ground plane for best performance.
22 VCO TUNE Loop filter input to VCO. RESNTR+ RESNTR-

11
4 kΩ
VCO TUNE
TRANSCEIVERS

23 LOOP FLT Output of the charge pump. An RC network from this pin to ground is VCC
used to establish the PLL bandwidth.
OUT
LOOP FLT

24 OSC SEL A logic high (OSC SEL>2.0V) applied to this pin powers on reference
oscillator 2 and powers down reference oscillator 1. A logic low (OSC
SEL<1.0V) applied to this pin powers on reference oscillator 1 and
powers down reference oscillator 2.
ESD This diode structure is used to provide electrostatic discharge protec-
VCC
tion to 3kV using the Human body model. The following pins are pro-
tected: 1-3, 9, 10,12-15, 17, 21-23.

11-26 Rev B8 010509

 RF2513
RF2513 Theory of Operation

Introduction In addition to the DIV CTRL setting, one also sets the
The RF2513 is a low-cost FM/FSK UHF transmitter prescaler modulus by setting pin 14 (MOD CTRL)
designed for applications operating within the 300MHz either high or low. A high logic level will select the 64/
to 1000MHz frequency range. It is particularly intended 128 divisor. A low logic level will select the 65/129 divi-
for 315/433/868MHz band systems, remote keyless sor.
entry systems, and FCC Part 15.231 periodic transmit-
ters. It can also be used as a single- or dual-channel Pin 12 (PRESCL OUT) provides access to the pres-
local oscillator signal source. The integrated VCO, caler output. This is used for interfacing to an external
phase detector, prescaler, and reference oscillator PLL IC.
require only the addition of an external crystal to pro-
The RF2513 contains an onboard phase detector and
vide a complete phase-locked loop.
charge pump. The phase detector compares the
The RF2513 is provided in a 24-pin SSOP-24 package phase of the reference oscillator to the phase of the
and is designed to operate from a supply voltage rang- VCO. The phase detector is implemented using flip-
ing from 2.2V to 5.0V, accommodating designs using flops in a topology referred to as either “digital phase/
three NiCd battery cells, two AAA flashlight cells, or a frequency detector” or “digital tri-state comparator”.
lithium button battery. The device is capable of provid- The circuit consists of two D flip-flops whose outputs
ing up to 10mW output power into a 50Ω load are combined with a NAND gate which is then tied to
(+10dBm) and is intended to comply with FCC require- the reset on each flip-flop. The outputs of the flip-flops
ments for unlicensed remote control transmitters. are also connected to the charge pump. Each flip-flop
output signal is a series of pulses whose frequency is
RF2513 Functional Blocks related to the flip-flop input frequency.
A PLL consists of a reference oscillator, phase detec-
tor, loop filter, voltage controlled oscillator (VCO), and When both inputs of the flip-flops are identical, the sig-
a programmable divider in the feedback path. The nals are both frequency and phase locked. If they are
RF2513 includes all of these internally, except for the different, they will provide signals to the charge pump
loop filter and the reference oscillator’s crystal and two which will either charge or discharge the loop filter or
feedback capacitors. enter into a high impedance state. This is where the
name “tri-state comparator” comes from.
The reference oscillators are Colpitts type oscillators. 11
Pins 1 (OSC B2), 2 (OSC E), and 3 (OSC B1) provide The main benefit of this type of detector it’s ability to
connections to the internal transistors used as refer- correct for errors in both phase and frequency. When

TRANSCEIVERS
ence oscillators. The Colpitts configuration is a low locked, the detector uses phase error for correction.
parts-count topology with reliable performance and When unlocked, it will use the frequency error for cor-
reasonable phase noise. Alternatively, an external sig- rection. This type of detector will lock under all condi-
nal could be injected into the base of either transistor. tions.
In either case, the drive level should be around
The prescaler and the phase detector bias voltage is
500mVPP. This level prevents overdriving the device
brought out through pin 13 (VREF P). This allows
and keeps phase noise and reference spurs minimal.
bypassing of the of these two circuits to filter the refer-
The user sets which oscillator is operational by setting ence crystal frequency.
pin 24 (OSC SEL) either high or low. This allows the
The charge pump consists of two transistors, one for
implementation of two channel systems.
charging the loop filter and the other for discharging
The prescaler divides the Voltage Controlled Oscilla- the loop filter. It’s inputs are the outputs of the phase
tor (VCO) frequency down by either 64/65 or 128/129, detector flip-flops. Since there are two flip-flops, there
using a series of flip-flops, depending upon the logic are four possible states. If both amplifier inputs are low,
level present at pin 15 (DIV CTRL). A high logic level then the amplifier pair goes into a high impedance
will select the 64/65 divisor. A low logic level will select state, maintaining the charge on the loop filter. The
the 128/129 divisor. This divided signal is then fed into state where both inputs are high will not occur. The
the phase detector where it is compared with the refer- other states are either charging or discharging the loop
ence frequency. filter. The loop filter integrates the pulses coming from

Rev B8 010509 11-27

 RF2513
the charge pump to create a control voltage for the
VCC
voltage controlled oscillator.

The voltage controlled oscillator (VCO) is a tuned

differential amplifier with the bases and collectors C2
cross-coupled to provide positive feedback and a 360° X1
C1
phase shift. The tuned circuit is located in the collec-
tors. It is comprised of internal varactors and two exter-
nal inductors. The designer selects the inductors for
the desired frequency of operation. These inductors This type of oscillator is a parallel resonant circuit for a
also provide DC bias for the VCO. The output of the fundamental mode crystal. The transistor amplifier is
VCO is buffered and applied to the prescaler circuit, an emitter follower and the voltage gain is developed
where it is divided down and compared to the refer- by the tapped capacitor impedance transformer. The
ence oscillator frequency. series combination of C1 and C2 act in parallel with the
input capacitance of the transistor to capacitively load
The PLL and VCO circuitry can be enabled by setting
the crystal.
applying a “high” logic level to pin 4 (PLL ENABL).
Conversely, the PLL and VCO circuitry will be turned The nominal capacitor values can be calculated with
off if the level is tied “low”. the following equations.
The transmit amplifier is a two stage amplifier con-
sisting of a driver and an open collector final stage. It is
60 ⋅ C load 1
C 1 = ------------------------ and C 2 = --------------------------
capable of providing 8dBm of output power into a 50Ω freq MHz 1 1
------------- – ------
load while operating from a 3.6V power supply. C load C 1
The output power is adjustable by the setting of pin 7
The load capacitance is usually 32pF. The variable freq
(LVL ADJ). This analog input allows the designer a
is the oscillator frequency in MHz. The frequency can
15dB range of output power. As the LVL ADJ voltage is
be adjusted by either changing C2 or by placing a vari-
reduced, the output power and current consumption
able capacitor in series with the crystal. As an exam-
are reduced. LVL ADJ must be low when the transmit-
ple, assume a desired frequency of 14MHz and a load
ter is disabled.
capacitance of 32pF. C1 =137.1pF and C2 =41.7pF.
11 Additionally, the transmitter circuitry can be disabled
These capacitor values provide a starting point. The
entirely by applying a “low” logic level to pin 11 (TX
ENABL). During transmission, this pin should be tied drive level of the oscillator should be checked by look-
TRANSCEIVERS

“high”. This pin controls all circuitry except for the PLL ing at the signal at pin 2 (OSC E). It has been found
circuitry. that the level at this pin should generally be around
500mVPP or less. This will reduce the reference spur
During transmission the transmitter is enabled and the levels and reduce noise from distortion. If this level is
impedance of the output pin, pin 8 (TX OUT), is low. higher than 500mVPP then decrease the value of C1.
When the transmitter is not enabled, the impedance The values of these capacitors are usually tweaked
becomes high. during design to meet performance goals, such as
minimizing the start-up time.
The RF2513 contains onboard band gap reference
voltage circuitry which provides a stable DC bias over Additionally, by placing a variable capacitor in series
varying temperature and supply voltages. with the crystal, one is able to adjust the frequency.
This will also alter the drive level, so it should be
Designing with the RF2513
checked again.
The reference oscillator is built around the onboard
transistor at pins 1, 2 and 3. The intended topology is An important part of the overall design is the voltage
of a Colpitts oscillator. The Colpitts oscillator is quite controlled oscillator (VCO). The VCO is configured as
common and requires few external components, mak- a differential amplifier. The VCO is tuned via the exter-
ing it ideal for low cost solutions. The topology of this nal inductors, capacitor and varactor. The varactor
type of oscillator is as seen in the following figure. capacitance is set by the loop filter output voltage
through a 4kΩ resistor.

11-28 Rev B8 010509

 RF2513
nected to the charge pump output through an internal
RESNTR+ RESNTR-
4kΩ resistor. The loop filter is then connected in paral-
lel to this point at pin 23 (LOOP FLT). This limits the
loop filter topology to a second order filter usually con-
L L
sisting of a shunt capacitor and a shunt series RC. A
LOOP passive filter is most common, as it is a low cost and
FLT 4 kΩ low noise design. An additional pole could be used for
reducing the reference spurs, however there is not a
way to add the series resistor. This should not be a
reason for concern however.

The schematic of the loop filter is as follows.

Charge Pump

To tune the VCO the designer only needs to calculate VCC Loop Filter VCO

the value of the inductors connected to pins 18 and 20

(RESNTR- and RESNTR+). The inductor value is C1
R2
determined by the following equation.
2 1 1 C2
L = æ ---------------- ö ⋅ ---- ⋅ ---
1
è 2 ⋅ π ⋅ fø C 2

In this equation, f is the desired operating frequency

and L is the value of the inductor required. The value C The transfer function is
is the amount of capacitance presented by the varac-
tor, capacitor and parasitics. The factor of one half is s ⋅ τ2 + 1
F ( s ) = R 2 ⋅ ------------------------------------------
due to the inductors being in each leg. s ⋅ τ2 ⋅ ( s ⋅ τ1 + 1 )
The setup of the VCO can be summarized as follows.
where the time constants are defined as
First, open the loop. Next, get the VCO to run on the
desired frequency by selecting the proper inductor and
C1 ⋅ C2
capacitor values. The capacitor value will need to τ 2 = R 2 ⋅ C 2 and τ 1 = R 2 ⋅ ------------------- 11
include the varactor and circuit parasitics. After the C1 + C2
VCO is running at the desired frequency, then set the

TRANSCEIVERS
VCO sensitivity. The frequency at which unity gain occurs is given by

The sensitivity is determined by connecting the control 1

voltage input point to ground and noting the frequency. ω LBW = -------------------
Then connect the same point to the supply and again τ1 ⋅ τ2
note the frequency. The difference between these two
frequencies divided by the supply voltage is the VCO This is also the loop bandwidth.
sensitivity expressed in Hz/V. Increasing the inductor
value while decreasing the capacitor value will If the phase margin (PM) and the loop bandwidth
increase the sensitivity. Decreasing the inductor value (ωLBW) are known, it is possible to calculate the time
while increasing the capacitor value will lower the sen- constants. These are found using the following equa-
sitivity. tions.

When increasing or decreasing component values, sec ( PM ) – tan ( PM ) 1

τ 1 = -------------------------------------------------- and τ 2 = -------------------------
-
make sure that the center frequency remains constant. ωLBW ω 2 LBW ⋅ τ 1
Finally, close the loop.

External to the part, the designer needs to implement a With these known, it is then possible to determine the
loop filter to complete the PLL. The loop filter converts values of the filter components.
the output of the charge pump into a voltage that is
used to control the VCO. Internally, the VCO is con-

Rev B8 010509 11-29

 RF2513
2 mended that pre-compliance testing be performed so
τ 1 K PD ⋅ K VCO 1 + ( ω LBW ⋅ τ 2 ) that there are no surprises during final compliance
C 1 = ----- ⋅ ----------------------------
- ⋅ ----------------------------------------
τ2 ω2 2 testing. This will help keep the product development
LBW ⋅ N 1 + ( ω LBW ⋅ τ 1 )
and release on schedule.

τ2 Working with a laboratory offers the benefit of years of

C 2 = C 1 ⋅ æ ----- – 1ö compliance testing experience and familiarity with the
è τ1 ø
regulatory issues. Also, the laboratory can often pro-
vide feedback that will help the designer make the
τ2 product compliant.
R 2 = ------
C2
On the other hand, having a GTEM cell or an open air
test site locally offers the designer the ability to rapidly
As an example, consider a loop bandwidth of 50kHz, a determine whether or not design changes impact the
phase margin of 45°, a divide ratio of 64, a KVCO of product's compliance. Set-up of an open air test site
20MHz/V, and a KPD of 0.01592mA/2πrad. Time con- and the associated calibration is not trivial. An alterna-
stant τ1 is 1.31848µs, time constant τ2 is 7.68468µs, tive is to use a GTEM test cell.
C1 is 131.15pF, C2 is 633.26pF, and R2 is 12.14kΩ.
After the design has been completed and passes com-
In order to perform these calculations, one will need to pliance testing, application will need to be made with
know the value of two constants, KVCO and KPD. KPD is the respective regulatory bodies for the geographic
region in which the product will be operated to obtain
calculated by dividing the charge pump current by 2π.
final certifications.
For the RF2513, the charge pump current is 40µA.
KVCO is best found empirically as it will change with Conclusions
frequency and board parasitics. By briefly connecting The RF2513 is an FM/FSK UHF transmitter that fea-
pin 23 (LOOP FLT) to VCC and then to ground, the fre- tures a phase-locked output. This device is suitable for
quency tuning range of the VCO can be seen. Dividing use in a CFR Part 15.231 compliant product as well as
the difference between these two frequencies by the a local oscillator signal source. Two examples of show-
difference in the voltage gives KVCO in MHz/V. ing these applications have been provided. Further, the
RF2513 is packaged in a low cost SSOP-24 plastic
The control lines provide an interface for connecting package and requires few external parts, thus making
11 the device to a microcontroller or other signal generat- it suitable for low cost designs.
ing mechanism. The designer can treat pin 16 (MOD
IN), pin 15 (DIV CTRL), pin 14 (MOD CTRL), pin 24
TRANSCEIVERS

(OSC SEL), and pin 7 (LVL ADJ) as control pins whose

voltage level can be set.

General RF bypassing techniques must be observed

to get the best performance. Choose capacitors such
that they are series resonant near the frequency of
operation.

Board layout is always an area in which great care

must be taken. The board material and thickness are
used in calculating the RF line widths. The use of vias
for connection to the ground plane allows one to con-
nect to ground as close as possible to ground pins.
When laying out the traces around the VCO, it is desir-
able to keep the parasitics equal between the two legs.
This will allow equal valued inductors to be used.

Pre-compliance testing should be performed during

the design process. This can be done with a GTEM cell
or at a compliance testing laboratory. It is recom-

11-30 Rev B8 010509

 RF2513
Pin Out

OSC B2 1 24 OSC SEL

OSC E 2 23 LOOP FLT OUT

OSC B1 3 22 VCO TUNE

PLL ENABL 4 21 GND3

GND1 5 20 RESNTR+

VCC3 6 19 NC

LVL ADJ 7 18 RESNTR-

TX OUT 8 17 VCC2

GND2 9 16 MOD IN

VCC1 10 15 DIV CTRL

TX ENABL 11 14 MOD CTRL

PRESCL OUT 12 13 VREF P

11

TRANSCEIVERS

Rev B8 010509 11-31

 RF2513
Evaluation Board Schematic
H (915MHz) and M (868MHz) Boards
(Download Bill of Materials from [Link].)
P1 P2 P3 P4
AUDIO P3-1 1 AUDIO
P1-1 1 LVL ADJ P2-1 1 PRESC OUT P4-1 1 DIV 64

2 GND 2 GND 2 GND 2 GND

R5* R3* C20 P3-3 3 OSCSLT
R4* P1-3 3 PLL ON P2-3 3 TX EN P4-3 3 MOD CTL
0Ω 0Ω 3-10 pF
0Ω
4 GND

D2* D1* X2* X1 P3-5 5 VCC

C3
100 pF
1 24 OSC SEL
C2* C1
100 pF 100 pF Ref
2 23
Select
C17 C16
3 22
PLL ON
VCC
4 21
C4 C5 R1
10 nF 22 pF Phase L2
5 Detector/ 20
Charge Pump L3
LVL ADJ
6 19 6.8 nH
C18
100 nF Gain
7 Control 18 L4 C12 C13 C14
L1
56 nH 10 nF 22 pF 4.7 µF
J1 50 Ω µstrip 8.2 nH
8 17
RF OUT
C6 C7 C8 50 Ω µstrip
4 pF 4 pF 100 pF J2
9 16
MOD IN

VCC 10 15 DIV 64
C9 C10 Prescaler
10 nF 22 pF 11 14 MOD CTL

TX EN 12 13
2513401A, 402A
PRESC OUT C11
R2* 0.1 µF
* Denotes optional. These parts are not normally populated.

Board X1 (MHz) X2 (MHz) R1 (kΩ) L2 (nH) C16 (nF) C17 (nF)

M (868MHz) 13.57734 13.41015 2.2 8.2 47 nF 4.7

H (915MHz) 7.15909 7.07549 5.1 6.8 22 nF 2.2

11
TRANSCEIVERS

11-32 Rev B8 010509

 RF2513
Evaluation Board Schematic
L (433MHz) Board
P1 P2 P3 P4

P1-1 1 LVL ADJ P2-1 1 PRESC OUT P3-1 1 AUDIO P4-1 1 DIV 64

2 GND 2 GND 2 GND 2 GND

P1-3 3 PLL ON P2-3 3 TX EN P3-3 3 OSCSLT P4-3 3 MOD CTL

AUDIO
4 GND

P3-5 5 VCC
R5* R3* C21
R4*
0Ω 0Ω 3-10 pF
0Ω

X1
D2* D1* X2*
6.78 MHz
C3
100 pF
1 24 OSC SEL
C2* C1
100 pF 100 pF Ref
2 23
Select
C17 C16
3 22 2.2 nF 22 nF
PLL ON
VCC
4 21 L3 R1
C4 C5 4.7 kΩ
10 nF 100 pF Phase 39 nH
5 Detector/ 20
Charge Pump L4
LVL ADJ
6 19 39 nH
C18
100 nF Gain
7 Control 18 L5 C12 C13 C14
L1 L2
220 nH 10 nF 100 pF 4.7 µF
J1 50 Ω µstrip 22 nH 22 nH
8 17
RF OUT
C19 C6 C7 C8 50 Ω µstrip
8 pF 15 pF 8 pF 100 pF J2
9 16
MOD IN

VCC 10 15 DIV 64
C9 C10 Prescaler
10 nF 100 pF 11 14 MOD CTL

TX EN 12 13
PRESC OUT C11
R2* 0.1 µF
2513400A

11

TRANSCEIVERS

Rev B8 010509 11-33

 RF2513
Evaluation Board Layout 433MHz
Board Size 2.0” x 2.0”
Board Thickness 0.031”, Board Material FR-4

Evaluation Board Layout 868MHz

Board Size 2.0” x 2.0”

11
TRANSCEIVERS

Evaluation Board Layout 915MHz

Board Size 2.0” x 2.0”

11-34 Rev B8 010509

 RF2513
TX Power versus VCC ICC versus VCC
7.0
Level Adjust = VCC 40.0
Level Adjust = VCC
-40°C -40°C
-15°C -15°C
+10°C +10°C
5.0 +35°C 35.0 +35°C
+60°C
+85°C +60°C
+85°C

3.0 30.0
TX Power (dBm)

ICC (mA)
1.0 25.0

-1.0 20.0

-3.0 15.0

-5.0 10.0
2.5 3.0 3.5 4.0 4.5 5.0 2.5 3.0 3.5 4.0 4.5 5.0
VCC (V) VCC (V)

11

TRANSCEIVERS

Rev B8 010509 11-35

 RF2513

11
TRANSCEIVERS

11-36 Rev B8 010509