Unit 6: Architecture of Commercial Devices

Syllabus : CPLD Architecture, Xilinx XC9500, Altera Max7000, FPGA organization and
architecture, Altera Flex 10k.

When it comes to programmable logic devices or PLDs, there are a number of different options
to choose from. From PALs and PLAs, to CPLDs and FPGAs- you can go either way depending
on what your individual requirements are in regards to your development project.

What is CPLD?

CPLD stands for Complex Programmable Logic Device. As explained by the name, these are
devices with relatively higher complexity than the likes of PALs but are less complex than
FPGAs or Field Programmable Gate Arrays.

A CPLD is essentially made up of numerous macrocells, consisting of disjunctive standard form

expressions and other logic operations for more specific applications for logic implementation.
Macrocells can be defined as the functional unit or building block of a Complex Programmable
Logic Device which can perform combinational or sequential logic. They contain a combination
of AND and OR gates arranged in an array that can be programmed to perform and execute
many different logic functions.

The CPLDs was the forerunner of the FPGA and is still helpful today in several applications.
We will start this article to examine the historical development of the CPLD to understand the
advantages and disadvantages of the CPLDs. Most major PLD vendors, including Intel (formerly
Altera), Xilinx, offer a wide-ranging of complex programmable devices Starting from the most
straightforward version name PAL, which is a result of a sum of products (SOP) logic functions
using a programmable gate and fixed array of gates followed by a fixed or array. This permitted
the substitution of up to a different logic package with a generic logic solution.

CPLD Architecture

Intel expanded the concept of PAL by putting multiple PAL structures called macrocells into a
single unified circuit package in which all the input pins are accessible to each macrocell, and
any macrocell could push any output pin. CPLDs were also built-in CMOS technology to be
reprogrammable while Bi-polar PALs are not. Although it didn’t seem to be a general
characteristic at the time, reprogrammability is now considered a vital aspect of PLD devices.
The program that defined the interconnections and CPLDs is stored in an on-chip EE prompt.
Intel extended this concept by putting various macrocells in a single IC package in which all the
input pins are available to each macrocell, and each macrocell has a devoted output pin. With the
capability to explore 16 digital inputs at a time, each macrocell could decode a 16-bit address
from a processor and generate a chip select, as shown in Figure below. In this way, a single chip
with 8 or 16 macrocells could create tip selects for an entire microprocessor system. The CPLDs
are correlated with the processor system’s glue logic.

The above figure shows that a CPLD Macrocell is just essentially a registered PAL array. The
fake symbols represent programmable configuration switches present in the device. The PIA is a
matrix of interconnecting wires that links the macrocells together, feeding the output of the cells
to the inputs of other cells. This arrangement is suitable for the kind of problems that require a
good deal of logic for every flip-flop, like a complex sixteen state machine wider-input decoder.
However, the CPLD architecture did not scale effectively for designs that required many flip
flips. This has become the jurisdiction of the FPGA.

CPLD Family

There are two leading CPLD families: Xilinx (AMD) and Altera (Intel). Starting from Xilinx’s
CPLD family, the CPLDs are defined based on the different number of blocks and different I/O
blocks.
The Figure above shows the functional block of the CPLD Xilinx series XC9500 that contains 18
macrocells per FB, 36 input per FB; macrocell outputs can go to I/O cells or back into the switch
matrix to be routed to this.

Intel-Altera has the series name MAX for the CPLDs starting from MAX – 10, MAX – V, MAX
– II. They provide the lowest power, lowest cost CPLDs. MAX V CPLD family, the newest
family in the CPLD series, delivers the market’s best value. Featuring unique, non-volatile
architecture and one of the industry’s largest density CPLDs, MAX V devices provide a robust
design.

CPLD Features

There are several features that CPLDs possess that makes them similar to other chips and
devices in their category and set them apart as a unique solution that is the optimum choice for
specific scenarios and situations based on the user’s requirements. Here are some of the most
important and defining features of CPLDs:

 CPLDs have a relatively large number of gates that implement more complex devices and
programs possible. Compared to PALs, which generally have gates ranging around a
couple of hundred, CPLDs have thousands to over tens of thousands of gates.

 Special logic functions, as well as complex interconnected feedback paths between the
macro cells, makes CPLD logic much more flexible and modifiable as compared to
others.

 CPLD does not require an external configuration memory and can start operating
immediately after the system has been booted up. It is a type of non-volatile
configuration memory.

 They employ the use of Electrically Erasable Programmable Read-Only Memory

(EEPROM).

 Thanks to the non-volatile and non-ROM based configuration of the CPLDs, you do not
have to worry about any unexpected delays or memory loss. The memory is retained in
the circuit even when it has been powered down.

 CPLDs are also easy to reprogram at a meagre cost, reducing your overall costs and
expenditure while simultaneously improving the time to market of your products.

 The integrative and simplistic nature of CPLDs makes them a perfect fit in most design
flows and architecture, posing very little trouble in terms of integration and design
adjustments.
  They have low maintenance costs, proving to be a sound investment in the long run.

 The non-volatile nature of CPLDs makes them a much more secure option as it is next to
impossible to steal the stored design. The external memory of the FPGA devices can
expose the IP, although the user can implement encryption techniques to combat this
security threat.

 CPLDs are much better suited for deterministic timing analysis than FPGAs because of a
lesser number of interconnects.

In some cases, you may find that both. CPLDs and FPGAs can be used and implemented
together for optimum performance and functioning. In these designs, CPLDs are typically
dedicated to acting as glue logic, and they also boot up the FPGA and the rest of the board.

CPLD Clock

CPLD requires multiple clocks because several parts of the CPLD will be programmed with
separate functionality that operates asynchronously from other parts of the CPLD using different
clock domains.

Some clocks will be generated from the external clock source using one of the unique clocks
generating chips that generated different clocks that have defined phase relationships. These can
be leveraged in different sections of the CPLD to improve the functioning performance of the
chip programming.

It is perfectly safe to have different parts of the CPLD using different clocks. Your task as the
designer is to use intense care to keep each circuit restricted to its clock domain. And, if it turns
out to be essential for some logic to make a crossing from one clock domain to another, you
apply the necessary design consistency to apply the essential clock synchronization circuits to
the crossing paths to confirm that the consequential logic is stable and not issue to metastability
problems.

CPLD Applications

The applications of CPLDs include the following:

 They for high performance, critical control applications.

 Used for boot loader

 Used as a memory element

 Used for address decoding

 CPLDs used for small logic calculations or checksum generation

 CPLD vs. FPGA- The Differences Between Them

FPGAs can essentially be considered as a more advanced or even more complex version of
CPLDs. The primary difference between them is that where CPLDs use a sum of products logic
with a sea of gates, FPGA uses internal look up tables or LUTs.

FPGAs can accommodate for millions of gates and also offer much more flexibility thanks to
their field modifiable circuit design. Compared to CPLDs, FPGAs are RAM based and lose their
memory and data when the power source is removed. This means that you will need to download
the data and the configuration from an external memories source to begin its operation again.
This can, unfortunately, lead to boot up delays which you will not encounter with the non
volatile CPLDs. FPGAs are also more expensive when considered as an overall package.

Between CPLDs and FPGAs, it is wiser to go with the former if you are making simple
applications. Go with the latter for more complex applications. CPLDs used to be known for
their high power consuming modules, but the latest versions and models have turned it around
and have been made much more efficient in terms of power use and dissipation. Thermal
management, however, still remains a prominent issue in high complexity and high speed
FPGAs. As mentioned before, another problem with FPGAs is that the complex network of
interconnected between the various function blocks causes less deterministic signal routing.
Because of this, timing scenarios become complicated and implementation tools need to be
provided to the user by the vendor to allow for deterministic timing of signals.

In some cases, you may find that both. CPLDs and FPGAs can be used and implemented
together for optimum performance and functioning. In these designs, CPLDs are typically
dedicated to acting as glue logic and they also boot up the FPGA and the rest of the board.

Choosing a CPLD

You will find a lot of options even within CPLDs when you actually go out to invest in some
hardware for your project. When browsing through your options for CPLDs, there are certain
salient parameters that you should also keep in the forefront of your mind and use to basically
determine what some of the most important features are in your CPLD. your criteria could, of
course, vary in accordance with your personal, specific requirements and needs

 Always check the density of the chip and the number I/Os available

 Figure out how great a system performance you require and get a suitable speed grade in
your CPLD, otherwise you will end up paying way more than what you actually need and
are using in practical application

 Go through the power requirements of the device, standby as well as dynamic, and see if
it fits within what you can provide

XC9500 5V In-System Programmable (ISP) CPLD Family

The XC9500™ In-System Programmable (ISP) CPLD family takes complex programmable
logic devices to new heights of high-performance, feature-richness, and flexibility. This 5V
family delivers industry-leading speeds, while giving you the flexibility of an enhanced customer
proven pin-locking architecture along with extensive IEEE Std. 1149.1 JTAG boundary scan
support. It features six devices ranging from 36 to 288 macrocells with a wide variety of package
combinations that both minimize board space and maintain package footprints as designs grow
or shrink. All I/O pins allow direct interfacing to both 3 and 5 volt systems, while the latest in
compact, easy-to-use CSP and BGA packaging gives you access to as many as 192 signals.
Family Highlights

Highest density

 5 ns pin-to-pin logic delays on all pins

 fCNT to 125 MHz

Competitively Priced

 Wide range of package styles including new Chip Scale Packaging (CSP)

Wide Density Range

 36 to 288 macrocells (800 to 6,400 gates)

 34 to 192 I/Os

Customer Proven Pin-Locking Architecture

 Flexible 36V18 function block

 90 product terms drive any or all of 18 macrocells

 Global and product term clocks, output enables, set and reset

 Power selection for each macrocell

Designed for True 5 Volt In-System Programmability

 Industry standard JTAG interface

 Endurance of 10,000 program/erase cycles

 Device programming over the full voltage and temperature range

 20 years data retention

Programmable Outputs

 24 mA drive on all pins

 3.3 V or 5 volt I/O capability

 Slew rate control on each output

Industry-Leading JTAG Boundary Scan Support

 Extended boundary scan functions

 On-chip logic testing

 High impedance I/O isolation

 ID and USER Codes

 Design security

 Write Only (no readback) function

Seamless Integration of ATE and Third-Party JTAG Programming and Test Tools

 Automatic test system programming support

 HP3070

 Genrad

 Teradyne

 Extensive third-party tool support

 JTAG Technologies

 Corelis Incorporated

 ASSET Intertech

Easy-to-Use Design Tools: Alliance and Foundation Series Software Support

 Windows NT, Windows 95, SunOS, Solaris, HPUX

 Standards-based design flows

 Open third-party EDA systems integration with the Alliance Series Software

 Complete, stand-alone solutions with the Foundation Series Software

Flexible Pin-Locking Architecture

The XC9500 devices, in conjunction with our fitter software, gives you the maximum in
routability and flexibility while maintaining high performance. The architecture is feature rich,
including individual p-term output enables, three global clocks, and more p-terms per output than
any other CPLD. The proven ability of the architecture to adapt to design changes while
maintaining pin assignments (pin-locking) has been demonstrated in countless real-world
customer designs since the introduction of the XC9500 family. This assured pin-locking means
you can take full advantage of in-system-programmability and you can easily change at any time,
even in the field.

Full IEEE 1149.1 JTAG Development and Debugging Support

The JTAG capability of the XC9500 family is the most comprehensive of any CPLD on the
market. It features the standard support including BYPASS, SAMPLE/PRELOAD, and
EXTEST. Additional boundary scan instructions, not found in any other CPLD, such as INTEST
(for device functional test), HIGHZ (for bypass), and USERCODE (for program tracking),

allow you the maximum debugging capability.

The XC9500 family is supported by a wide variety of industry standard third-party development
and debugging tools including Corelis, JTAG Technologies, and Asset Intertech. These tools
allow you to develop boundary scan test vectors to interactively analyze, test, and debug system
failures. The family is also supported on all major ATE platforms including Teradyne, Hewlett
Packard, and Genrad.

Leadership FastFLASH™ Technology

Xilinx is the innovator in Flash technology designed specifically for high-performance CPLDs.
The superior pin-locking capability of the XC9500 family is made possible by a dense internal
switch matrix with over three times the routing switches of any other ISP CPLD. FastFLASH
cells that are 1/3 the size of EEPROM cells bring you the benefits of high-density and high-
performance along with the added benefit of 10,000 program/erase cycles to assure complete
product life cycle support. The rapid growth and rapid development of memory-based flash
technologies assures you of lower product costs along with multiple, competitive, state-of-the-art
fabrication sources.

Powerful Software Tools

Advanced fitter algorithms and powerful "auto-interactive" features allow you to choose between
pushbutton and manual design flows, and standards-based design-flows including EDIF, SDF,
VHDL (VITAL), and Verilog. Both the Alliance Series and Foundation Series software include
the JTAG software and the JTAG cable required for ISP JTAG programming of all XC9500
products.
Altera MAX 7000 CPLD

To realize logic [Link] MAX 7000 devices EEPROM cells are used. Because of
involvement of iterations the MAX 7000 devices are reprogrammed. MAX 7000 family devices
are combined into groups known as logic array blocks. In order to build complex logic circuits,
the macrocell is supplemented product terms. The MAX 7000 family provides programmable
speed/power optimization. The features of this family of CPLDs are, 1) High-performance
second-generation MAX architecture, 2) Built-in JTAG boundary-scan test, 3) Complete EPLD
family, 4) Programmable macrocell flip-flops with individual controls and 4) Programmable
power-saving mode in each macrocell. The MAX 7000 architecture includes, 1) Logic array
blocks 2) Macrocells, 3) Expander product terms, 4) Programmable interconnect array and 5)
Input/Output control blocks. The MAX 7000 architecture is based on high performance logic
array blocks consist of 16-macrocell arrays. Logic array blocks are linked together with the
programmable interconnect array. The MAX 7000 macrocell configured for sequential and
combinational logic operation. In MAX 7000 macrocell the combinational logic is implemented
in the logic array and provides five product terms per macrocell. Here, logic is routed between
logic array blocks to programmable interconnect array. Signals required by each logic array
block are routed from the programmable interconnect array into the logic array block. EEPROM
cell controls one input to a 2-input AND gate, and selects a programmable interconnect array
signal to drive into the logic array block. The I/O control block for the MAX 7000 family leads
to I/O pin configuration for input, output, or bidirectional operation. The I/O pins has tri-state
buffer to control global output signals. The I/O control block of devices has two global output
enable signals.
What is FPGA?

FPGA stands for Field-Programmable Gate Array and can be defined as a hardware chip that is
used to carry out logical operations. They are composed of an integrated network or sets of logic
blocks placed across a chip; where the circuits are the programmable logic gates. FPGAs consist
of individual configurable logic blocks, or CLBs, which are connected through programmable
interconnects. As suggested by the name of the semiconductor technology, advantages of
FPGA are known for their ability to be programmed when implemented in the field as opposed
to other kinds of semiconductor chips (e.g ASICs) which are largely rigid in their design and
execution.

FPGA Architecture

An FPGA is made up of an array of blocks called programmable logic blocks, these blocks are
connected by configurable interconnect matrix. This means that both the logic behavior and
internal routing can be programmed by the designer, giving the device its flexibility. The number
of logic blocks is depending on the FPGA size (and price). The larger the FPGA the more logics
blocks you could use. More logic blocks will allow you to use more “gates” and hence more
functionality. The following diagrams show a general overview of FPGA architecture. Since the
1980’s and still today FPGAs are using the same architecture as shown below.
 Figure : FPGA Architecture

The logic blocks and the interconnect structure are arranged in the form of a two-dimensional
array and spread across the FPGA.

The following paragraphs describe the internal architecture of an FPGA:

Logic Blocks

Logic blocks are the fundamental elements in an FPGA that provide the logic function
capabilities. An FPGA consists of many logic blocks that together can perform any possible
logic implementation. A logic block is configurable and generally consists of a flip-flop along
with a look-up-table and a muliplexer.

The following drawing shows a typical FPGA logic block architecture:

 Figure : FPGA Logic Block Example

Input and Output Blocks

Input and output blocks are located next to every physical input or output pin. The IO blocks
allow the user to select each pin functionality: whether it’s input, output or tri-state. And consist
of some buffers and logic that are beneficial to have near the input or output pin. In some cases,
the user can also control the signal slew rate to operate on fast or slow mode.

Figure : FPGA IOB Example

Using the internal routing, the signal is redirected in or from the IO block to the logic block.
Internal Routing

An FPGA chip’s internal routing is one of the most critical components of the device. It is the
path that is used to connect all signals, as well as your clock to the different parts of your FPGA.
The various logic blocks are connected to one another with the help of this internal routing which
consists of channels comprising of interconnecting wires and electrically reconfigurable
switches. These switches can be manipulated to connect and disconnect the various common
logic blocks at different points and create a unique FPGA chip that is specific to your
requirements.

Figure : FPGA Interconnect Example

FPGA Design Language

When it comes to FPGA programming, one of the most important parts is the design language.
This is the medium using which you will communicate with your technology and tell it what you
want it to do. Using this language, you will basically be defining the operations of the hardware
of that particular semiconductor chip and the device it powers. In the modern day, there are a
huge number of computer design languages that can be used for this purpose.

Normally, you will use any hardware description language, or HDL, in the process of FPGA
programming. You can use low level languages for circuits having relatively lower capacity.
Higher end languages such as VHDL and Verilog which are used for higher complexity circuits
and devices. Other factors that play a part in deciding which language to use include previous
experience, personal preference and expertise, availability of models, synthesis capabilities,
financial restraints, and hardware design.
Advantages of FPGA

An ASIC, or Application Specific Integrated Circuit for example, is designed to accomplish a

particular task. As such, it will only perform that one function and cannot be modified to
anything else, neither can it be erased and rewritten so as to reuse the chip. A new one must be
created for a new purpose. An FPGA, on the other hand, can be reprogrammed and reused, and is
much more flexible when it comes to customization and personalization, especially when
deployed out in the field. This makes FPGA much more suitable and preferable over an ASIC in
certain applications, which will be discussed ahead.

With the help of an FPGA , you can write a program which is loaded onto a silicon chip, and
then execute the functions. If you want to optimize a chip, to fit a certain workload, then you can
use an FPGA chip. Like mentioned before, FPGAs are field programmable and offer much more
scalability and flexibility. They are able to keep up with modern requirements of high
complexity and high performing devices. They also offer greater logic density, embedded
processors, DSP blocks, and clocking among other prominent features.

FPGA are ideal for systems where consistent updates are a requirement. If a processor needs
some changing, then FPGA chips can be used for making those changes if they are installed,
eliminating the need to purchase new hardware. If FPGA chips are used in cars, then they can be
updated with the help of these chips, even after they have been sold. These chips are also used
frequently by enterprise businesses, because they can be reprogrammed using a data path that
matches data analytics, image inference, and even compression.

The main purpose of an FPGA chip, at least originally, was for the prototyping of ASICs. The
benefit of using an FPGA for this purpose is that it can be reprogrammed again and again, until a
design is finalized and there are no bugs found in the design. Intel, a huge name in the IT
industry, uses FPGAs to prototype new permanent chips so as to ensure their quality, function,
and integrity.

FPGA Applications

Since FPGAs work in a parallel fashion, they boast much higher speeds and thus can be used to
solve complex computable problems, together with the re-programmability ability — this makes
FPGAs both powerful and flexible machines. Some of the most common uses and applications
for FPGAs today are:

 FPGA is being used frequently and extensively in communication systems to improve

network capacity, coverage, as well quality of service while simultaneously reducing
latency and delays, especially when it comes to the data manipulation. For example, in
 Server or cloud applications, companies are using FPGA extensively. Read here an article
by Forbes about the usage of FPGA in datacenters.

Xilinx FPGAs are being offered by Amazon Web Services to accelerate compute intensive
applications.

 The use of FPGA in automotive and vehicles allows application such as ADAR, LiDAR
and autonomous driving. for a reduction in energy consumption, and improvement in
efficiency, an increase in the power and communications systems, strengthened security
systems, as well as a reduced overall cost..

 In the business industry, the FPGA chips are opening up new doors for automation and
secure technology which can help business owners and factory runners counter security
threats and risks and enable the growth of automation in the workplace. Similar to the
industrial hemisphere, FPGAs are also being used in the defense department for increased
security, cyber or otherwise, as well as increased automation in vehicles and weapons.

 FPGAs are being used extensively over a wide range of other fields such as in medical
equipment, computer hardware, and radio devices. They are also being implemented in
the likes of bioinformatics, voice recognition technology, security and communications
 systems- wired or wireless, and in a number of scientific, medical, and consumer
electronics.

 Since FPGAs have a large internal memory along with a great number of multipliers,
they are being used as signal processing systems and digital signal processing
applications. The logic blocks of FPGAs are being used for image and video processing.

 FPGAs are used for the purpose of hardware and algorithm acceleration as well as for
accelerating artificial neural networks or machine learning applications as is being done
Microsoft in their Project Catapult.

 These are ideal for use in low volume, vertical application productions as it may prove to
be more affordable than an ASIC.

 The use of FPGAs is becoming increasingly more frequent as compared to

microcontrollers for the Internet of Things as it allows fast processing of multiple aspects
in a parallel and simultaneous fashion.

 They are ideal for use for high end control applications where an advanced degree of
control is needed.

There are two general types of digital integrated circuits: ASIC and FPGA. ASIC (application
specific integrated circuit) has a pre-defined one-specific hardware functionality which can’t be
reprogrammed after manufacturing. FPGA (field programmable gate array) on the other hand
can be programmed and reprogrammed after manufacturing.

FPGA is a type of integrated circuit that allows engineers to program customized digital logic,
it’s a programmable chip that changes its hardware logic according the program. The main idea
is to allow engineers to redesign and reconfigure their chips faster and cheaper and as often as
they want to, however FPGA chips have limitations too — there is nothing ideal in the world!
FPGAs first appeared in 1980’s and their initial application was to allow the engineers to have
general purpose programmable logic chip. This however required a lot of programming for being
able to perform simple functions back then, so the engineers tried to avoid them as much as
possible. But while in 1980’s FPGA was a simple interface device that was mostly targeted a
glue logic which was hard to use for designing a complex system, it became a system-level
integrated circuit with its own memory blocks, microprocessors and interfaces that allows
designing serious systems.

Advantages of FPGA

FPGAs have several main advantages that make them unique:

 They enable engineers to build exactly the needed hardware, instead of having to use
standard ICs or having to take the time, cost, and risk related to ASIC design.

 They allow doing operations in much faster, more energy efficient and more simple way
compared to microprocessor or microcontroller.

 FPGA functionality can be updated like any other software code. Even if the hardware
left the production site. This can help fixing bugs or adding new features.

Figure : FPGA Advantages

Compared to microprocessors, FPGAs deal better with parallel tasks since microprocessors are
sequential devices. However, microprocessors are more flexible when it comes to doing different
tasks. FPGA does one specific task extremely good once configured while microprocessor does
different things adequately.

CPLD vs FPGA

A complex programmable logic device (CPLD) is also a device that can be reprogrammed after
being manufactured, it’s another type programmable device. In this sense they are similar to
FPGA. However, there are significant differences as well. FPGA consists of many logic cells,
while CPLDs are made of fewer logic cells. Due to their size, CPLDs are usually cheaper and
faster. Nevertheless, CPLDs are very limited in their functions, they can’t be used for building
complex systems, they are usually used in simple designs such as glue logic.

Applications of FPGA

Applications for FPGA are many today. One of the examples is when we don’t know our
requirements for sure during the manufacturing or they change with time. FPGA is one of the
fastest and cheapest way of prototyping, but not limited to it. It is used for different purposes:
from flexible design and machine-learning training to fast trading and crypto mining. Server
application is one the latest application of FPGA devices.

However, they also have disadvantages such as:

 Hardware costs (but we believe this can change with time)

 Speed requirements (this will also improve as we go to deeper sub geometry

technologies)

Architecture and Building Blocks of FPGA

FPGA consists of building blocks that are like Lego pieces you can use to build your system. It
has a basic logic building block called logic cells (CLB) shown below, but can also contain
bigger other blocks like PLLs, interfaces, memories, etc. A single FPGA chip will have hundreds
of thousands of logic cells (CLBs).
 Figure : FPGA logic cell

We have a look up table (LUT) as a core of the FPGA logic block. LUT is a small memory that
can implement any Boolean function by “remembering” it’s truth table. As you can see the
output of the building block is multiplexed. One input of the multiplexor is a direct output from
the LUT, which is used for pure combinational logic such as NAND, NOR, XOR or other logic
gates. The other input of the multiplexer is the registered output of the LUT, after passing
through D-type flip-flop and being stored synchronously with the clock.

One logic cell itself is a simple circuit that can’t do too much, but when there are many logic
cells, we can implement any function we want. In order to do that the logic cell is being
connected to an array of other logic cells. See the diagram below.
 Figure : Conceptual simplified structure of an FPGA device

The orange rectangles between the CLB blocks in the middle of the diagram are the
programmable switches that can route the output from a logic cell to anywhere. This is a very
simplified diagram; in reality, there are many more wires and interconnects than shown here.

Pay attention to the carry in and carry out pins. Each adder is only one bit wide, while using the
carry in/carry out pins it is possible to create large adders and counters very quickly and
efficiently. Having fast, dedicated carry chains is one of the biggest advantages that FPGAs
have over other programmable logic devices like CPLD for example.

In FPGA, a clock can reach all flip flops since digital design without clock is almost
unimaginable. FPGAs have very advanced clock resources including a built-in configurable PLL
(phase locked loop) and DLL (Delay Locked Loop). Since almost no modern digital design
happens without multiple clocks with various frequencies and phase delays, clock management
is very important.
FPGA also has input-output blocks for reading and outputting data. In addition to standard I/O
blocks, most of the FPGAs have the following I/O features:

 Flip-flop output for synchronous I/O

 Differential signaling

 Double data rate (DDR)

 Serializers and deserializers (SERDES)

 Pull-up, pull-down, and tri-state I/O

 Adjustable slew rate, drive strength

FPGAs have built in memory like block RAM, distributed RAM (which can vary between
100Kb and 100Mb). The newest generation of FPGA devices also have DSP multiplier slices
which are mostly used in DSP applications (digital signal processing). Some other built-in blocks
that most of the FPGAs have are:

 ADC and DAC (Analog-to-Digital and Digital to analog converters)

 External memory controller such as DRAM, DDR, DDR2, etc.

 PCI Express controllers

 Ethernet MAC

 Dedicated FIFO

 High-speed transceivers

These blocks are designed on FPGA devices as “hard blocks” instead of being built by logic
blocks and switches after the manufacturing process, because they are usually required by all
complex systems. Since they exist in all the systems and are used very frequently, we want them
to be there to save time (it does not make sense to design them from scratch using CLBs and
switches all the time, instead we design them as a separate configurable block so that the
designers can still change their parameters), but more importantly we want them to have very
good characteristics, work very efferently and occupy less space. Moreover, some of these
blocks have analog parts in them which require manual design and can’t be built only by digital
cells.

How to Program and Configure an FPGA

Now let’s discuss the workflow of FPGA programming for building a system we want. In order
to configure the FPGA, we need to program it. For programming FPGA hardware description
languages such as Verilog, System Verilog and VHDL are used. These languages have some
differences like Verilog data types being pre-defined while VHDL allowing a wide choice of
data types (not necessarily pre-defined). Verilog is easier when it comes to syntax since it is
similar to C language. All these hardware languages are equally effective for designing hardware
devices. These languages are concurrent languages. This means that statements can be
implemented in a parallel way similar to real life hardware. They are sequential languages too,
since the statements are implemented one after another. They are also timing specific languages.
While writing HDL code we should make sure that the code is synthesizable. Code’s syntax may
be correct, but unlike software programming languages it also needs to be synthesizable. Verilog
has different level of abstraction – from behavioral to register transfer and gate level. They
describe circuits in a different level of abstraction. The workflow of defining hardware using
FPGA is shown below:
 Figure: FPGA programming workflow using Verilog

ALTERA FLEX 10K

The FLEX 10K series represents a breakthrough in the world of embedded programmable logic
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One of the advantages of the FLEX 10K is its reconfigurability. You can adjust and optimize
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