VLSI MODULE 2

1. Derive the threshold voltage for a CMOS inverter

The threshold voltage (𝑉𝑡ℎ ) of a CMOS inverter is defined as the input voltage at which
the output changes state, often taken as when the output equals half the supply voltage
(𝑉𝐷𝐷 /2) in a symmetric inverter. For matched CMOS inverters, the derivation gives:

𝑉𝑇,𝑛 + √𝐾𝑝 /𝐾𝑛 (𝑉𝐷𝐷 + 𝑉𝑇,𝑝 )

𝑉𝑡ℎ =
1 + √𝐾𝑝 /𝐾𝑛

where 𝑉𝑇,𝑛 and 𝑉𝑇,𝑝 are NMOS and PMOS threshold voltages, and 𝐾𝑛 , 𝐾𝑝 are current
parameters. This equation helps design the switching point based on transistor
properties and supply voltage.

2. What are the advantages of CMOS inverter over depletion load inverter?

CMOS inverters offer several advantages over depletion load inverters:

• Extremely low static power dissipation (only draws power during switching).

• Full voltage swing between 0 and 𝑉𝐷𝐷 , resulting in better logic levels.

• Improved noise margins and less susceptibility to noise.

• Higher integration density and simpler fabrication for complex circuits.

 • Reduced loading effects and symmetric signal propagation.

3. Why are critical voltages of an inverter defined for VTC when slope = -1?

Critical voltages (such as 𝑉𝐼𝐿 and 𝑉𝐼𝐻 ) are defined on the voltage transfer characteristic
(VTC) of an inverter at the points where the slope is -1. These points represent
transitions in the inverter's output and mark the boundaries for noise margins,
determining reliable high and low input regions. Identifying these helps design robust
logic circuits that function correctly in the presence of input noise.

4. How can we increase the noise margin of an inverter?

Noise margin in a CMOS inverter can be improved by:

• Increasing the supply voltage (𝑉𝐷𝐷 ), which widens noise margins but increases
power.

• Adjusting the transistor sizing (width-to-length ratios), which tailors the inverter
VTC and maximizes noise immunity.

• Modifying the channel lengths or using keepers—resulting in up to 40%

improvement in noise margin in some studies.

5. Estimate the dynamic power consumption of a CMOS inverter

The dynamic power consumed by a CMOS inverter, primarily during switching, is given
by:
2
𝑃𝑑𝑦𝑛 = 𝐶𝐿 ⋅ 𝑉𝐷𝐷 ⋅𝑓

where 𝐶𝐿 is the load capacitance, 𝑉𝐷𝐷 is the supply voltage, and 𝑓 is the switching
frequency. During steady-state operation, CMOS inverters have negligible static power
loss, and nearly all power is dissipated in the charging and discharging of load
capacitance during logic transitions.

6. How dynamic power consumption can be reduced for a CMOS inverter?

Dynamic power in CMOS inverters can be reduced using several techniques:

• Lowering the supply voltage (𝑉𝐷𝐷 ), since power is proportional to 𝑉𝐷𝐷

2
.

• Minimizing load capacitance (𝐶𝐿 ) by optimizing interconnects and transistor

sizing.

• Reducing switching activity using clock gating and disabling unused blocks.

• Using multi-Vdd and multi-threshold (𝑉𝑡 ) techniques to optimize power at circuit

or block level.
 • Gate-level optimizations to avoid unnecessary node transitions.

7. Locate five distinct regions for CMOS inverter and specify operating modes of
MOSFET on VTC

The voltage transfer characteristic (VTC) of a CMOS inverter identifies five regions with
specific MOSFET operating modes:

• Region A: 𝑉𝑖𝑛 < 𝑉𝑇𝑛 — NMOS is OFF (cut-off),

PMOS is ON (linear).

• Region B: 𝑉𝑖𝑛 𝑉𝐼𝐿 — NMOS enters saturation,

PMOS remains in linear.

• Region C: 𝑉𝑖𝑛 𝑉𝑀 — NMOS and PMOS both in

saturation; transition region, highest gain.

• Region D: 𝑉𝑖𝑛 > 𝑉𝐼𝐻 — PMOS in saturation,

NMOS moves to linear.

• Region E: 𝑉𝑖𝑛 > 𝑉𝐷𝐷 − 𝑉𝑇𝑝 — PMOS OFF (cut-

off), NMOS ON (linear).

These regions are critical for digital logic reliability and understanding switching
characteristics.

8. What is ratioed logic? Why is it called ratioed logic?

Ratioed logic is a design style where logic gate output levels depend on the ratio of
widths of pull-down (NMOS) and pull-up (PMOS or load) transistors, rather than a full
complementary structure. For instance, in pseudo-NMOS logic, a single PMOS load is
always ON, and outputs are determined by competition ("ratio") between ON NMOS and
PMOS devices. The term "ratioed" arises because the output swing and logic levels
depend directly on the size ratio of NMOS and PMOS transistors.

9. What are the disadvantages of CMOS inverter?

Key disadvantages of CMOS inverters are:

• Complex fabrication process and relatively higher cost for very small nodes.

• Significant leakage and static current at deep submicron technologies.

• Susceptibility to electrostatic damage (ESD).

• Slower speed and analog performance compared to bipolar technology at high

currents.

• Require careful layout to avoid latching effects and static charge damage.
10. Estimate 𝒕𝑯𝑳 and 𝒕𝑳𝑯 of a CMOS inverter using RC model

Propagation delay from high to low (𝑡𝐻𝐿 ) and low to high (𝑡𝐿𝐻 ) in a CMOS inverter can be
estimated using the RC model:

𝑡𝑝𝐻𝐿 ≈ 0.69 ⋅ 𝑅𝑛 ⋅ 𝐶𝐿
𝑡𝑝𝐿𝐻 ≈ 0.69 ⋅ 𝑅𝑝 ⋅ 𝐶𝐿

Where 𝑅𝑛 and 𝑅𝑝 are average ON resistances for NMOS and PMOS, and 𝐶𝐿 is the output
load capacitance. Practical delay values depend on device sizes and load, typically
modeled at the 50% input/output voltage crossing.

11. How rise and fall times are calculated?

• Rise time (𝑡𝑟 ) is the time taken for the output voltage to rise from 10% to 90% of
its maximum value (𝑉𝐷𝐷 ).

• Fall time (𝑡𝑓 ) is the time taken for the output voltage to fall from 90% to 10%
of 𝑉𝐷𝐷 .

• These times can be derived from the RC circuit equivalent of the inverter output,
where the transistor's equivalent resistance charges or discharges the load
capacitance 𝐶𝐿 .

• Typically, rise time approximates 𝑡𝑟 = 2.2𝑅𝑝 𝐶𝐿 and fall time 𝑡𝑓 = 2.2𝑅𝑛 𝐶𝐿 ,

where 𝑅𝑝 , 𝑅𝑛 are the equivalent resistances of PMOS and NMOS transistors
respectively.

12. Describe two methods of approximate delay calculations

Two common approximate methods to calculate CMOS inverter delay are:

1. RC Delay Model: Treats the inverter as an RC network with a resistance of the

conducting transistor and load capacitance. The propagation delay is
approximated as 𝑡𝑝 = 0.69𝑅𝐶, derived from the RC time constant for charging or
discharging the load capacitance.

2. Charge-Based Model: Estimates delay by calculating the charge required to

change the output voltage and dividing by the average drive current of the
transistor during switching. This method accounts for transistor non-linearity
more accurately than the RC model.
1. Design the 4:1 multiplexer circuit using TG switches (5 Marks)

A 4:1 multiplexer (MUX) using transmission gates (TGs) is constructed as follows:

• Inputs: 𝐼0 , 𝐼1 , 𝐼2 , 𝐼3

• Select lines: 𝑆1 , 𝑆0

• Use four TGs, each connected to one input.

• Each TG is enabled when its select lines match the required combination:

• 𝐼0 is enabled when 𝑆1 = 0, 𝑆0 = 0
 • 𝐼1 when 𝑆1 = 0, 𝑆0 = 1

• 𝐼2 when 𝑆1 = 1, 𝑆0 = 0

• 𝐼3 when 𝑆1 = 1, 𝑆0 = 1

• All TG outputs are tied together to produce the final output 𝑌, which equals the
selected [Link]+1

2. Design a 4:1 multiplexer using three 2:1 TG multiplexers (10 Marks)

To build a 4:1 MUX with three 2:1 TG MUXes:

• Stage 1: Use MUX A to select between 𝐼0 and 𝐼1 (control: 𝑆0 ), and MUX B

between 𝐼2 and 𝐼3 (control: 𝑆0 ).

• Stage 2: The outputs of MUX A and MUX B become inputs to MUX C, which
selects between them with 𝑆1.

• Logic: Output 𝑌 is

𝑌 = 𝑆1 ⋅ 𝑍1 + 𝑆‾1 ⋅ 𝑍0

where 𝑍0 = 𝑆0 ⋅ 𝐼1 + 𝑆‾0 ⋅ 𝐼0 , 𝑍1 = 𝑆0 ⋅ 𝐼3 + 𝑆‾0 ⋅ 𝐼2 .

• This configuration allows all four inputs to be routed using only three 2:1 TG
[Link]+1youtube

3a. Design an XOR gate using a 4:1 multiplexer (5 Marks)

For a 2-input XOR gate (𝑋 = 𝐴 ⊕ 𝐵) using a 4:1 MUX:

• Let 𝐴 and 𝐵 be select lines (𝑆1 , 𝑆0).

• MUX inputs are set according to XOR truth table:

• Input lines: 𝐼0 = 0; 𝐼1 = 1; 𝐼2 = 1; 𝐼3 = 0.

• The output 𝑌 = 𝐼0 when 𝐴 = 0, 𝐵 = 0, 𝑌 = 𝐼1 when 𝐴 = 0, 𝐵 = 1, 𝑌 =

𝐼2 when 𝐴 = 1, 𝐵 = 0, 𝑌 = 𝐼3 when 𝐴 = 1, 𝐵 = 1.

• Thus, output follows XOR behaviour for all select line combinations.

4. Design a CMOS logic gate for 𝒇 = 𝒂𝒃 + 𝒂𝒄 + 𝒄𝒃𝒅

For the function 𝑓 = 𝑎𝑏 + 𝑎𝑐 + 𝑐𝑏𝑑:

• Pull-Down Network (PDN) (NMOS): Use AND networks for each product term:

• 𝑎𝑏 (NMOS in series for a and b)

• 𝑎𝑐 (NMOS in series for a and c)

 • 𝑐𝑏𝑑 (NMOS in series for c, b, and d)

• Combine these branches in parallel to form the OR.

• Pull-Up Network (PUN) (PMOS): Dual of PDN; build NOR for each
complemented term using PMOS in parallel for each branch and series within
terms.

• Connect input signals accordingly to meet logic [Link]+4

5. Design a NAND3 gate using an 8:1 multiplexer

‾ ) with inputs A, B, C as select lines:
For a 3-input NAND (𝑌 = 𝐴𝐵𝐶

• MUX Select Lines: 𝑆2 = 𝐴, 𝑆1 = 𝐵, 𝑆0 = 𝐶

• Inputs configuration: Only when A=1, B=1, C=1 (i.e., 𝑆2 𝑆1 𝑆0 = 111), set that
input as 0; all other inputs are 1 due to NAND truth table.

• For MUX inputs:

• 𝐼0 = 1, 𝐼1 = 1, 𝐼2 = 1, 𝐼3 = 1, 𝐼4 = 1, 𝐼5 = 1, 𝐼6 = 1, 𝐼7 = 0

• Any selection except 111 yields output 1; 111 gives [Link]+2youtube

6. Design a NOR3 gate using an 8:1 multiplexer as a basis

‾ + 𝐶 ):
For a 3-input NOR (𝑌 = 𝐴 + 𝐵

• Select lines: 𝑆2 = 𝐴, 𝑆1 = 𝐵, 𝑆0 = 𝐶

• MUX Inputs: Output is 1 only when all inputs are 0 (i.e., 𝑆2 𝑆1 𝑆0 = 000), else 0 for
any input high.

• 𝐼0 = 1, 𝐼1 = 0, 𝐼2 = 0, 𝐼3 = 0, 𝐼4 = 0, 𝐼5 = 0, 𝐼6 = 0, 𝐼7 = 0

• MUX implements NOR by input mapping to the 8 possibilities of select

[Link]+2youtube

7. Four nMOS used as pass transistor with input 𝑽𝒊𝒏 = 𝑽𝑫𝑫 = 𝟓𝑽 and 𝑽𝒕𝒏 =
𝟎. 𝟕𝟓𝑽 with signals initially at (1,1,0,0) switched to (0,1,1,1). Find 𝑽𝒐𝒖𝒕 (10 Marks)

• The output voltage after passing through an nMOS pass transistor degrades by
approximately the threshold voltage 𝑉𝑡𝑛 because the nMOS can only pass
voltages above 𝑉𝑖𝑛 − 𝑉𝑡𝑛 .

• Since the input voltage changes from (1,1,0,0) to (0,1,1,1), calculate 𝑉𝑜𝑢𝑡 by
considering the threshold drop for each transistor switched ON in series and
ON/OFF states.
 • The exact output voltage would be approximately 𝑉𝐷𝐷 − 𝑛 × 𝑉𝑡𝑛 for 𝑛 series
nMOS ON transistors.

• Here, 𝑉𝑜𝑢𝑡 ≈ 5𝑉 − 0.75𝑉 = 4.25𝑉 or lower depending on transistor

[Link]

8. Design a tri-state circuit that is in a high-impedance state when the control

signal T=1, acts as a non-inverting buffer when T=0 (5 Marks)

• Use a tri-state buffer circuit, which has three states: high (1), low (0), and high-
impedance (Z).

• When T=0, the buffer passes input to output normally (non-inverting buffer).

• When T=1, the output is disconnected (high impedence) by disabling both pull-
up and pull-down transistors.

• Implementation usually done using CMOS transmission gates controlled by T

and 𝑇‾ signals for output enable/[Link]+1youtube

9. Full adder sum bit 𝒔 = 𝒂 ⊕ 𝒃 ⊕ 𝒄 using multiplexer-based gates (10 Marks)

• Implement the sum bit using XOR logic.

• Use a 4:1 MUX with two inputs as select lines (say 𝑎 and 𝑏) and the third
input 𝑐 as MUX data inputs to create the sum:

• Set MUX inputs according to 𝑠 = 𝑎 ⊕ 𝑏 ⊕ 𝑐 truth table.

• This reduces the complexity and transistor count compared to direct XOR gate
implementations.

• MUX implementation also provides efficient hardware utilization for full adder
sum [Link]+1youtube

10. Implement 𝒀 = (𝑨. 𝑩) + (𝑨. 𝑪. 𝑬) + (𝑫. 𝑬) + (𝑫. 𝑪. 𝑩) in full static CMOS with no
more than 10 transistors (10 Marks)

• Use Rabey’s optimization method to factor the boolean and share transistors
between pull-up and pull-down networks.

• Regroup terms, e.g., (𝐴. 𝐵) + 𝐴. 𝐶. 𝐸 and 𝐷. 𝐸 + 𝐷. 𝐶. 𝐵 as branches driven

by 𝐴 and 𝐷.

• Reuse common sub-expressions and carefully design transistor pairs

complementarily to implement pull-up and pull-down networks.

• This method achieves full voltage swing and noise margin with only 10 transistors
1. What are the advantages of dynamic logic over static logic? (2 Marks)

• Dynamic logic circuits use fewer transistors per gate than static logic, resulting in
smaller silicon area and reduced input capacitance.

• They typically offer higher switching speed due to reduced parasitic loading and
faster NMOS-only [Link]+2

2. What are the disadvantages of dynamic logic? (5 Marks)

• Charge leakage: Output state can degrade over time due to capacitor leakage,
requiring periodic refreshing.

• Noise sensitivity: More susceptible to noise, which can cause incorrect

switching.
 • Clock dependency: Circuits require a global clock for operation, increasing
design complexity.

• Charge sharing: Internal node voltage drops due to shared capacitance can
cause output errors.

• Design complexity and power consumption: Precise timing and design

techniques are needed; dynamic gates often consume higher dynamic power
due to frequent [Link]+3

3. What is precharge-evaluate logic? (2 Marks)

• Precharge-evaluate logic (dynamic logic) uses a clock to operate in two phases:

"precharge" (sets output to a default state, usually high) and "evaluate"
(conditionally discharges output based on inputs).

• Precharge ensures the node is set, and evaluate allows logic computation by the
pull-down [Link]+3

4. Implement a 2-input NOR gate using precharge-evaluate logic (5 Marks)

• During the precharge phase, a PMOS transistor sets the output node (𝑌) to high
(𝑉𝐷𝐷 ).

• During the evaluation phase, if either input (𝐴 or 𝐵) is high, at least one NMOS
transistor conducts, pulling the output low.

• If both 𝐴 and 𝐵 are low, output remains high, thus performing NOR
[Link]+1youtube

5. Why dynamic logic cannot be cascaded directly? (5 Marks)

• In dynamic logic, the output is valid only during the evaluate phase; cascading
stages can result in incorrect operation due to charge sharing and timing
mismatches.

• Output node may lose precharged value, or next stage may evaluate before
previous stage output is valid, causing logic errors and signal glitches.

• 6. How domino logic solves the cascading

problem of dynamic logic? (5 Marks)
Domino logic addresses the cascading problem by inserting a static CMOS
inverter between each dynamic stage. This “breaks” the direct chain of
dynamic gates, ensuring that each output can only transition once during the
evaluate phase. This allows reliable multi-stage operation without charge
sharing or signal loss, as each inverter restores the logic level fully. Thus,
 domino logic supports fast, noise-immune cascading, similar to falling
dominoes—each stage triggers the next reliably.
• 7. What is signal race? How NORA logic is not
affected by race? (5 Marks)
• A signal race occurs in dynamic logic when the relative timing of signals
causes one to arrive at a gate too early or too late, potentially producing
incorrect outputs (“races” between paths). NORA (NO Race) logic interleaves
dynamic n-type and p-type stages with complementary clocking—ensuring
no two consecutive dynamic stages are active together—eliminating race
hazards inherent in dynamic cascades.
• 8. What is charge sharing? How to prevent
charge sharing? (5 Marks)
• Charge sharing in dynamic logic refers to the undesired redistribution of
charge from the precharged output node to internal nodes, causing output
voltage degradation and potential logic errors. Prevention techniques include
precharging critical internal nodes, using keeper transistors to maintain
output level, or minimizing capacitance on susceptible nodes.
• 9. Implement Manchester carry chain using
MODL (10 Marks)
• A Manchester carry chain (MCC) adder in MODL (Multi-Output Domino Logic)
computes carry signals efficiently. In this design, each domino stage
generates carry-propagate and carry-generate signals using parallel dynamic
blocks. The MODL topology allows several carry bits to be computed per
cycle, improving performance and scalability for wide adders.
• 10. Implement a NAND gate using DCVSL (5
Marks)
• DCVSL (Differential Cascode Voltage Switch Logic) uses differential NMOS
pull-down networks for both true and complementary logic functions, with
common PMOS loads. To make a NAND2 gate, design two complementary
nMOS networks: one for 𝐴 ‾⋅ 𝐵, another for 𝐴 ⋅ 𝐵; outputs drive the differential
circuit, offering fast switching and noise immunity.
•
1. Draw the circuit diagram of D-type flip-flop using transmission gate (10 Marks)

• A D-type flip-flop using transmission gates (TG) consists of two latches—one is

negative level-sensitive (master), the other is positive level-sensitive (slave).

• ‾ )
Transmission gates controlled by clock (𝐶𝐿𝐾) and its complement (𝐶𝐿𝐾
determine which latch is transparent.

• The D input passes to Q only on the clock edge (usually rising for edge-triggered
DFF), and the connection involves two inverters and two TGs per latch for signal
flow, ensuring reliable data storage and transfer.

2. Differentiate between combinational and sequential circuits (5 Marks)

• Combinational circuits: Output depends solely on the current input values. No

memory, no feedback; examples include adders, multiplexers.

• Sequential circuits: Output depends on present inputs and previous states due
to memory elements (flip-flops, latches). Feedback is present; examples are
counters, registers, state machines.

• Main differences: time-independence vs time-dependence, absence vs

presence of memory, and primary building blocks.

3. What is the advantage of JK flip-flop over SR flip-flop? (5 Marks)

• JK flip-flops do not have the invalid state present in SR flip-flops (where S=R=1
causes an undefined output).

• JK flip-flops allow toggling action when J=K=1, they are more versatile and stable.
 • Race conditions reduced and universal flip-flop functionality, as D, T, SR flip-
flops can be made from JK.

4. Draw and explain working of SR latch using positive and negative logic (10 Marks)

• SR latch: Consists of two cross-coupled NOR or NAND gates. Set (S) and Reset
(R) inputs control the circuit.

• Positive logic: Logic '1' means high voltage or 'true' state. Setting S=1 sets Q=1;
R=1 resets Q=0.

• Negative logic: Logic '0' means active state; often used in NAND-based latches.

• Operation: Q remains until inputs change, demonstrating bistable behavior. S=1,

R=0 sets; S=0, R=1 resets; S=R=0 holds current state; S=R=1 is invalid (for SR-
NOR latch).

5. Describe the circuit operation of Master Slave JK Flip Flop (10 Marks)

• A Master-Slave JK Flip-Flop consists of two JK flip-flops connected in series; the

master responds to the clock’s leading edge, and the slave to the trailing edge.

• On the rising edge, the "master" latches the input state; on the falling edge, the
"slave" transfers the master’s output to its own, producing the final output 𝑄.

• This arrangement eliminates timing problems and the race-around condition

seen in basic JK flip-flops, ensuring only one output change per clock cycle.

6. What is bistability principle? What is metastable state? (5 Marks)

• Bistability principle: Digital storage circuits (latches, flip-flops) are bistable—

they have two stable states (0 or 1) due to positive feedback, retaining their value
until changed by input signals.

• Metastable state: If timing constraints (setup, hold times) are violated, the
circuit may enter a temporary, unpredictable state—neither clearly 0 nor 1. This
is metastability; the circuit eventually settles to a stable state, but may output
unreliable logic during the transition.

7. Draw a clocked CMOS D latch (5 Marks)

• A clocked CMOS D latch is built using transmission gates (TGs) and two
inverters. The D latch latches input 𝐷 when clock (CLK) is high; otherwise, it
holds the previous value.

• ‾ , gating the data path in or out. The schematic

TGs are controlled by CLK and 𝐶𝐿𝐾
includes:
 • D input, one TG (enabled by CLK), inverter as storage, another TG
‾ ), and final output inverter [; diagrams are available in
(enabled by 𝐶𝐿𝐾
standard references].

8. Why edge triggered flip-flops are preferred? (5 Marks)

• Edge-triggered flip-flops change state only on specific clock transitions

(rising/falling edge), providing precise timing control.

• They are less susceptible to glitches and race conditions compared to level-
triggered latches, supporting reliable data transfer in high-speed, synchronous
digital systems.

• Circuit complexity is reduced and integration with large ICs is straightforward.

1. Write a Verilog program for a two-input NAND gate

verilog

module nand_gate(

input a,

input b,

output y

);

assign y = ~(a & b);

endmodule

This code defines a basic 2-input NAND gate using dataflow modeling in Verilog.

2. Design the following circuits using transmission gates

(a) D flip-flop

• A D flip-flop using transmission gates consists of two latches: a "master" and a

"slave," each using a pair of transmission gates controlled by the clock and its
complement, with inverters for feedback.

• Data passes from D to Q on the clock edge, storing the value until the next edge.

(b) Two-input XOR gate

• A 2-input XOR using transmission gates connects two TGs as controlled

inverting/non-inverting selectors.

• Each input is passed or inverted via separate TGs based on the state of the other
input. The outputs combine to give 𝐴 ⊕ 𝐵 = 𝐴‾𝐵 + 𝐴𝐵‾.

1. Draw a stick diagram of CMOS NAND gate

• A stick diagram visually represents the layout of a CMOS NAND gate, showing
poly (for gate), n-diffusion (NMOS), p-diffusion (PMOS), and metal connections.

• For a 2-input CMOS NAND:

• Two PMOS transistors in parallel (at top, connected to VDD)

• Two NMOS transistors in series (bottom, connected to GND)

• Input gates controlled by polysilicon running perpendicular to diffusions

• The output node is taken where both branches meet, showing contacts
and layers ().

2. Draw a stick diagram of CMOS XOR gate

 • The CMOS XOR stick diagram depicts the required arrangement of series/parallel
NMOS and PMOS transistors for 𝐴 ⊕ 𝐵, clearly labeling gates, drains, sources,
and output ().

• The layout uses crossing polysilicon and diffusion for individual transistors,
joining metal for output and power rails.

3. Design a CMOS half-adder circuit

• A CMOS half adder produces:

• 𝑆𝑈𝑀 = 𝐴 ⊕ 𝐵 (implemented as a CMOS XOR gate)

• 𝐶𝐴𝑅𝑅𝑌 = 𝐴 ⋅ 𝐵 (using a CMOS AND gate)

• Both outputs are produced in parallel, with the schematic using complementary
pull-up (PMOS) and pull-down (NMOS) networks following sum/carry logic ().

• Inputs A, B feed to separate logic gates for each output, ensuring full CMOS logic
swing and noise margins.

4. Realize a 2:1 MUX using CMOS transmission gate

• A 2:1 multiplexer selects 𝑌 = 𝑆 ⋅ 𝐴 + 𝑆‾ ⋅ 𝐵:

• Use two transmission gates, one passing A (enabled by S), the other
passing B (enabled by 𝑆‾)

• The output connects the drains of both TGs, and the select lines control
which data path is enabled ().

• The circuit shows two complementary control signals (S, 𝑆‾), TGs built from
parallel PMOS and NMOS.

5. What is pseudo-nMOS gate and what is its advantage over CMOS gate?

• Pseudo-nMOS gate uses a single, always ON pMOS transistor as a load,

combined with nMOS pull-down network.

• It has fewer transistors than static CMOS (which needs complementary pMOS
and nMOS), resulting in smaller area and faster switching.

• Advantage: Higher speed (especially for large fan-in gates) and reduced
transistor count; disadvantage is static power dissipation due to always ON
pMOS.

6. Implement the Boolean function 𝑭 = 𝑨(𝑩 + 𝑪𝑫) using static CMOS logic.

• 𝐹 = 𝐴(𝐵 + 𝐶𝐷) can be implemented by:

 • PMOS pull-up network: Parallel connection of 𝐵 and 𝐶 ⋅ 𝐷, all in series
with 𝐴.

• NMOS pull-down network: Parallel branch of NMOS for 𝐵 and series

of 𝐶 and 𝐷, all in parallel with an NMOS for 𝐴 (to respect duality).

• Proper sizing and connection of transistors ensure full voltage swing and correct
logic.

7. Draw the circuit of a CMOS full-adder and explain its operation.

• CMOS full adder adds three inputs (A, B, Cin) to produce sum and carry.

• Sum is SUM = 𝐴 ⊕ 𝐵 ⊕ 𝐶𝑖𝑛, usually realized with CMOS XOR gates.

• Carry is Cout = 𝐴𝐵 + 𝐵𝐶𝑖𝑛 + 𝐴𝐶𝑖𝑛, using CMOS AND/OR logic.

• The circuit consists of pull-up PMOS and pull-down NMOS networks arranged as
per the logic expressions, ensuring full logic swing and reliable operation.

8. Design a clocked inverter using static CMOS logic.

• A clocked inverter uses a standard CMOS inverter with a clock-controlled

transmission gate (TG) or pass-gate controlling input or output.

• When clock is high, the inverter passes input to output; when clock is low, output
is held or set to high impedance.

• This design reduces power consumption and aids synchronous logic operation.

9. Design a two-input XOR gate using pseudo-nMOS logic.

• Construct XOR using nMOS network implementing XOR function with a single
always-on pMOS load transistor.

• Due to the ratioed pull-up load, the circuit is faster but consumes static power.

• Implementation uses fewer transistors than full CMOS XOR gates.

10. Write a Verilog program for Latch.

verilog

module latch(input d, input en, output reg q);

always @ (en or d) begin

if (en)

q = d;

end
endmodule

Device Structure of CMOS Inverter

• A CMOS inverter consists of a PMOS transistor at the top connected

to 𝑉𝐷𝐷 (positive supply) and an NMOS transistor at the bottom connected to
ground.

• The input is connected to the gates of both transistors.

• The output is taken from the node connecting the drains of PMOS and NMOS.

• The PMOS transistor conducts when the input is low, pulling the output high.

• The NMOS transistor conducts when the input is high, pulling the output low.

• This complementary arrangement ensures low static power consumption and

full voltage swing at the output.

Fabrication Steps of CMOS Inverter

1. Start with a p-type Silicon substrate.

2. Grow a thin layer of silicon dioxide (SiO2) on the substrate by thermal

oxidation; this acts as a field oxide for isolation.

3. Form n-well region by doping (ion implantation or diffusion) where PMOS

transistors will be built.

4. Remove SiO2 from active areas for transistor formation using photolithography
and etching.

5. Grow thin gate oxide on the exposed active areas; this will form the gate
dielectric.

6. Deposit polysilicon layer over the wafer; this forms the transistor gates.

7. Pattern and etch polysilicon to form gate structures.

8. Dope the source and drain regions for NMOS and PMOS transistors by ion
implantation or diffusion.

9. Deposit and pattern insulating layers (e.g., SiO2 or Si3N4) between transistors.

10. Create contacts and metallization by depositing metal layers and patterning
them to form electrical connections.

11. Final passivation and testing complete the CMOS processing.