Sequential Circuit

Introduction
In our previous sections, we learned about combinational circuit and their working.
The combinational circuits have set of outputs, which depends only on the present
combination of inputs. Below is the block diagram of the synchronous logic circuit.

The sequential circuit is a special type of circuit that has a series of inputs and
outputs. The outputs of the sequential circuits depend on both the combination of
present inputs and previous outputs. The previous output is treated as the present
state. So, the sequential circuit contains the combinational circuit and its memory
storage elements. A sequential circuit doesn't need to always contain a
combinational circuit. So, the sequential circuit can contain only the memory
element.
Difference between the combinational circuits and sequential circuits are given
below:

Combinational Circuits Sequential Circuits

1) The outputs of the The outputs of the sequential circuits

combinational circuit depend depend on both present inputs and
only on the present inputs. present state(previous output).

2) The feedback path is not The feedback path is present in the

present in the combinational sequential circuits.
circuit.

3) In combinational circuits, In the sequential circuit, memory

memory elements are not elements play an important role and
required. require.

4) The clock signal is not required The clock signal is required for
for combinational circuits. sequential circuits.

5) The combinational circuit is It is not simple to design a sequential

simple to design. circuit.

Types of Sequential Circuits

Asynchronous sequential circuits
The clock signals are not used by the Asynchronous sequential circuits. The
asynchronous circuit is operated through the pulses. So, the changes in the input
can change the state of the circuit. The asynchronous circuits do not use clock
pulses. The internal state is changed when the input variable is changed. The un-
clocked flip-flops or time-delayed are the memory elements of asynchronous
sequential circuits. The asynchronous sequential circuit is similar to the
combinational circuits with feedback.

Synchronous sequential circuits

In synchronous sequential circuits, synchronization of the memory element's state is
done by the clock signal. The output is stored in either flip-flops or latches(memory
devices). The synchronization of the outputs is done with either only negative edges
of the clock signal or only positive edges.

Clock Signal and Triggering

Clock signal
A clock signal is a periodic signal in which ON time and OFF time need not be the
same. When ON time and OFF time of the clock signal are the same, a square wave
is used to represent the clock signal. Below is a diagram which represents the clock
signal:

A clock signal is considered as the square wave. Sometimes, the signal stays at
logic, either high 5V or low 0V, to an equal amount of time. It repeats with a certain
time period, which will be equal to twice the 'ON time' or 'OFF time'.

Types of Triggering
These are two types of triggering in sequential circuits:

Level triggering
The logic High and logic Low are the two levels in the clock signal. In level
triggering, when the clock pulse is at a particular level, only then the circuit is
activated. There are the following types of level triggering:

Positive level triggering

In a positive level triggering, the signal with Logic High occurs. So, in this triggering,
the circuit is operated with such type of clock signal. Below is the diagram of positive
level triggering:
Negative level triggering
In negative level triggering, the signal with Logic Low occurs. So, in this triggering,
the circuit is operated with such type of clock signal. Below is the diagram of
Negative level triggering:

Edge triggering
In clock signal of edge triggering, two types of transitions occur, i.e., transition
either from Logic Low to Logic High or Logic High to Logic Low.

Based on the transitions of the clock signal, there are the following types of edge
triggering:

Positive edge triggering

The transition from Logic Low to Logic High occurs in the clock signal of positive
edge triggering. So, in positive edge triggering, the circuit is operated with such type
of clock signal. The diagram of positive edge triggering is given below.

Negative edge triggering

The transition from Logic High to Logic low occurs in the clock signal of negative
edge triggering. So, in negative edge triggering, the circuit is operated with such
type of clock signal. The diagram of negative edge triggering is given below.
FLIP -FLOP

A flip flop is an electronic circuit with two stable states that can be used to
store binary data. The stored data can be changed by applying varying inputs.
Flip-flops and latches are fundamental building blocks of digital electronics
systems used in computers, communications, and many other types of
systems. Flip-flops and latches are used as data storage elements. It is the
basic storage element in sequential logic. But first, let’s clarify the difference
between a latch and a flip-flop.

Flip flop v/s Latch

The basic difference between a latch and a flip-flop is a gating or clocking
mechanism.

Read the full comparison of Flip Flop v/s latch here

For example, let us talk about SR latch and SR flip-flops. In this circuit when
you Set S as active the output Q would be high and Q’ will be low. This is
irrespective of anything else. (This is an active-low circuit so active here means
low, but for an active high circuit active would mean high)

A flip flop, on the other hand, is synchronous and is also known as gated or
clocked SR latch.

SR Flip-Flop
In this circuit diagram, the output is changed (i.e. the stored data is changed)
only when you give an active clock signal. Otherwise, even if the S or R is
active the data will not change. Let’s look at the types of flip-flops to
understand better.

SR Flip Flop
The SR flip flop is a 1-bit memory bistable device having two inputs, i.e., SET and
RESET. The SET input 'S' set the device or produce the output 1, and the RESET
input 'R' reset the device or produce the output 0. The SET and RESET inputs are
labeled as S and R, respectively.

The SR flip flop stands for "Set-Reset" flip flop. The reset input is used to get back
the flip flop to its original state from the current state with an output 'Q'. This output
depends on the set and reset conditions, which is either at the logic level "0" or "1".

The NAND gate SR flip flop is a basic flip flop which provides feedback from both of
its outputs back to its opposing input. This circuit is used to store the single data bit
in the memory circuit. So, the SR flip flop has a total of three inputs, i.e., 'S' and 'R',
and current output 'Q'. This output 'Q' is related to the current history or state. The
term "flip-flop" relates to the actual operation of the device, as it can be "flipped" to
a logic set state or "flopped" back to the opposing logic reset state.

The NAND Gate SR Flip-Flop

We can implement the set-reset flip flop by connecting two cross-coupled 2-input
NAND gates together. In the SR flip flop circuit, from each output to one of the other
NAND gate inputs, feedback is connected. So, the device has two inputs, i.e., Set 'S'
and Reset 'R' with two outputs Q and Q' respectively. Below are the block diagram
and circuit diagram of the S-R flip flop.

Block Diagram:
Circuit Diagram:

The Set State

In the above diagram, when the input R is set to false or 0 and the input S is set to
true or 1, the NAND gate Y has an input 0, which will produce the output Q' 1. The
value of Q' is faded to the NAND gate 'X' as input 'A', and now both the inputs of the
NAND gate 'X' are 1(S=A=1), which will produce the output 'Q' 0.

Now, if the input R is changed to 1 with 'S' remaining 1, the inputs of NAND gate 'Y'
is R=1 and B=0. Here, one of the inputs is also 0, so the output of Q' is 1. So, the
flip flop circuit is set or latched with Q=0 and Q'=1.

Reset State
The output Q' is 0, and output Q is 1 in the second stable state. It is given by R =1
and S = 0. One of the inputs of NAND gate 'X' is 0, and its output Q is 1. Output Q is
faded to NAND gate Y as input B. So, both the inputs to NAND gate Y are set to 1,
therefore, Q' = 0.

Now, if the input S is changed to 0 with 'R' remaining 1, the output Q' will be 0 and
there is no change in state. So, the reset state of the flip flop circuit has been
latched, and the set/reset actions are defined in the following truth table:
From the above truth table, we can see that when set 'S' and reset 'R' inputs are set
to 1, the outputs Q and Q' will be either 1 or 0. These outputs depend on the input
state S or R before the input condition exist. So, when the inputs are 1, the states of
the outputs remain unchanged.

The condition in which both the inputs states are set to 0 is treated as invalid and
must be avoided.

JK Flip Flop
The SR Flip Flop or Set-Reset flip flop has lots of advantages. But, it has the
following switching problems:

o When Set 'S' and Reset 'R' inputs are set to 0, this condition is always
avoided.

o When the Set or Reset input changes their state while the enable input is 1,
the incorrect latching action occurs.

The JK Flip Flop removes these two drawbacks of SR Flip Flop.

The JK flip flop is one of the most used flip flops in digital circuits. The JK flip flop is
a universal flip flop having two inputs 'J' and 'K'. In SR flip flop, the 'S' and 'R' are
the shortened abbreviated letters for Set and Reset, but J and K are not. The J and
K are themselves autonomous letters which are chosen to distinguish the flip flop
design from other types.

The JK flip flop work in the same way as the SR flip flop work. The JK flip flop has 'J'
and 'K' flip flop instead of 'S' and 'R'. The only difference between JK flip flop and SR
flip flop is that when both inputs of SR flip flop is set to 1, the circuit produces the
invalid states as outputs, but in case of JK flip flop, there are no invalid states even
if both 'J' and 'K' flip flops are set to 1.
The JK Flip Flop is a gated SR flip-flop having the addition of a clock input circuitry.
The invalid or illegal output condition occurs when both of the inputs are set to 1
and are prevented by the addition of a clock input circuit. So, the JK flip-flop has
four possible input combinations, i.e., 1, 0, "no change" and "toggle". The symbol of
JK flip flop is the same as SR Bistable Latch except for the addition of a clock
input.

Block Diagram:

Circuit Diagram:

In SR flip flop, both the inputs 'S' and 'R' are replaced by two inputs J and K. It
means the J and K input equates to S and R, respectively.

The two 2-input AND gates are replaced by two 3-input NAND gates. The third input
of each gate is connected to the outputs at Q and Q'. The cross-coupling of the SR
flip-flop permits the previous invalid condition of (S = "1", R = "1") to be used to
produce the "toggle action" as the two inputs are now interlocked.
If the circuit is "set", the J input is interrupted from the "0" position of Q' through
the lower NAND gate. If the circuit is "RESET", K input is interrupted from 0
positions of Q through the upper NAND gate. Since Q and Q' are always different, we
can use them to control the input. When both inputs 'J' and 'K' are set to 1, the JK
toggles the flip flop as per the given truth table.

Truth Table:

When both of the inputs of JK flip flop are set to 1 and clock input is also pulse
"High" then from the SET state to a RESET state, the circuit will be toggled. The JK
flip flop work as a T-type toggle flip flop when both of its inputs are set to 1.

The JK flip flop is an improved clocked SR flip flop. But it still suffers from
the "race" problem. This problem occurs when the state of the output Q is changed
before the clock input's timing pulse has time to go "Off". We have to keep short
timing plus period (T) for avoiding this period.

D Flip Flop
In SR NAND Gate Bistable circuit, the undefined input condition of SET = "0" and
RESET = "0" is forbidden. It is the drawback of the SR flip flop. This state:

1. Override the feedback latching action.

2. Force both outputs to be 1.

3. Lose the control by the input, which first goes to 1, and the other input
remains "0" by which the resulting state of the latch is controlled.

We need an inverter to prevent this from happening. We connect the inverter

between the Set and Reset inputs for producing another type of flip flop circuit
called D flip flop, Delay flip flop, D-type Bistable, D-type flip flop.

The D flip flop is the most important flip flop from other clocked types. It ensures
that at the same time, both the inputs, i.e., S and R, are never equal to 1. The
Delay flip-flop is designed using a gated SR flip-flop with an inverter connected
between the inputs allowing for a single input D(Data).
This single data input, which is labeled as "D" used in place of the "Set" input and
for the complementary "Reset" input, the inverter is used. Thus, the level-sensitive
D-type or D flip flop is constructed from a level-sensitive SR flip flop.

So, here S=D and R= ~D(complement of D)

Block Diagram

Circuit Diagram

We know that the SR flip-flop requires two inputs, i.e., one to "SET" the output and
another to "RESET" the output. By using an inverter, we can set and reset the
outputs with only one input as now the two input signals complement each other. In
SR flip flop, when both the inputs are 0, that state is no longer possible. It is an
ambiguity that is removed by the complement in D-flip flop.

In D flip flop, the single input "D" is referred to as the "Data" input. When the data
input is set to 1, the flip flop would be set, and when it is set to 0, the flip flop would
change and become reset. However, this would be pointless since the output of the
flip flop would always change on every pulse applied to this data input.
The "CLOCK" or "ENABLE" input is used to avoid this for isolating the data input from
the flip flop's latching circuitry. When the clock input is set to true, the D input
condition is only copied to the output Q. This forms the basis of another sequential
device referred to as D Flip Flop.

When the clock input is set to 1, the "set" and "reset" inputs of the flip-flop are both
set to 1. So it will not change the state and store the data present on its output
before the clock transition occurred. In simple words, the output is "latched" at
either 0 or 1.

Truth Table for the D-type Flip Flop

Symbols ↓ and ↑ indicates the direction of the clock pulse. D-type flip flop assumed
these symbols as edge-triggers.

Master-Slave JK Flip Flop

In "JK Flip Flop", when both the inputs and CLK set to 1 for a long time, then Q
output toggle until the CLK is 1. Thus, the uncertain or unreliable output produces.
This problem is referred to as a race-round condition in JK flip-flop and avoided by
ensuring that the CLK set to 1 only for a very short time.

Explanation
The master-slave flip flop is constructed by combining two JK flip flops. These flip
flops are connected in a series configuration. In these two flip flops, the 1st flip flop
work as "master", called the master flip flop, and the 2nd work as a "slave", called
slave flip flop. The master-slave flip flop is designed in such a way that the output of
the "master" flip flop is passed to both the inputs of the "slave" flip flop. The output
of the "slave" flip flop is passed to inputs of the master flip flop.

In "master-slave flip flop", apart from these two flip flops, an inverter or NOT gate is
also used. For passing the inverted clock pulse to the "slave" flip flop, the inverter is
connected to the clock's pulse. In simple words, when CP set to false for "master",
then CP is set to true for "slave", and when CP set to true for "master", then CP is
set to false for "slave".
Working:
o When the clock pulse is true, the slave flip flop will be in the isolated state,
and the system's state may be affected by the J and K inputs. The "slave"
remains isolated until the CP is 1. When the CP set to 0, the master flip-flop
passes the information to the slave flip flop to obtain the output.

o The master flip flop responds first from the slave because the master flip flop
is the positive level trigger, and the slave flip flop is the negative level trigger.

o The output Q'=1 of the master flip flop is passed to the slave flip flop as an
input K when the input J set to 0 and K set to 1. The clock forces the slave
flip flop to work as reset, and then the slave copies the master flip flop.

o When J=1, and K=0, the output Q=1 is passed to the J input of the slave. The
clock's negative transition sets the slave and copies the master.

o The master flip flop toggles on the clock's positive transition when the inputs
J and K set to 1. At that time, the slave flip flop toggles on the clock's
negative transition.
 o The flip flop will be disabled, and Q remains unchanged when both the inputs
of the JK flip flop set to 0.

Timing Diagram of a Master Flip Flop:

o When the clock pulse set to 1, the output of the master flip flop will be one
until the clock input remains 0.

o When the clock pulse becomes high again, then the master's output is 0,
which will be set to 1 when the clock becomes one again.

o The master flip flop is operational when the clock pulse is 1. The slave's
output remains 0 until the clock is not set to 0 because the slave flip flop is
not operational.

o The slave flip flop is operational when the clock pulse is 0. The output of the
master remains one until the clock is not set to 0 again.

o Toggling occurs during the entire process because the output changes once in
the cycle.