Combinational circuits
Decoder
Decoder
• A Decoder is a combinational circuit that converts
binary information from ‘N’ input lines to a
maximum of 2N unique output lines.
• One of these outputs will be active High based on
the combination of inputs present, when the
decoder is enabled.
• That means decoder detects a particular code.
• The outputs of the decoder are nothing but the
minterms of ‘N’ input variables lines, when it is
enabled.
Decoder
• If the N-bit decoded information has unused
or don’t care combination, the decoder
output will have fewer than 2N output.
Block diagram of Decoder
2-to-4 Binary Decoders
• In the 2 to 4 line decoder, there is a total of
two inputs, i.e. A and B and four outputs, i.e.,
Q0, Q1, Q2, and Q3.
• Each output represents one of the minterms
of the 2 input variables, (each output = a
minterm).
2-to-4 Binary Decoders
Boolean expression
The output values will be:
Q0=A’B’
Q1=A’B
Q2=AB’
Q3=AB
Logic diagram
2 to 4 Decoder with Enable input
Let 2 to 4 Decoder has two inputs A1 & A0 and
four outputs Y3, Y2, Y1 & Y0. The block diagram
of 2 to 4 decoder is shown in the following
figure.
One of these four outputs will be ‘1’ for each
combination of inputs when enable, E is ‘1’.
The Truth table of 2 to 4 decoder is shown
below.
Boolean expression
From Truth table, we can write the Boolean
functions for each output as
Y3=E.A1.A0
Y2=E.A1.A0ʹ
Y1=E.A1ʹ.A0
Y0=E.A1ʹ.A0ʹ
Logic diagram
3-to-8 Decoder
• A 3-to-8 decoder has three inputs (A, B, C) and
eight outputs (D0 to D7 ).
• Based on the 3 inputs, one of the eight
outputs is selected.
Truth table of 3-to-8 decoder
Boolean expression
• From the truth table, it is clear that only one
of eight outputs (D0 to D7 ) is selected based
on the three select inputs.
• From the truth table, the logic expressions for
the outputs can be written as follows:
• Enable inputs: Some decoders have one or
more enable inputs which are used to control
the operation of the decoder.
• With the enable line held HIGH, the decoder
functions normally and the input code, A, B
and C will determine which output is HIGH.
• Hence, the decoder is enabled only if the
enable line is HIGH.
Logic diagram of 3-to-8 decoder
Decoder Application
• Decoders are widely used in memory systems
of computers, where they respond to the
address code input from the central processor
to activate the memory storage location
specified by the address code.
Implementation of Higher-order
Decoders
3 to 8 Decoder using 2 to 4 Decoder:
We know that 2 to 4 Decoder has two inputs,
A1 & A0 and four outputs, Y3 to Y0.
Whereas, 3 to 8 Decoder has three inputs A2, A1
& A0 and eight outputs, Y7 to Y0.
the number of lower order decoders required for implementing
higher order decoder using the following formula.
Required number of lower order decoders=m2/m1
Where,
m1 is the number of outputs of lower order decoder.
m2 is the number of outputs of higher order decoder.
Here, m1 = 4 and m2 = 8. Substitute, these two values in the above
formula.
Required number of 2 to 4 decoders=8/4=2
we require two 2 to 4 decoders for implementing one 3 to
8 decoder. The block diagram of 3 to 8 decoder using 2 to
4 decoders
• The parallel inputs A1 & A0 are applied to each 2
to 4 decoder.
• The complement of input A2 is connected to
Enable, E of lower 2 to 4 decoder in order to get
the outputs, Y3 to Y0.
• These are the lower four minterms.
• The input, A2 is directly connected to Enable, E of
upper 2 to 4 decoder in order to get the outputs,
Y7 to Y4.
• These are the higher four minterms.
4 to 16 decoder using 3 to 8 decoders
3 to 8 Decoder has three inputs A2, A1 & A0 and
eight outputs, Y7 to Y0.
Whereas, 4 to 16 Decoder has four inputs A3, A2, A1
& A0 and sixteen outputs, Y15 to Y0.
the number of lower order decoders required.
Required number of lower order decoders=m2/m1
Substitute, m1 = 8 and m2 = 16 in the above
formula.
Required number of 3 to 8 decoders=16/8=2
The block diagram of 4 to 16 decoder
using 3 to 8 decoders
• The parallel inputs A2, A1 & A0 are applied to
each 3 to 8 decoder.
• The complement of input, A3 is connected to
Enable, E of lower 3 to 8 decoder in order to
get the outputs, Y7 to Y0.
• These are the lower eight min terms.
• The input, A3 is directly connected to Enable,
E of upper 3 to 8 decoder in order to get the
outputs, Y15 to Y8.
• These are the higher eight min terms.
Design a full adder using 3:8 decoder
• i. The A, B and Cin inputs are applied to 3:8
decoder as an input.
• ii. The outputs of decoder m1, m2, m4 and m7
are applied to OR gate as shown in figure to
obtain the sum output.
• iii. Similarly outputs m3, m5, m6 and m7 are
applied to another OR gate to obtain the carry
output.
• iv. Implement of full adder is shown in figure1.
Design the full subtractor with using
Decoder
• For the different functions in the truth table,
the minterms can be written as 1,2,4,7, and
similarly, for the borrow, the minterms can be
written as 1,2,3,7.
• Since there are three inputs and a total of
eight minterms. So we need 3-to-8 line
decoder.