65W LED Lightning:

Over all efficiency =90% @ Vac = 90Vac

Universal input (Vin=90 to 264 Vac)

Output voltage range= 36 to 48V

Max output current = 1.35 A

Line/ main frequency is= 230 Vac @ 50 Hz

PFC Controller Designing

Questuin 1: How we can design a EMI filter for input.

1. The filter capacitor must be large enough to have a relatively low ripple
superimposed on the DC level. This means that the instantaneous line voltage is
below the voltage on the capacitor most of the time, thus the rectifiers conduct only
for a small portion of each line half-cycle.
2. The current drawn from the mains is then a series of narrow pulses whose
amplitude is 5-10 times higher than the resulting DC value.

Drawback:
A much higher peak and RMS current down from the line, distortion of the AC line voltage,
overcurrents in the neutral line of the three-phase systems and, consequently, a poor utilization of
the power system's energy capability.

This can be measured in terms of either total harmonic distortion (THD), as norms provide for, or
power factor (PF).

Intended as the ratio between the real power (the one transferred to the output) and the apparent
power (RMS line voltage times RMS line current) drawn from the mains, which is more immediate.

A traditional input stage with capacitive filter has a low PF (0.5-0.7) and a high THD (>100%).

Why need to use PFC controller:

1. It located between the rectifier bridge and the filter capacitor, allows drawing a
quasi-sinusoidal current from the mains, in phase with the line voltage.
2. The PF becomes very close to 1 (more than 0.99 is possible) and the previously
mentioned drawbacks are eliminated.
Why need to use boost topology in PFC controller:
1. Primarily because the circuit requires the fewest external parts (low-cost solution).
2. The boost inductor located between the bridge and the switch causes the input di/dt
to be low, thus minimizing the noise generated at the input and, therefore, the
requirements on the input EMI filter.
3. The switch is source-grounded, therefore easy to drive.

However, boost topology requires the DC output voltage to be higher than the maximum expected
line peak voltage (400 VDC is a typical value for 230 V or wide-range mains applications).
Drawback:
There is no isolation between the input and output, thus any line voltage surge is passed on to the
output.

Why need to use L6562A IC in PFC controller:

Two methods of controlling a PFC preregulator are currently widely used:

The fixed frequency average current mode PWM (FF PWM):

1. The first method needs a complex control that requires a sophisticated controller IC
(ST's L4981A, with the variant of the frequency modulation offered by the L4981B)
and a considerable component count.
2. In this method the boost inductor works in continuous conduction mode.
The transition mode (TM) PWM (fixed ON-time, variable frequency:
It is a requires a simpler control (implemented by ST's L6562A), much fewer external parts and is
therefore much less expensive.

It makes the inductor work on the boundary between continuous and discontinuous mode, by
definition.

For a given throughput power, TM operation involves higher peak currents. This, also consistently
with cost considerations, suggests its use in a lower power range (typically below 200 W).

TM PFC operation (boost topology):

1. The AC mains voltage is rectified by a bridge and the rectified voltage is delivered
to the boost converter. This, using a switching technique, boosts the rectified input
voltage to a regulated DC output voltage (Vo).
2. The boost converter consists of a boost inductor (L), a controlled power switch (Q),
a catch diode (D), an output capacitor (Co).
3. The goal is to shape the input current in a sinusoidal fashion, in phase with the input
sinusoidal voltage. To do this the L6562A uses the transition mode technique.

IC working steps:
1. The error amplifier compares a partition of the output voltage of the boost converter
with an internal reference, generating an error signal proportional to the difference
between them. If the bandwidth of the error amplifier is narrow enough (below 20
Hz), the error signal is a DC value over a given half-cycle.
2. The error signal is fed into the multiplier block and multiplied by a partition of the
rectified mains voltage. The result is a rectified sinusoid whose peak amplitude
depends on the mains peak voltage and the value of the error signal.
3. The output of the multiplier is in turn fed into the (+) input of the current comparator,
thus it represents a sinusoidal reference for PWM.
4. In fact, as the voltage on the current sense pin (instantaneous inductor current
times the sense resistor) equals the value on the (+) of the current comparator, the
conduction of the MOSFET is terminated. As a consequence, the peak inductor
current is enveloped by a rectified sinusoid.
5. TM control causes a constant ON-time operation over each line half-cycle.
6. After the MOSFET has been turned off, the boost inductor discharges its energy
into the load until its current goes to zero. The boost inductor has now run out of
energy, the drain node is floating and the inductor resonates with the total
capacitance of the drain. The drain voltage drops rapidly below the instantaneous
line voltage and the signal on ZCD drives the MOSFET on again and another
conversion cycle starts.
7. This low voltage across the MOSFET at turn-on reduces both the switching losses
and the total drain capacitance energy that is dissipated inside the MOSFET.
8. The resulting inductor current and the timing intervals of the MOSFET are shown:
By geometric relationships, the average input current (the one which is drawn from the mains) is just
one-half of the peak inductor current waveform.

The system operates not exactly on, but very close to, the boundary between continuous and
discontinuous current mode and that is why this system is called a transition mode PFC.
Grawbacks of Transistion mode:

1. this system minimizes the inductor size due to the low inductance value needed. On
the other hand, the high current ripple on the inductor involves high RMS current
and high noise on the rectified main bus, which needs a heavier EMI filter to be
rejected.
2. These drawbacks limit the use of the TM PFC to lower power range applications.

Designing of a TM PFC
1. Mains voltage range (Vac rms): Vac_min= 90V; Vac_max=264
2. Minimum mains frequency: fL=50 Hz (for wrost case it would be 63Hz) %always
considers the wrost case ( Min=47 Hz, Typical= 50Hz, Max=63 Hz)
 3. Rated output power: P_out= 65W

PFC is a boost topology the regulated output voltage depends strongly on the maximum AC input
voltage.

Boost correct operation the output voltage must always be higher than the input.

clc;
close all;
clear all;
%------------------------------------------------------------------------
------------------------------------
Vac_max=264;
V_pk=sqrt(2)*Vac_max

Output voltage must be set 6/7% higher than the maximum input voltage peak.

Percentage=0.07*V_pk
V_out=V_pk+Percentage

DC Regulated output voltage:

V_out=400V

The target efficiency and PF are set here at minimum input voltage and maximum load. They are
used for the following operating condition calculations of the PFC. Of course at high input voltage the
efficiency is higher.

Over all efficiency =90% @ Vac = 90Vac

Expected power factor: PF=0.99 (Assumed for this application)

Because of the narrow loop voltage bandwidth, the PFC output can face overvoltages at startup or in
case of load transients. To prevent from excessive output voltage that can overstress the output
components and the load, the L6562A integrates an OVP. The overvoltage protection sets the extra
voltage overimposed at Vout:

Maximum output overvoltage (Vdc): Del_OVP=55V

A certain holdup capability in case of mains dips can be requested of the PFC in which case the
output capacitor must also be dimensioned, taking into account the required minimum voltage value
(Vout_min) after the elapsed holdup time (t_Hold).

1. Minimum output voltage after line drop (Vdc): Vout_min=300V (A drope in starting)
2. Holdup capability (ms): t_Hold = 10 ms

the switching frequency must be higher than the audio bandwidth in order to avoid audible noise and
additionally it must not interfere with the L6562A minimum internal starter period, as given in the
datasheet. On the other hand, if the minimum frequency is set too high, the circuit shows excessive
losses at a higher input voltage and probably operates skipping switching cycles not only at light
load.

1. Minimum switching frequency (kHz): 35kHz

2. Maximum ambient temperature (°C):T_A=50C

Operating condition:
[Link] DC output current:
P_out=65W

V_out=400V
P_out=65;
V_out=400
I_out=P_out/V_out

I_out=0.1625 A= 0.163A

2. Maximum input power:

Over all efficiency =90% @ Vac = 90Vac

P_out=65W
Efficiency=0.9;
P_in=P_out/Efficiency
P_in=72.2

P_in=72.2W

3. RMS input current:

P_in=72.2W

VAC_min=90V

Assume Power factor (PF)=0.99

VAC_min=90;
PF=0.99;
I_in=P_in/(VAC_min*PF)
I_in =0.81

I_in =0.81A
4. Peak inductor current:

I_in =0.81A
IL_pk=2*sqrt(2)*I_in
IL_pk=2.29

IL_pk=2.29A

inductor current is a triangle shape at switching frequency, and the peak of triangle is twice its
average value. The average value of the inductor current is exactly the peak of the input sine wave
current, and therefore it can be easily calculated as its rms value is obtained from equatio.

Questuin 2: I dont understand why the average value

of the inductor current is exactly the peak of the input
sine wave current.
The average value of the inductor current can be easily calculated as its rms value.

5. RMS inductor current:

IL_rms=(2/sqrt(3))*I_in
IL_rms=0.94

IL_rms=0.94A

6. AC inductor current:

IL_ac=sqrt((IL_rms)^2-(I_in)^2)
IL_ac=0.48

IL_ac=0.48A

The current flowing in the inductor can be split in two parts, depending on the instant of conduction.
During the on time, the current increases from zero up to the peak value and circulates into the
switch, while during the following off-time the current decreases from peak down to zero and
circulates into the diode.

Therefore there is a current with a triangular wave, with the same peak value equal to the inductor
current flowing into these two components.

7. RMS switch current:

IL_pk=2.29A

Vac_min=90V

V_out=400V
Isw_rms=IL_pk*sqrt((1/6)-((4*sqrt(2))/(9*pi))*(VAC_min/V_out))
Isw_rms=0.8

Isw_rms=0.8A

8. RMS diode current:

IL_pk=2.29A

Vac_min=90V

V_out=400V
Id_rms=IL_pk*sqrt(((4*sqrt(2)/(9*pi)))*(VAC_min/V_out))
Id_rms=0.49

Id_rms=0.49A

Power section design

Bridge rectifier
The input rectifier bridge can use standard, slow-recovery, low-cost devices. Typically a 600 V
device is selected in order to have good margin against mains surges.

Question No.3: Why need to use negative temprature

cofficient (NTC) at output.
An NTC resistor limiting the current at plug-in is required to avoid overstress to the rectifier bridge
and fuse.

The rectifier bridge power dissipation:

I have choosed the rectifier model "Enhanced isoCink+TM Bridge Rectifiers"
Find the dynamic resistance of the bridge rectifier at highest temprature= TA=150C

User the ohm law at Vf= 0.8V we have a current If approximatly = 12A

Vf=0.8;
If=12;
R_d=Vf/If
R_d=0.07

R_d=0.07 Ohms

1. Input RMS current:

I_in =0.81A
Iin_rms=(sqrt(2)*I_in)/2
Iin_rms=0.6

Iin_rms=0.6A

2. Input Average current

I_in =0.81A
Iin_avg= (sqrt(2)*I_in)/pi
Iin_avg=0.4

Iin_avg=0.4A
3. The power dissipated on the bridge is:

R_d=0.07 Ohms

Iin_rms=0.6A

Iin_avg=0.4A

Vth =1V at (Ta=125C) %always consider the wrost case

Vth =1;
P_bridge=(4*R_d*(Iin_rms)^2)+(4*Vth*Iin_avg)
P_bridge=1.7

P_bridge=1.7W

Calculations of Input capacitor:

The input high-frequency filter capacitor (Cin) has to attenuate the switching noise due to the high-
frequency inductor current ripple (twice the average line current. The worst conditions occur at the
peak of the minimum rated input voltage. The maximum high-frequency voltage ripple across Cin is
usually imposed between 5% and 20% of the minimum rated input voltage. This is expressed by a
coefficient r (from 0.05 to 0.2) as an input design parameter:

Ripple voltage coefficient (%)=r=0.2 (20% of the minimum input voltage)

Minimum switching frequency= 35 KHz

Vac_min=90V

I_in =0.81A
r=0.2;
fsw_min=35e3;
C_in=(I_in)/(2*pi*fsw_min*r*VAC_min)
C_in=0.205*10^-6

C_in=0.205*10^-6
In real conditions the input capacitance is designed taking the EMI filter into account and a tolerance
on the component of about 5% -10% (typical for polyester capacitors)
Cin_5=C_in*0.05;
Cin_10=C_in*0.1;
C_in-Cin_5
C_in+Cin_5
C_in-Cin_10
C_in+Cin_10

C_in=0.22 uF (+10%)

A bigger capacitor provides a benefit from the EMI point of view but worsens the THD, especially at
high mains. Therefore a compromise must be found between these two parameters. A good quality
film capacitor for this component must be selected in order to provide good filtering effectiveness.

Calculations of Over voltage protection:

Under steady-state conditions, the voltage control loop keeps the output voltage Vo of a PFC pre-
regulator close to its nominal value, set by the resistors R1 and R2 of the output divider. Neglecting
ripple components, the current through R1, IR1, equals that through R2, IR2. Considering that the
non-inverting input of the error amplifier is internally referenced at 2.5V, also the voltage at pin INV
will be 2.5V.

If the output voltage experiences an abrupt change ∆Vo > 0 due to a load drop, the voltage at pin
INV will be kept at 2.5V by the local feedback of the error amplifier, a network connected between
pins INV and COMP that introduces a long time constant to achieve high PF (this is why ∆Vo can be
large). As a result, the current through R2 will remain equal to 2.5/R2 but that through R1 will
become:

The difference current ∆IR1=I'R1-IR2=I'R1-IR1= ∆Vo/R1 will flow through the compensation network
and enter the error amplifier output (pin COMP). This current is monitored inside the device and if it
reaches about 24µA the output voltage of the multiplier is forced to decrease, thus smoothly
reducing the energy delivered to the output. As the current exceeds 27µA, the OVP is triggered
(Dynamic OVP): the gate-drive is forced low to switch off the external power transistor and the IC put
in an idle state. This condition is maintained until the current falls below approximately 7µA, which
re-enables the internal starter and allows switching to restart. The output ∆Vo that is able to trigger
the Dynamic OVP function is then:

Del_V0=40V

Taking dynamic over voltage trigering current=27uH

So, R1 would be:

Del_V_out=40;
I_OVT=27e-6;
R1=Del_V_out/I_OVT
Del_V_out=R1*20e-6

R1=1.5 MHz

Del_V_out=30V

1. Maximum output low-frequency ripple: Del_V_out=30V

2. R2 would be:

R2=(R1*2.5)/(V_out-2.5)

R2=9.32 kHz

Calculations of Output capacitor:

The output bulk capacitor (Co) selection depends on the following
factors:Del_V_out=30VDel_V_out=30V
 1. DC output voltage=400V
2. Holdup capability (ms): t_Hold = 16 ms w.r.t 63Hz

Holdup capability (ms): t_Hold = 16 ms w.r.t 63Hz

Output power=P_out=65W

Output voltage=V_out=400V

Out put capacitance would be:

f_L=63;
C_out=P_out/(2*pi*f_L*V_out*Del_V_out)
C_out=13.9e-6

C_out=13.9e-6F

Although ESR usually does not affect the output ripple, it should be taken into account for power loss
calculations. The total RMS capacitor ripple current, including mains frequency and switching
frequency components, is:

Ic_rms=sqrt((Id_rms)^2-(I_out)^2)
Ic_rms=0.46

Ic_rms=0.46 A

If the PFC stage has to guarantee a specified holdup time, the selection criterion of the capacitance
changes. CO has to deliver the output power for a certain time (tHold) with a specified maximum
dropout voltage (Vout min) which is the minimum output voltage value (which takes load regulation
and output ripple into account). Vout min is the minimum output operating voltage before the 'power
fail' detection and consequent stopping by the downstream system supplied by the PFC.
f_L=63;
t_hold=1/f_L
Vout_min=300
C_out=(2*P_out*t_hold)/((V_out-Del_V_out)^2-(Vout_min)^2)
C_out=44e-6

A 20% tolerance on the electrolytic capacitors has to be taken into account for the right
dimensioning.

tolerance=8.81uF

C_out=53uF
C_out=53e-6

Holdup capability at C_out=53uF:

t_hold=(C_out*((V_out-Del_V_out)^2-(Vout_min)^2))/(2*P_out)

t_hold=19ms

Ripple variation on the output:

Del_V_out=I_out/(2*pi*f_L*C_out)

Del_V_out=7.75V

Boost inductor:
The boost inductor determines the working frequency of the [Link] is usually calculated so that
the minimum switching frequency is greater than the maximum frequency of the L6562A internal
starter (190 µs)=5.3kHz, to ensure a correct TM operation. Assuming unity PF, it is possible to write:

The absolute minimum frequency fswmin can occur at either the maximum VACmax or the minimum
mains voltage VACmin, thus the inductor value is defined by the formula:

L_vac_min=((VAC_min)^2*(V_out-(sqrt(2)*VAC_min)))/(2*fsw_min*P_in*V_out)
L_vac_min=1.1e-3

L_vac_min=1.1mH
L_vac_max=((Vac_max)^2*(V_out-(sqrt(2)*Vac_max)))/(2*fsw_min*P_in*V_out)
L_vac_max=0.92e-3

L_vac_max=0.92mH

For this application L=1.1mH boost inductance has been selected.

Calculations of minimum fsw_min:

fsw_min=((VAC_min)^2*(V_out-(sqrt(2)*VAC_min)))/(2*L_vac_min*P_in*V_out)
fsw_min=35e3;

By L=1.1mH we verifies ouer minim switching frequency that was fsw_min=35kHz..

Inductor L=1.1mH turns calculation;

Ae = 189 mm2

N87 B_max=390mT
B_80=(390e-3)*0.8
B_80=312e-3

B_80=312mT

The internal current sense clamping sets the maximum current that can flow in the inductor, the
maximum peak of the inductor current is calculated considering the maximum voltage Vcsmax
allowed on the L6562A (in the datasheet):

Sense resistor value (Rs) can be calculated as follows.

For the 65 W PFC it is:

Vcs_min=1.0V

IL_pk=2.29A
Vcs_min=1.0;
Rs=Vcs_min/IL_pk

It should be less than so we select Rs=0.39 Ohm.

Vcs_max=1.16V
Vcs_max=1.16
Rs=0.39
I_pk=Vcs_max/0.39
I_pk=2.8

I_pk=2.8A
A_e=189e-6
N_L=((L_vac_min)*I_pk)/(B_80*A_e)

N_L=52 Turns

Power MOSFET selection and dissipation:

RDS(on), which depends on the output power (3), since the breakdown voltage is fixed just by the
output voltage (4), plus the overvoltage admitted (7) and a safety margin (20%). Thus, a voltage
rating of 500 V (1.2 · Vout = 480 V) is selected.

Using its current rating as a rule of thumb, we can select a device having ~ 3 times the RMS switch
current.
I_mosfet=3*Isw_rms

The conduction losses at maximum load and minimum input voltage are calculated by:

Because normally in the datasheets RDS(on) is given at ambient temperature (25°C) to calculate
correctly the conduction losses at 100 °C (typical MOSFET junction operating temperature) a factor
of 1.75 to 2 should be taken into account. The exact factor can be found in the device datasheet.
Now, the conduction losses normalized to 1Ω RDS(on) at ambient temperature as a function of Pin
and VAC can be calculated, combining equations:

P_cond=2*(Isw_rms)^2
P_cond=1.3

P_cond=1.3W
Fall time=t_f=6ns (Typical value)

Vmos=550V

Imos=8A

fsw=35kHz
t_f=6e-9;
V_mos=550;
I_mos=8;
P_switch=V_mos*I_mos*t_f*fsw_min
P_switch=0.9

P_switch=0.9W

At turn-on the losses are due to the discharge of the total drain capacitance inside the MOSFET
itself. In general, the capacitive losses are given by:

C_d=50e-12;
P_cap=(1/2)*C_d*(V_mos)^2*fsw_min
P_cap=0.3

P_cap=0.3W

R_dson=1;
P_loss=(R_dson*P_cond)+(((t_f)^2/C_d)*P_switch)+(C_d*P_cap)

1. Maximum ambient temperature (°C):T_A=50C

2. Maximum total losses occurs at VACmin which is 1.3 W
R_th=(125-50)/P_loss

Rth= 58 Ohm

Diode Selection Calculations:

A minimum breakdown voltage of 1.2·(Vout + ΔVovp) and a current rating higher than 3·Iout
Vth_diode=1.2*(V_out+55)
If_diode=3*I_out

From the STTH1L06 datasheet, Vth is 0.89 V and Rd is 0.165 Ω

Vth_diode=0.89
R_diode=0.165
P_diode=(Vth_diode*I_out)+(R_diode*(Id_rms)^2)
Rdiode_th=(125-50)/P_diode

L6562A biasing circuitry:

1. Pin 1 (INV):
This pin is connected both to the inverting input of the E/A and to the DIS circuitry. A resistive divider
is connected between the boost regulated output voltage and this pin. The internal reference on the
non-inverting input of the E/A is 2.5 V (typ), while the DIS intervention threshold is 27 µA (typ).
RoutH and RoutL are then selected as follows:
 1. Maximum output over voltahe=Del_OVP=55V
2. Dynamic OVP triggering current=Iovp=27uA

Del_OVP=55;
Iovp=27e-6;
RoH=Del_OVP/Iovp

RoH=2 MOhm

Two series 1M resistoes for RoL 2 MOhm. RoutH a resistor with a suitable voltage rating (>400 V) is
needed

Ratio=(V_out/2.5)-1

Ratio=159.

RoL=RoH/Ratio

RoL=13 kOhm

RoutL = 15 kΩ in parallel to a 82 kΩ.

2. Pin 2 (COMP):
This pin is the output of the E/A that is fed to one of the two inputs of the multiplier. A feedback
compensation network is placed between this pin and INV (1). It has to be designed with a narrow
bandwidth in order to avoid that the system rejects the output voltage ripple (100 Hz) that would
bring high distortion of the input current waveform. A simple criterion to define the capacitance value
is to set the bandwidth (BW) from 20 to 30 Hz. The compensation network can be just a capacitor,
providing a low-frequency pole as well as a high DC gain. A more complex network, typically a type-
II CRC network providing 2 poles and a zero, is more suitable for constant power loads like a
downstream converter. In case a single capacitor is used, it can be dimensioned using the following
formulas:
Zt=(1/RoH)+(1/RoL);
Zth=1/Zt

For this 65W W TM PFC, a CRC network providing two poles and a zero has been implemented,
using the following values:

1. CcompP= 150nF
2. CcomS=2.2uF
3. RcompS=22k Ohm

Question: Need to ask professor how can I make

compensation circuit.

3. Pin 4 (CS):
The pin #4 is the inverting input of the current sense comparator. Through this pin, the L6562A
senses the instantaneous inductor current, converted to a proportional voltage by an external sense
resistor (Rs). As this signal crosses the threshold set by the multiplier output, the PWM latch is reset
and the power MOSFET is turned off. The MOSFET stays in OFF-state until the PWM latch is reset
by the ZCD signal. The pin is equipped with 200 ns leading-edge blanking to improve noise
immunity. The sense resistor value (Rs) can be calculated as follows. For the 65W PFC it is:

Vcs_min=1.0V

IL_pk=2.29A
Vcs_min=1.0;
Rs=Vcs_min/IL_pk

It should be less than so we select Rs=0.39 Ohm.

Vcs_max=1.16V
Vcs_max=1.16
Rs=0.39
I_pk=Vcs_max/0.39
I_pk=2.8

I_pk=2.8A

The calculated ILpkx is the limit at which the boost inductor saturates and it is used for calculating
the inductor number of turns and air gap length.

The power dissipated in Rs is given by:

P_s=Rs*(Isw_rms)^2

power dessipated by Rs=0.39 and Ps= 0.25W

According to the result two parallel resistors of 0.39 Ω with 0.25 W of power rating have been
selected.

4. Pin 3 (MULT):
The linear operation of the multiplier is guaranteed within the range 0 to 3 V of VMULT and the
range 0 to 1.16 V (typ) of Vcs, while the minimum guaranteed value of the maximum slope of the
characteristics family (typ) is:

First, the maximum peak value for VMULT, VMULTmax is selected. This value, which occurs at
maximum mains voltage, should be 3 V or nearly so in wide-range mains and less in case of single
mains. The sense resistor selected is Rs = 0.39 Ω and it is described in the paragraph concerning
pin 4 of this section. The maximum peak value, occurring at maximum mains voltage is:

Vmult_max=((IL_pk*Rs)/1.1)*(Vac_max/VAC_min)

The maximum required divider ratio is calculated as:

k_p=Vmult_max/(sqrt(2)*Vac_max)

k_p=6.4e-3

Supposing a 200 µA current flowing into the multiplier divider, the lower resistor value can be
calculated:

Rmul_L=15 kOhm
Rmul_L=15e3;
Rmul_H=((1-k_p)/k_p)*Rmul_L

In this application example RmultH = 2 MΩ and RmultL = 15 kΩ have been selected. Please note
that for RmultH a resistor with a suitable voltage rating (>400 V) is needed, or more resistors in
series must be used.

The voltage on the multiplier pin with the selected component values recalculated is 0.89 V at
minimum line voltage and is 2.8 V at maximum line voltage. The multiplier works correctly within its
linear region.

5. Pin 5 (ZCD):
Pin #5 is the input of the zero current detector circuit. In transition mode PFC, the ZCD pin is
connected, through a limiting resistor, to the auxiliary winding of the boost inductor. The ZCD circuit
is negative-going edge triggered. When the voltage on the pin falls below 0.7 V, it sets the PWM
latch and the MOSFET is turned on. To do so the circuit must first be armed. Prior to falling below
0.7 V, the voltage on pin 5 must experience a positive-going edge exceeding 1.4 V (due to the
MOSFET's turnoff). The maximum main-to-auxiliary winding turn ratio, nmax, has to ensure that the
voltage delivered to the pin during the MOSFET's OFF-time is sufficient to arm the ZCD circuit. A
safe margin of 15% is added.

Total was assume that the 100% and 15% of safty margin is added and now it becomes=115=1.15

n=(V_out-(sqrt(2)*Vac_max))/(1.4*1.15)

N_auxaliry=N_L/n
N_auxaliry=3

N_auxaliry=3 turns

The minimum value of the limiting resistor can be found considering the maximum voltage across
the auxiliary winding with a selected turn ratio = 3 and assuming 0.8 mA current through the pin.

V_zcdH=5.7;
R_1=((V_out/N_auxaliry)-V_zcdH)/0.8e-3

R_1=160 kOhm
V_zcdL=0;
R_2=(((sqrt(2)*Vac_max)/N_auxaliry)-V_zcdL)/0.8e-3

R_2=156 k Ohm

R_zcd=160 kOhm

6. Pin 6 (GND):
: This pin acts as the current return both for the signal internal circuitry and for the gate drive current.
When laying out the printed circuit board, these two paths should run separately. (Most important
point in PCB designing)

7. Pin 7 (GD):
It is the output of the driver. The pin is able to drive an external MOSFET with 600 mA source and
800 mA sink capability. The high-level voltage of this pin is clamped at about 12 V to avoid
excessive gate voltages in case the pin is supplied with a high Vcc. To avoid undesired switch-on of
the external MOSFET because of some leakage current when the supply of the L6562A is below the
UVLO threshold, an internal pulldown circuit holds the pin low. The circuit guarantees 1.1 V
maximum on the pin (at Isink = 2 mA), with Vcc > Vcc_ON. This allows omitting the "bleeder" resistor
connected between the gate and the source of the external MOSFET used for this purpose.

8. Pin 8 (Vcc):
s the supply of the device. This pin is externally connected to the startup circuit (usually, one resistor
connected to the rectified mains) and to the self-supply circuit. Whatever the configuration of the
self-supply system, a capacitor is connected between this pin and ground. To start the L6562A, the
voltage must exceed the startup threshold (12.5 V typ) (Most important point in Voltage divider
circuit).

Below this value the device does not work and consumes less than 30 µA (typ) from Vcc. This allows
the use of high value startup resistors (in the hundreds kΩ), which reduces power consumption and
optimizes system efficiency at low load, especially in wide-range mains applications. When
operating, the current consumption (of the device only, not considering the gate drive current) rises
to a value depending on the operating conditions but never exceeding 3.75 mA. The device keeps
on working as long as the supply voltage is over the UVLO threshold (10.5 V max). If the Vcc voltage
exceeds 25 V, an internal clamping circuitry, is activated in order to clamp the voltage. Please
remember that during normal operation the internal clamp does not have to limit the voltage, in
which case the power consumption of the device increases considerably and its junction
temperature also increases. The suggested operating condition for safe operation of the device is
powering the L6562A with a Vcc below the minimum calmping voltage of pin 8.
The power stage of the PFC is a conventional boost converter, connected to the output of the
rectifier bridge D2. It includes the coil T1, the diode D1 and the capacitor C6. The boost switch is
represented by the power MOSFET Q1. The NTC limits the inrush current at plugin. It has been
connected on the DC rail, in series to the output electrolytic capacitor, in order to improve the
efficiency during low line operation because the rectifier RMS current is significantly lower than the
AC input current at minimum input voltage and maximum load. Even in this position the NTC limits
the surge current due to the output electrolytic capacitor as well.

Connect a ceramic capacitor (100÷470 nF) to pin #8 (Vcc) and to pin #6 (GND), close to the
L6562A. Connect this point to the RTN start point 1.