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Cache Memory Assignment Questions

The document outlines a paired assignment involving cache memory calculations. It includes questions on determining bits required for a 4-way set-associative cache, calculating the Tag field for a specific cache configuration, and analyzing a 2-way set associative cache with specific parameters. The assignment requires students to perform calculations based on given memory addresses and cache characteristics.

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12 views2 pages

Cache Memory Assignment Questions

The document outlines a paired assignment involving cache memory calculations. It includes questions on determining bits required for a 4-way set-associative cache, calculating the Tag field for a specific cache configuration, and analyzing a 2-way set associative cache with specific parameters. The assignment requires students to perform calculations based on given memory addresses and cache characteristics.

Uploaded by

wagakiraaa
Copyright
© All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd

Cache Assignment

N/B: Paired assignment

1) When the cache is 64 kilobytes in size and the size of Block/line is 8 bytes, how many bits
would be required in order to represent the lines of a 4-way set-associative memory in
cache?
2) A certain 4-way set associative memory that has a 16KB capacity is built with about 8
words of block size. Here, the word length would be 32 bits. The total size of the space of
the physical address is 4 gigabytes. Find the number of bits for a Tag field.
3) The following cache represents a 2-way set associative cache, i.e., there are two lines per
set. Notice that the set ID values start at 011011012 and increment every other row. This
is meant to imply that you are looking at a group of lines/sets toward the middle of the
cache and not the entire cache. There are 14 bits for the tag, 8 bits for the set id, and 2 bits
for the word id. Answer the following three questions based on this cache.

a) A copy of the data from memory address 7121C5 (hex) is contained in the portion
of the cache shown above. Enter the value that was retrieved from that address in
the space below as a two-digit hexadecimal number with no base identification,
e.g., 0x4F (hexadecimal 4F) should be entered as 4F16
b) How many lines are contained in this cache?
c) How many blocks are contained in the memory space (not the cache, but the
memory) of the cache system defined above? (Due to D2L constraints, the
notation used to represent 2 raised to the power of n is 2n)

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