Natalius 8 bit RISC Processor
Fabio Andrés Guzmán Figueroa
[Link]@[Link]
[Link]@[Link]
1. Description:
Natalius is a compact, capable and fully embedded 8 bit RISC processor core described 100% in
Verilog. It occupies about 268 Slices, 124 FF, 503 LUTs (4 input) in Xilinx Spartan3E1600 (around 1.67%
slices). Natalius offers an assembler that can run on any python console. The instruction memory is
implemented using two Xilinx BlockRAM Memories, it stores 2048 instructions, each instruction has a
width of 16 bits (2048x16). Each instruction takes 3 clock cycles to be executed.
Features:
1. 8 Bit ALU
2. 8x8 Register File
3. 2048x16 Instruction Memory
4. 32x8 Ram Memory
5. 16x11 Stack Memory
6. Three CLK / Instruction
7. Carry and Zero flags
8. 8 bit Address Port (until 256 Peripherals)
2. Instruction Set:
Natalius contains the typical instruction set on a processor. These are: Memory access, arithmetic,
logical and flow control, as described in Table 1. Detailed instruction set shown in Table 3.
Instruction Description Type Instruction Description Type
ldi load immediate memory access ret return subrutine flow control
ldm load from memory memory access adi add with imm arithmetic
stm store to memory memory access csz csr if zero flow control
cmp compare arithmetic cnz csr if no zero flow control
add addition arithmetic csc csr if carry flow control
sub subtraction arithmetic cnc csr if no carry flow control
and logic and logical sl0 shift left zero fill logical
oor logic or logical sl1 shift left one fill logical
xor logic xor logical sr0 shift right zero fill logical
jmp jump flow control sr1 shiftright one fill logical
jpz jump if zero flow control rrl rotary register left logical
jnz jump if no zero flow control rrr rotay register right logical
jpc jump if carry flow control not logic not logical
jnc jump if no carry flow control nop no operation nop
csr call subrutine flow control
Table 1. Natalius Instruction Set
3. Natalius Interface Signals:
The top-level interface signals to the Natalius Processor appear in Figure 1. and are described in
Table 2.
data_in [7:0] data_out [7:0]
Natalius Processor
port_addr [7:0]
CLK write_e
RST read_e
Figure 1. Natalius interface connections
Signal Direction Description
clock input: All Natalius registers are
clk input clocked from the rising clock edge
reset input: To reset the Natalius
processor, this rst is asynchronous input
and it set program counter register to zero
rst input address
Input data port: The data is captured on
the rising edge of CLK (used in ldm
data_in[7:0] input instruction)
Output data port: Output data appears on
this port for three CLK cycles during a stm
instruction, capture this data when write_e
data_out[7:0] output is high (uded in stm instruction)
Port address: This addresses the peripheral
port to the input or output by instruction
port_addr[7:0] output ldm or stm
Table 2. Interface signals descriptions
4. Organization of source codes:
The hierarchy of the files are shown in Figure 2.
Opcode Instr Description Use
2 ldi load immediate ldi rd,imm (rd=imm)
load from
3 ldm memory ldm rd,port_addr (rd=data_in <= mem[port_addr])
4 stm store to memory stm rd,port_addr (rd=data_out => mem[port_addr])
5 cmp compare cmp rd,rs (affects carry and zero)
6 add addition add rd,rs (rd=rd+rs)
7 sub subtraction sub rd,rs (rd=rd-rs)
8 and logic and and rd,rs (rd=rd and rs)
9 oor logic or oor rd,rs (rd=rd or rs)
10 xor logic xor xor rd,rs (rd=rd xor rs)
11 jmp jump jmp inst_addr (pc=inst_addr)
12 jpz jump if zero jpz inst_addr (pc=inst_addr if zero)
13 jnz jump if no zero jnz inst_addr (pc=inst_addr if no zero)
14 jpc jump if carry jpc inst_addr (pc=inst_addr if carry)
15 jnc jump if no carry jnc inst_addr (pc=inst_addr if no carry)
16 csr call subrutine csr inst_addr (pc=inst_addr) save pc+1 in stack
17 ret return subrutine ret (pc=value stored in stack)
18 adi add with imm add rd,imm (rd=rd+imm)
19 csz csr if zero csr inst_addr (pc=inst_addr if zero) affects stack
20 cnz csr if no zero csr inst_addr (pc=inst_addr if no zero) affects stack
21 csc csr if carry csr inst_addr (pc=inst_addr if carry) affects stack
22 cnc csr if no carry csr inst_addr (pc=inst_addr if no carry) affects stack
23 sl0 shift left zero fill sl0 rd (rd <= {rd[6:0],0})
24 sl1 shift left one fill sl1 rd (rd <= {rd[6:0],1})
25 sr0 shift right zero fill sr0 rd (rd <= {0,rd[7:1]})
26 sr1 shiftright one fill sr1 rd (rd <= {1,rd[7:1])
rotary register
27 rrl left rrl rd (rd <= {rd[6:0],rd[7]})
rotay register
28 rrr right rrr rd (rd <= {rd[0],rd[7:1])
29 not logic not sub rd,rs (rd=rd-rs)
30 nop no operation no operation (take 3 clk )
Table 3. Detailed Instruction Set
5. Assembler script
The assembler script was written in python, you can download python for any operating system from:
[Link]. How to use the script from the console is as follows:
Figure 2. Source files hierarchy for Natalius processor and reference design
./[Link] [Link] (linux)
python [Link] [Link] (win cmd)
Where "[Link]" is the file that will be assembled. The output file is named: " [Link]", and
it must be included on the same route where the source codes are, because the hardware
description of the instruction memory (instruction_memory.v) is needed.
It is also possible an assembled view line by line, this option is possible by adding the flag [-s] as
shown below:
./[Link] -s [Link] (linux)
python [Link] -s [Link] (win cmd)
5.1 Example
Consider the following code:
csr negro
end jmp end
negro stm r0,32
ldi r1,80
ldi r2,60
ldi r3,0
ldi r4,0
nextc cmp r4,r1
jpz inc_fil
stm r3,64
stm r4,32
adi r4,1
jmp nextc
inc_fil ldi r4,0
cmp r3,r2
jpz fneg
adi r3,1
jmp nextc
fneg ret
The above code is saved in the file "[Link]". When running the line:
./[Link] -s [Link]
the console displays the following:
addr inst asm
0 8002 csr 2
1 5801 jmp 1
2 2020 stm r0,32
3 1150 ldi r1,80
4 123C ldi r2,60
5 1300 ldi r3,0
6 1400 ldi r4,0
7 2C20 cmp r4,r1
8 600D jpz 13
9 2340 stm r3,64
10 2420 stm r4,32
11 9401 adi r4,1
12 5807 jmp 7
13 1400 ldi r4,0
14 2B40 cmp r3,r2
15 6012 jpz 18
16 9301 adi r3,1
17 5807 jmp 7
18 8800 ret
6. Reference Design:
The reference design is the implementation of the classic video game (pong) using the processor
Natalius. The architecture of this design is shown in Figure 3, a photo of the game in action is shown in
Figure 4.
port_addr[7:5]==000
RAM Memory (32x8)
Natalius Processor
{ 4'b0, SW } 0
data_in [7:0] data_out [7:0] din [7:0]
memout [7:0] 1
port_addr [4:0]
port_addr [7:0] addr [4:0]
CLK write_e we
RST read_e memout [7:0]
dout [7:0]
COL register
write_e d [6:0] q [6:0]
up1 D Q CE COL [6:0]
CE
clk
port_addr [7:5]
Rst_ext deco ROW register
write_e
d [5:0] q [5:0]
ROW[5:0]
CE
down1 D Q
CE
clk
SW[3:0] COLOR register
Rst_ext write_e
d [2:0] q [2:0]
COLOR[2:0]
CE
up2 D Q
CE
clk
WE register
Rst_ext
write_e
d q
we
CE
down2 D Q
CE Rst_ext register
clk mem_video write_e
d q
Rst_ext Rst_ext
(8192x4) CE
{ 0, COLOR[2:0] } DIA[3:0]
{ ROW, COL } ADDRA[12:0]
we WEA
vga_control
h_sync
v_sync
addr_read rst
ADDRB[12:0] color[2:0] -> r,g,b
DOB[2:0]
DOB[3:0] doutb[2:0]
Figure 3. Hardware architecture of reference design (pong video game)
Figure 4. Reference design implementation on Spartan 3E 1600E Starter Kit Board
ANNEX (Pong assembler code)
ldi r0,0 csr moli
csr negro stm r2,21
ldi r1,25 ldm r2,22
stm r1,21 ldm r5,32
stm r1,22 ldi r6,4
ldi r1,5 and r6,r5
stm r1,11 sr0 r6
ldi r1,75 sr0 r6
stm r1,12 ldi r7,8
stm r0,5 and r7,r5
stm r0,6 sr0 r7
ldi r1,1 sr0 r7
stm r0,8 sr0 r7
stm r1,9 csr moli
punto ldi r1,40 stm r2,22
stm r1,10 csr cobo
ldi r1,30 csr mobo
stm r1,20 ldm r1,11
csr dbl ldm r2,21
csr dbl ldi r4,7
csr dbl csr lineav
csr dbl ldm r1,12
csr dbl ldm r2,22
csr dbl ldi r4,7
csr dbl csr lineav
csr dbl csr bola
csr dbl csr delay
csr dbl csr delay
csr dbl csr delay
csr dbl csr delay
csr dbl ldi r7,1
csr dbl stm r7,128
inicio csr marca stm r0,128
csr vermarc jmp inicio
csr negro delay ldi r1,0
csr marca ldi r2,0
ldm r2,21 ldi r3,255
ldm r5,32 pat04 cmp r1,r3
ldi r6,1 jpz pat03
and r6,r5 pat02 cmp r2,r3
ldi r7,2 jpz pat01
and r7,r5 adi r2,1
sr0 r7 jmp pat02
pat01 adi r1,1 adi r6,1
ldi r2,0 stm r6,5
jmp pat04 stm r0,9
pat03 ret jmp punto
bola ldm r1,10 comp05 cmp r2,r7
ldm r2,20 jnz comp06
ldi r4,7 ldi r6,1
stm r1,32 stm r6,8
stm r2,64 comp06 cmp r2,r4
stm r4,96 jnz comp07
csr we stm r0,8
ret comp07 ldm r3,11
mobo ldm r1,10 ldm r4,21
ldm r2,20 adi r3,1
ldm r3,8 cmp r1,r3
ldm r4,9 jnz comp08
ldi r5,1 cmp r2,r4
cmp r3,r5 jpz comp09
jpz comp12 adi r4,1
sub r2,r5 cmp r2,r4
jmp comp13 jpz comp09
comp12 adi r2,1 adi r4,1
comp13 cmp r4,r5 cmp r2,r4
jnz comp14 jpz comp09
adi r1,1 adi r4,1
jmp comp15 cmp r2,r4
comp14 sub r1,r5 jpz comp09
comp15 stm r1,10 adi r4,1
stm r2,20 cmp r2,r4
ret jpz comp09
cobo ldm r1,10 adi r4,1
ldm r2,20 cmp r2,r4
ldi r3,78 jnz comp08
ldi r4,58 comp09 ldi r6,1
ldi r7,2 stm r6,9
cmp r1,r7 comp08 ldm r3,12
jnz comp04 ldi r6,1
ldm r6,6 ldm r4,22
adi r6,1 sub r4,r6
stm r6,6 cmp r1,r3
ldi r6,1 jnz comp10
stm r6,9 cmp r2,r4
jmp punto jpz comp11
comp04 cmp r1,r3 adi r4,1
jnz comp05 cmp r2,r4
ldm r6,5 jpz comp11
adi r4,1 csr lineav
cmp r2,r4 gana1 jmp gana1
jpz comp11 comp01 ldi r3,6
adi r4,1 cmp r2,r3
cmp r2,r4 jnz comp02
jpz comp11 ldm r1,11
adi r4,1 ldm r2,21
cmp r2,r4 ldi r4,4
jpz comp11 csr lineav
adi r4,1 gana2 jmp gana2
cmp r2,r4 comp02 ret
jnz comp10 lineav ldi r3,5
comp11 stm r0,9 add r3,r2
comp10 ret con cmp r2,r3
moli ldi r3,1 jnc ter
ldi r4,55 stm r2, 64
ldi r5,2 stm r1, 32
cmp r6,r3 stm r4, 96
jnz comp03 csr we
cmp r2,r3 adi r2,1
jpz finmol jmp con
sub r2,r5 ter ret
comp03 cmp r7,r3 negro ldi r7,1
jnz finmol stm r7,160
cmp r2,r4 stm r0,96
jpz finmol ldi r1,80
add r2,r5 ldi r2,60
finmol ret ldi r3,0
marca ldm r5,5 ldi r4,0
ldi r1,19 nextc cmp r4,r1
ldi r2,5 jpz inc_fil
ldi r4,6 stm r3,64
csr impnum stm r4,32
ldm r5,6 adi r4,1
ldi r1,57 jmp nextc
ldi r2,5 inc_fil ldi r4,0
csr impnum cmp r3,r2
ret jpz fneg
vermarc ldm r1,5 adi r3,1
ldm r2,6 jmp nextc
ldi r3,6 fneg stm r0,160
cmp r1,r3 ret
jnz comp01 we ldi r7,1
ldm r1,12 stm r7,160
ldm r2,22 ldi r7,0
ldi r4,4 stm r7,160
ret sub r1,r7
dbl csr delay ret
csr delay segc ldi r7,2
csr delay add r1,r7
ldm r1,11 add r2,r7
ldm r2,21 csr segv
ldi r4,2 ldi r7,2
csr lineav sub r1,r7
ldm r1,12 sub r2,r7
ldm r2,22 ret
ldi r4,2 segd ldi r7,4
csr lineav adi r2,4
csr bola csr segh
ret ldi r7,4
segh ldi r3,3 sub r2,r7
add r3,r1 ret
pon1 cmp r1,r3 sege ldi r7,2
jpz mer1 adi r2,2
stm r2, 64 csr segv
stm r1, 32 ldi r7,2
stm r4, 96 sub r2,r7
csr we ret
adi r1,1 segf csr segv
jmp pon1 ret
mer1 ldi r3,3 segg ldi r7,2
sub r1,r3 adi r2,2
ret csr segh
segv ldi r3,3 ldi r7,2
add r3,r2 sub r2,r7
pon2 cmp r2,r3 ret
jpz mer2 impnum ldi r7,1
stm r2, 64 cmp r5,r7
stm r1, 32 jpz num01
stm r4, 96 ldi r7,4
csr we cmp r5,r7
adi r2,1 jpz num01
jmp pon2 csr sega
mer2 ldi r3,3 num01 ldi r7,5
sub r2,r3 cmp r5,r7
ret jpz num02
sega csr segh ldi r7,6
ret cmp r5,r7
segb ldi r7,2 jpz num02
add r1,r7 csr segb
csr segv num02 ldi r7,2
ldi r7,2 cmp r5,r7
jpz num03
csr segc
num03 ldi r7,1
cmp r5,r7
jpz num04
ldi r7,4
cmp r5,r7
jpz num04
ldi r7,7
cmp r5,r7
jpz num04
csr segd
num04 ldi r7,0
cmp r5,r7
jpz num05
ldi r7,2
cmp r5,r7
jpz num05
ldi r7,6
cmp r5,r7
jpz num05
ldi r7,8
cmp r5,r7
jnz num06
num05 csr sege
num06 ldi r7,1
cmp r5,r7
jpz num07
ldi r7,2
cmp r5,r7
jpz num07
ldi r7,3
cmp r5,r7
jpz num07
ldi r7,7
cmp r5,r7
jpz num07
csr segf
num07 ldi r7,0
cmp r5,r7
jpz num08
ldi r7,1
cmp r5,r7
jpz num08
csr segg
num08 ret