MICROPROCESSOR
Q1) Explain memory banking in 8086
1) The 8086 processor provides a 16-bit data bus. So, It is capable of transferring 16 bits in
one cycle, but each the memory location is only of a byte(8 bits), therefore we need two
cycles to access 16 bits(8 bit each) from two different memory locations.
2) The solution to this problem is Memory Banking. Through Memory banking, our goal is
to access two consecutive memory locations in one cycle(transfer 16 bits).
3) The memory chip is equally divided into two parts(banks). One of the banks contains
even addresses called Even bank and the other contains odd addresses called Odd bank.
4) Even bank always gives lower byte So Even bank is also called Lower bank(LB) and
Odd bank is also called a Higher bank(HB).
5) This banking scheme allows accessing two aligned memory locations from both banks
simultaneously and process 16-bit data transfer.
6) Memory banking doesn’t make it compulsory to transfer 16 bits, it facilitates the 16-bit
data transfer.
7) The choice between 8 bit and 16-bit transfer depends on the instructions given by the
programmer.
Q2) Explain memory segmentation in 8086. Write its advantages and
disadvantages
Segmentation is the process in which the main memory of the computer is logically
divided into different segments and each segment has its own base address. It is basically
used to enhance the speed of execution of the computer system, so that the processor is
able to fetch and execute the data from the memory easily and fast.
The Bus Interface Unit (BIU) contains four 16 bit special purpose registers (mentioned
below) called as Segment Registers.
Code segment register (CS)
Data segment register (DS)
Extra Segment Register (ES)
Stack Segment Register (SS)
The four segment registers actually contain the upper 16 bits of the starting addresses of
the four memory segments of 64 KB each with which the 8086 is working at that instant
of time. A segment is a logical unit of memory that may be up to 64 kilobytes long. Each
segment is made up of contiguous memory locations. It is an independent, separately
addressable unit. Starting address will always be changing. It will not be fixed.
Advantages of the Segmentation
1) It provides a powerful memory management mechanism.
2) Data related or stack related operations can be performed in different segments.
3) Code related operation can be done in separate code segments.
4) It allows to processes to easily share data.
Q3) Draw and explain format of flag register of 8086.
The flag register is a 16-bit register in the Intel 8086 microprocessor that contains
information about the state of the processor after executing an instruction. It is sometimes
referred to as the status register because it contains various status flags that reflect the
outcome of the last operation executed by the processor.
The flag register is an important component of the 8086 microprocessor because it is used
to determine the behavior of many conditional jump and branch instructions. The various
flags in the flag register are set or cleared based on the result of arithmetic, logic, and
other instructions executed by the processor.
There are total 9 flags in 8086 and the flag register is divided into two types:
(a) Status Flags – There are 6 flag registers in 8086 microprocessor which become
set(1) or reset(0) depending upon condition after either 8-bit or 16-bit operation. These
flags are conditional/status flags.
The 6 status flags are:
1. Sign Flag (S)
2. Zero Flag (Z)
3. Auxiliary Carry Flag (AC)
4. Parity Flag (P)
5. Carry Flag (CY)
6. Overflow Flag (O)
b) Control Flags – The control flags enable or disable certain operations of the
microprocessor. There are 3 control flags in 8086 microprocessor and these are:
1) Directional Flag (D)
2) Interrupt Flag (I)
3) Trap Flag (T)
Q4) Explain interrupt structure (Types on interrupts) of 8086.
An interrupt is a condition that halts the microprocessor temporarily to work on a
different task and then returns to its previous task. An interrupt is an event or signal that requests
the CPU’s attention. This halt allows peripheral devices to access the microprocessor. Whenever
an interrupt occurs, the processor completes the current instruction and starts the implementation
of an Interrupt Service Routine (ISR) or Interrupt Handler. ISR is a program that tells the
processor what to do when the interrupt occurs. After the ISR execution, control returns to the
main routine where it was interrupted. In the 8086 microprocessor following tasks are performed
when the microprocessor encounters an interrupt:
1. The value of the flag register is pushed into the stack.
2. The value of starting memory address of CS is pushed into the stack.
3. The value of IP is pushed into the stack.
4. IP is loaded from word location
5. CS is loaded from word location.
6. Interrupt, and Trap flags are reset to 0.
The different types of interrupts present in the 8086 microprocessor
1) Hardware Interrupts – Hardware interrupts are those interrupts that are caused by
any peripheral device by sending a signal through a specified pin to the
microprocessor.
There are two hardware interrupts :NMI (Non-Maskable Interrupt)
NTR (Interrupt Request)
2) Software Interrupts – These are instructions inserted within the program to generate
interrupts. There are 256 software interrupts in the 8086 microprocessor.
software interrupts are:
TYPE 0 corresponds to division by zero(0).
TYPE 1 single-step execution for debugging the program.
TYPE 2 NMI and is used in power failure conditions.
TYPE 3 break-point interrupt.
TYPE 4 overflow interrupt.
Q5) Explain 8086 addressing modes with suitable example
The way of specifying data to be operated by an instruction is known as addressing
modes. This specifies that the given data is an immediate data or an address.
Types of addressing modes:
1) Register mode – In this type of addressing mode both the operands are registers
2) Immediate mode – In this type of addressing mode the source operand is a 8 bit or 16 bit
data. Destination operand can never be immediate data.
3) Displacement or direct mode – In this type of addressing mode the effective address is
directly given in the instruction as displacement.
4) Register indirect mode – In this addressing mode the effective address is in SI, DI or
BX.
5) Based indexed mode – In this the effective address is sum of base register and index
[Link] physical memory address is calculated according to the base register.
6) Indexed mode – In this type of addressing mode the effective address is sum of index
register and displacement.
7) Based mode – In this the effective address is the sum of base register and displacement.
8) Based indexed displacement mode – In this type of addressing mode the effective
address is the sum of index register, base register and displacement.
9) String mode – This addressing mode is related to string instructions. In this the value of
SI and DI are auto incremented and decremented depending upon the value of directional
flag.
10) Input/Output mode – This addressing mode is related with input output operations.
11) Relative mode –In this the effective address is calculated with reference to instruction
pointer.
Q6)
Sr. No Features 8086 80386
Pentium-I Pentium-II
Pentium-III
1. Year of Release 1978
1985 1993 1997 1999
2. Processor Size 16 Bit 32
Bit 32 Bit 32 Bit 32 Bit
3. Data Bus 16 Bit 32 Bit 64
Bit 64 Bit 64 Bit
4. Address Bus 20 Bit 32 Bit
32 Bit 32 Bit 32 Bit
5. Memory Banks 2 4 8 8 8
6. Memory Size 1 MB 4 GB
4 GB 64 GB 64GB
7. Pipeline Stages 2 3 5 17
15
8. ALU Size 16 Bit 32 Bit 32
Bit 32 Bit 32 Bit
9. Number of
Transistors
29 K 275 K 3.1 M 7.5 M 9.5
M
10. Operating Frequency 6
MHz 33 MHz 100 MHz 450
MHz 450-1400 MH
Sr. No Features 8086 80386
Pentium-I Pentium-II
Pentium-III
1. Year of Release 1978
1985 1993 1997 1999
2. Processor Size 16 Bit 32
Bit 32 Bit 32 Bit 32 Bit
3. Data Bus 16 Bit 32 Bit 64
Bit 64 Bit 64 Bit
4. Address Bus 20 Bit 32 Bit
32 Bit 32 Bit 32 Bit
5. Memory Banks 2 4 8 8 8
6. Memory Size 1 MB 4 GB
4 GB 64 GB 64GB
7. Pipeline Stages 2 3 5 17
15
8. ALU Size 16 Bit 32 Bit 32
Bit 32 Bit 32 Bit
9. Number of
Transistors
29 K 275 K 3.1 M 7.5 M 9.5
M
10. Operating Frequency 6
MHz 33 MHz 100 MHz 450
MHz 450-1400 MH
The Pentium 4 processor is
the first hardware
implementation of a new
micro-architecture, the
Intel NetBurst micro-
architecture.
The Intel NetBurst
micro-architecture is
designed to achieve high
performance for both
integer
and floating-point
computations at very high
clock rates.
It has the following
features:
i. Hyper pipelined
technology to enable high
clock rates and frequency
headroom to well
above 1GHz
ii. Rapid execution engine
to reduce the latency of
basic integer instructions
iii. High-performance, quad-
pumped bus interface to
the 400 MHz Intel NetBurst
micro-
architecture system bus.
iv. Execution trace cache to
shorten branch delays
v. Cache line sizes of 64
and 128 bytes
vi. Hardware prefetch
vii. Aggressive branch
prediction to minimize
pipeline delays
viii. Out-of-order
speculative execution to
enable parallelism
ix. Superscalar issue to
enable parallelism
x. Hardware register
renaming to avoid register
name space limitations
Q7) Pentium 4: Net burst micro architecture.
i. It is an overview of Intel net burst [Link] architecture of pipeline is mode up for
three section:
The front and pipeline
The out of order execution core
The retirement unit
ii. The concept behind the Intel net worth micro architecture was to improve the efficiency
of the out of order execution engine and to create a processor that can reach much higher
frequency with higher performance relative to p5 and P6 micro architecture while
maintaining backward compatibility
iii. The execution trace cache address their problems by storing decoded IA 32 instructions
iv. The trace cache delivers up to 3 operations.
v. Branch targets are predicted based on their linear address using branch production logic
and fetched as soon as possible.
vi. Translation engines branch prediction information is used to form traces along the most
likely path.
vii. The core ability to execute instruction out of order remains a key factor in enabling
parallelism.
viii. The processor employees several buffers to smooth the flow of operations.
ix. The net worth micro architecture ads for the improvements to execution units over that of
P4 micro architecture.
Q8) Explain features of Pentium 4
a. The Pentium 4 processor was released in the year 2000 and consists 42 million
transistors
b. It is available with a maximum internal clock rating of 1.4 MHz to 2.8 GHz
Features of the Pentium 4 processor are:
• hyperthreading HT technology
• hyper pipeline technology which supports advanced dynamic execution and very
deep out-of-order execution
• rapid execution engine ALUS run at twice the processor core frequency system
bus frequency at 400 / 533 / 800 MHz
• binary compatibility with application running on previous member of Intel
processor
• 8 KB level 1 data cache
• level 1 execution trace cashless stores 12 - k micro ops and error correcting code
Q9)Explain MESI protocol in brief
a. The MESI protocol is a formal mechanism for controlling cache coherently using
snooping technique.
b. Its acronym stands for modified, exclusive, shared, invalid and refers to the states
that the cached data can take.
c. The transition between the states is control by memory access and bus snooping
activity this information appears on special signals pin during bus transactions.
d. The MESI diagram is generic and shows a general operation of the protocol.
There are four stage that describe the cache contents and it coherence with system
memory
• Invalid - the target address is not cached
• Shared- The target address is in cache and also in at least one other it is coherent
with system memory
• Exclusive - The target address is in the cache but the data is not coherent with
system memory
• Modified - The target address is in the cache but the contents have been modified
and is not coherent with system no other cache in the system has this data.
Q10)What do you mean by super-scalar
1) Superscalar refers to a machine that is designed to improve the performance of the
execution of scalar instruction
2) In superscalar processor instructions execute independently in different pipelines
3) In superscalar processor is a CPU that implements a form of parallelism called
instruction-level parallelism with a single processor
4) The main principle of super scalar approach is that it executives instruction independently
in different instruction pipelining which leads to your parallel processing there by
speeding of the preserve installation
Q11)What do you mean by HyperThreading
1) Hyper-Threading (HT) is a technology developed by Intel that allows a single physical
processor core to execute multiple software threads concurrently, simulating the presence
of additional cores to the operating system and software applications.
2) When a processor with Hyper-Threading technology runs an application that uses
multiple threads, the operating system sees two logical processors for each physical
processor core. This means that a dual-core processor with Hyper-Threading appears to
the operating system and software applications as a quad-core processor.
3) Hyper-Threading works by duplicating some of the components of a processor core that
are shared by multiple threads, such as the instruction pipeline, the program counter, and
certain registers. This duplication allows each logical processor to maintain a separate
state and execute different threads simultaneously, as if there were two independent
processors on the same physical core.
4) Hyper-Threading technology can improve the performance of multithreaded applications
by allowing the processor to utilize its resources more efficiently. However, the actual
performance improvement depends on factors such as the number of threads being
executed, the complexity of the application, and the workload of the system.
Q12) Integer and floating pipeline in Pentium.
The Pentium processor, introduced by Intel in 1993, has both an integer pipeline and a
floating-point pipeline. These pipelines are parallel processing units that can execute
instructions simultaneously, allowing for faster processing of instructions.
1) The Integer pipeline is responsible for executing instructions that involve integer
data types, such as addition, subtraction, multiplication, and division. The pipeline
is divided into five stages: instruction fetch, instruction decode, instruction
execution, memory access, and write back. During each stage, a specific operation
is performed on the instruction and its associated data.
2) The Floating-Point pipeline is responsible for executing instructions that involve
floating-point data types, such as decimal numbers. The pipeline is divided into
two stages: the execution stage and the write-back stage. During the execution
stage, the floating-point unit (FPU) performs mathematical operations on the data.
During the write-back stage, the results of the operation are written back to
memory.
3) Both pipelines work in parallel, which means that while one pipeline is executing
an instruction, the other pipeline can be fetching the next instruction from
memory. This parallelism allows the Pentium processor to execute instructions at
a much faster rate than previous processors.
Q13)Distinguish between real mode, virtual mode, and protected mode.
REAL MODE VIRTUAL MODE PROTECTED MODE
Real mode is also called as real Virtual mode is a mode of operation Protected mode is a mode of operation
address mode. It is a default that allows 16-bit real mode that provides memory protection and
operating mode on reset applications to run in a protected multitasking capabilities
mode environment.
It has only 1MB memory It has 1MB with 20 bit physical It has more than 1MB to few GB
addressing capability. memory addressing capability memory addressing capability.
It performs 16 bit operations It performs 16 bit operations It performs 32 bit operations
In this mode control registers are In this mode control registers are not Here, 4 control registers are
not available available available.CR0,CR1,CR2,CR3.
Flag registers is of 16 bits 16 bit flag register 32 bit flag register
Paging and protection mechanism Paging and protection mechanism is Paging and protection mode both are
is not available not available available. 4 level protection-
PL0,PL1,PL2,PL3.
In real mode 80386 works as In virtual mode 80386 works as 8086 In protected mode all features of 80386
8086. All features of 8086 are but the speed is very fast than 8086 are available
working.
Q12)Explain code cache organistaion of pentium
1) The code cache is 8 KB read only and is organized as 2 way set associative cache the
two ways are called way zero and way one.
2) Total size of cache is equal to 8 KB.
3) Size of each way is 4 KB.
4) Cache line size is 32 bytes.
5) Total number of lines in one way is 128.
6) There is separate 128 entry directory associated with each cacheway the 4GB memory
space of processor is mapped into 4kb cacheway and total number of pages is 1M.
7) Thus each cache directory entry stores 20 bit tag address the entry also consist of one
state bit and parity bit P.
8) The cache directories are triple ported to allow three simultaneous directory accesses.
9) Two of ports support split line access capability while 3rd port is used for snooping.
10) Each cache line holds 4 quad words and parity bit.
Split line access-
1) In CISC processor like Pentium instruction are of variable length
2) Multi byte instructions may span two sequential line store to code cache.
3) When prefetcher determines that instruction is straddled across two lines, it
would have to perform two sequential cache access
4) For this reason the Phantom processor incorporate split line access which
allows upper half of one line and lower half of next line to be
accessed in one cycle
Q14)Write branch prediction logic of pentium.
1) The Pentium processor include branch prediction logic, allowing into minimise
pipeline flushing.
2) When branch operation is correctly predicted no performance penalty is incurred
3) However, when branch prediction is not correct, a 3 cycle penalty is incurred if
branch is executed in U pipeline and up to 4 cycle penalty, if branch is V.
4) The prediction mechanism is implemented using 4-way set associative cache with
256 entries.
5) This is referred to as branch target buffer, BTB is look- aside cache that sits off to
side of DI stages of 2 pipelines and monitors for branch instructions.
6) If history bits are 00 or 01 then prediction in branch will not be taken.
7) If history bits are 10 or 11 then prediction in branch will be taken.
8) If branch is predicted to be taken then active queue is no longer used. Instead the
prefetcher start fetching instructions from branch address and stores them into
second queue which now becomes active queue. This queue now start feeding
instructions into two pipes.
9) If branch is predicted to be not taken then nothing changes and active queue
remains active and instructions are fetched from sequentially next location.
The history of bits can indicate four possible States: