PCCSL308 - DIGITAL LAB DEPARTMENT OF ELECTRONICS &
COMMUNICATION ENGINEERING
ASYNCHRONOUS COUNTER
Aim
1. Set up a 3 bit binary up counter.
2. Set up a 3 bit binary down counter.
3. Set up a 3 bit binary up / down counter.
4. Set up a Mod N counter (Decade counter).
Components and equipment’s required
ICs 7400, 7476, 7486 and trainer kit.
Theory
A counter is a circuit that produces a set of unique output combinations in relation to the number of applied
input pulses. The number of unique outputs of a counter is known as its modulus or mod number.
In asynchronous counters, the flip flops are not given the clock simultaneously. Therefore, the
propagation delay increases with the number of flip flops used. Four JK flip flops must be used in toggle
mode to count 16 states (JKFF can be converted to TFF by shorting J & K inputs).
4 bit binary up counter (Ripple counter) - In the circuit set up, all flip flops are clocked by the Q output
of the preceding flip flop. JK inputs of all the flip flops are connected to a high state. 7476 is a dual JK
Master Slave flip flop with preset and clear. A ripple counter comprising of n flip flops can be used to
count up to 2n pulses. A circuit with three flip flops gives a maximum count of 23 = 8. The counter gives
a natural binary count from 0 to 7 and resets to initial condition on 8th input pulse. With the application of
the first clock pulse Q0 changes from 0 to 1. Q1, Q2 and Q3 remain unaffected. With second clock pulse,
Q0 becomes 0 and Q1 becomes 1. At the arrival of 7th clock pulse all the Q outputs will become 1. At the
8th clock pulse all Q outputs reset and the cycle repeats.
A good example of a Mod-N counter circuit which uses external combinational circuits to produce a
counter with a modulus of 10 is the Decade Counter. Decade (divide-by-10) counters such as the TTL
74LS90, have 10 states in its counting sequence making it suitable for human interfacing where a digital
display is required. The decade counter has four outputs producing a 4-bit binary number and by using
external AND & OR gates we can detect the occurrence of the 9th counting state to reset the counter back
to zero. As with other mod counters, it receives an input clock pulse, one by one, and counts up from 0 to
9 repeatedly. Once it reaches the count 9 (1001 in binary), the counter goes back to 0000 instead of
continuing on to 1010. The basic circuit of a decade counter can be made from JK flip-flops (TTL 74LS76)
that switch state on the negative trailing-edge of the clock signal.
In a 3 bit up / down counter, the direction of counting sequence is decided by a mode control input M.
An XOR gate between flip flops functioning as a controlled inverter connects either of Q or Q to the clock
input of the succeeding flip flop as decided by the logic state at M. When mode control is 0, Q outputs get
connected to the clock inputs of the succeeding flip flops and counter counts up. When mode control is 1,
Q outputs are connected to the clock inputs and counter counts down.
RAJIV GANDHI INSTITUTE OF TECHNOLOGY, KOTTAYAM 1
PCCSL308 - DIGITAL LAB DEPARTMENT OF ELECTRONICS &
COMMUNICATION ENGINEERING
Procedure
1. Test all ICs using a digital IC tester. Also test all the wires for continuity using a multi meter or
IC trainer. Continuity of a wire can be tested using an IC trainer by shorting any supply point to
an LED.
2. Set up the circuit for 4 bit ripple counter. Connect all the PRESET pins to +5 V to disable it.
3. Clear all flip flop outputs initially connecting common CLEAR terminal to logic 0. After the
usage of CLEAR pins connect them to logic 1 or keep them open. Apply mono pulses. Counter
starts counting up.
4. Move clock inputs of every flip flop except FF0 from Q outputs to the Q outputs. Preset all FFs
by connecting common PRESET terminal to logic 0. Apply mono pulses. Counter will start
counting downwards.
5. Set up the decade counter circuit and repeat steps for counting up.
6. Set up 3 bit up/down counter and observe the forward (up) counting when mode control is 1 and
backward (down) counting when mode control is 0.
7. To observe the waveforms on CRO, feed the clock input of high frequency and observe input and
output simultaneously on a dual trace CRO.
Circuit Diagrams
1. 3 Bit binary Up Counter:
Circuit Diagram
Clock Q2 Q1 Q0
0 0 0 0
1 0 0 1
2 0 1 0
3 0 1 1
4 1 0 0
5 1 0 1
6 1 1 0
7 1 1 1
8 0 0 0
Truth Table
RAJIV GANDHI INSTITUTE OF TECHNOLOGY, KOTTAYAM 2
PCCSL308 - DIGITAL LAB DEPARTMENT OF ELECTRONICS &
COMMUNICATION ENGINEERING
2. 3 Bit binary Down Counter:
Circuit Diagram
Clock Q2 Q1 Q0
0 1 1 1
1 1 1 0
2 1 0 1
3 1 0 0
4 0 1 1
5 0 1 0
6 0 0 1
7 0 0 0
8 1 1 1
Truth Table
3. 3 bit binary up / down counter:
Circuit Diagram
RAJIV GANDHI INSTITUTE OF TECHNOLOGY, KOTTAYAM 3
PCCSL308 - DIGITAL LAB DEPARTMENT OF ELECTRONICS &
COMMUNICATION ENGINEERING
Truth Table
4. Decade Counter:
Circuit Diagram
Truth Table
RAJIV GANDHI INSTITUTE OF TECHNOLOGY, KOTTAYAM 4
PCCSL308 - DIGITAL LAB DEPARTMENT OF ELECTRONICS &
COMMUNICATION ENGINEERING
Result
A 3-bit binary up counter, 3-bit binary down counter, a Mod-N counter (Decade counter) and a 3-bit
binary up / down counter were implemented and their working studied.
RAJIV GANDHI INSTITUTE OF TECHNOLOGY, KOTTAYAM 5