Shri Baleshwar Shaikshanik va Krushi Vikas Foundation

SHRI SWAMI SAMARTH INSTITUTE OF

MANAGEMENT AND TECHNOLOGY
At. Malwadi, Po. Bota, Tal. Sangamner, Dist: [Link] 422602

DEPARTMENT OF CO/IT/AI&DS/E&TC

Year : 20 TO 20

Name of Students : _________________________________________

Class : ______________________ Semester: ___________________

Subject : __________________________________________________

Examination Seat No. : ______________________________________

 Shri Baleshwar Shaikshanik va Krushi Vikas Foundation

SHRI SWAMI SAMARTH INSTITUTE OF

MANAGEMENT AND TECHNOLOGY
At. Malwadi, Po. Bota, Tal. Sangamner, Dist, [Link] 422602

Completion of Practical Work

CERTIFICATE
This is to Certify that Mr./ Miss.________________________________________
of Class : _________________________PRN No. :__________________________

Successfully completed his/her practical’s for the lab course in the subject of
______________________________________________for the academic year
202 - 202 and the same has been examined by the Practical – In –charge

Date : | | 202

Practical In-charge Principle

External Examiner Internal Examiner

 Shri Baleshwar Shaikshanik va Krushi Vikas Foundation

SHRI SWAMI SAMARTH INSTITUTE OF

MANAGEMENT AND TECHNOLOGY
At. Malwadi, Po. Bota, Tal. Sangamner, Dist, [Link] 422602

INDEX
Sr. Date Title of Experiment Page Signature
No. No.
 SHRI SWAMI SAMARTH COLLEGE OF ENGINEERING, MALWADI ,BOTA.
DEPARTMENT OF ELECTRONIC’S ENGINEERING

DEPARTMENT OF ELECTRONIC’S ENGINEERING

LABORATORY MANUAL
Digital Electronics

Sr. No. Description

I. Institute and Department Vision, Mission, Quality Policy, Quality Objectives,

PEOs, POs and PSOs

II. List of Experiments

Study of Logic gates and their ICs and universal gates.
1.
Implement AND, OR, NOT, XOR, XNOR using NAND gates
2.
Implement AND, OR, NOT, XOR, XNOR using NOR gates.
3.
Verifying De Morgan's laws. (Using Logic gates)
4.
Implement the given Boolean expressions using minimum number of gates.
5.
Design and implement Half adder and Full adder.
6.
Design and implement 4:1 multiplexer.
7.
Design and implement 1:4 Demultiplexer. Study of IC 74139
8.
Design of 3-bit synchronous counter using 7473 and required gates.
9
Study of IC 7490, 7492, 7493 and designing mod-n counters using these.
10
Design and implement a 2-bit by 2-bit multiplier.
11
Design and implement a 2-bit comparator.
12

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 SHRI SWAMI SAMARTH COLLEGE OF ENGINEERING, MALWADI ,BOTA.
DEPARTMENT OF ELECTRONIC’S ENGINEERING

Vision and Mission of the College

VISION:

To transform rural youth power into knowledge, skilled and competent professionals

MISSION:

To facilitate best teaching learning practices by creating a supportive environment to develop

competent professionals

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 SHRI SWAMI SAMARTH COLLEGE OF ENGINEERING, MALWADI ,BOTA.
DEPARTMENT OF ELECTRONIC’S ENGINEERING

PROGRAM EDUCATIONAL OBJECTIVES (PEOs)

Electronics engineering graduates will be able to-
1. Demonstrate the ability to analyse and solve engineering problems through application of
knowledge of mathematics, science, and engineering.

2. Design, test and implement electronic systems using modern tools and technologies.

3. Demonstrate leadership, understand professional and ethical responsibilities and contribute

for the betterment of the society.

4. Communicate effectively and function well as a team member and be able to manage
projects in a multi-disciplinary environment.

5. Pursue lifelong learning in the broadest context of ever advancing technological change and
the needs of time.

PROGRAMME SPECIFIC OUTCOMES (PSOs)

The graduate is expected to acquire

1. An ability to identify, formulate and solve electronics engineering problems.

2. An ability to design electronics circuits, conduct experiments, analyse and interpret
data.
3. Skill to use modern electronics engineering tools, software and equipment.

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 SHRI SWAMI SAMARTH COLLEGE OF ENGINEERING, MALWADI ,BOTA.
DEPARTMENT OF ELECTRONIC’S ENGINEERING

PROGRAM OUTCOMES (POs)

Engineering Graduates will be able to:

 Engineering knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals, and an engineering specialization to the solution of complex engineering
problems.
 Problem analysis: Identify, formulate, review research literature, and analyze
complex engineering problems reaching substantiated conclusions using first
principles of mathematics, natural sciences, and engineering sciences.
 Design/development of solutions: Design solutions for complex engineering
problems and design system components or processes that meet the specified needs
with appropriate consideration for the public health and safety, and the cultural,
societal, and environmental considerations.
 Conduct investigations of complex problems: Use research-based knowledge and
research methods including design of experiments, analysis and interpretation of data,
and synthesis of the information to provide valid conclusions.
 Modern tool usage: Create, select, and apply appropriate techniques, resources, and
modern engineering and IT tools including prediction and modeling to complex
engineering activities with an understanding of the limitations.
 The engineer and society: Apply reasoning informed by the contextual knowledge
to assess societal, health, safety, legal and cultural issues and the consequent
responsibilities relevant to the professional engineering practice.
 Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of,
and need for sustainable development.
 Ethics: Apply ethical principles and commit to professional ethics and responsibilities
and norms of the engineering practice.
 Individual and team work: Function effectively as an individual, and as a member or
leader in diverse teams, and in multidisciplinary settings.
 Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend
and write effective reports and design documentation, make effective presentations, and
give and receive clear instructions.
 Project management and finance: Demonstrate knowledge and understanding of
the engineering and management principles and apply these to one’s own work, as a
member and leader in a team, to manage projects and in multidisciplinary environments.
 Life-long learning: Recognize the need for, and have the preparation and ability to
engage in independent and life-long learning in the broadest context of technological
change.

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 SHRI SWAMI SAMARTH COLLEGE OF ENGINEERING, MALWADI ,BOTA.
DEPARTMENT OF ELECTRONIC’S ENGINEERING

QUALITY POLICY

THE SHRE E SWAM I SAM ART H C OLLEGE OF ENGINE ER ING IS

C OMMIT TE D TO DE VE LOP IN Y OUNG MINDS THE STATE – OF – T HE –
ART TECHNOLO GY AND HIGH AC AD EM IC AMBIENCE BY SYNERGISING
S PIRITUAL VALUE S AND T EC H NOLOGICAL COM PET ENCE CONT INUA LLY
IN A LEAR NING ENV IRO NME NT.

QUALITY OBJECTIVES
 To improve overall development of student.

 To enhance industry-institute interaction.

 To provide assistance for placement & entrepreneurship development.

 To promote and encourage R&D activities.

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 SHRI SWAMI SAMARTH COLLEGE OF ENGINEERING, MALWADI ,BOTA.
DEPARTMENT OF ELECTRONIC’S ENGINEERING

Digital Electronics

Experiment No: 1 Study of Logic gates and their ICs and universal gates. Page

AIM: Study of Logic gates and their ICs and universal gates.

Objective:
1. To study the basic logic gates: AND, OR, NOT, NAND, NOR, XOR, XNOR.
2. To verify their truth tables using ICs.
3. To verify that NAND and NOR gates are universal gates.

Apparatus Required:

Sr. No. Component IC Number Quantity

1 AND Gate IC 7408 1
2 OR Gate IC 7432 1
3 NOT Gate IC 7404 1
4 NAND Gate IC 7400 1
5 NOR Gate IC 7402 1
6 XOR Gate IC 7486 1
7 XNOR Gate IC 4077 or 74266 1
8 Breadboard – 1
9 Connecting wires – As required
10 Power supply (5V DC) – 1
11 LEDs or logic probe – As required

Theory:
Logic gates are the building blocks of Digital Electronics.
Each gate performs a basic logic function:

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 SHRI SWAMI SAMARTH COLLEGE OF ENGINEERING, MALWADI ,BOTA.
DEPARTMENT OF ELECTRONIC’S ENGINEERING

Gate Boolean Expression Logic Symbol Function

AND Y = A·B 7408 Output is 1 only if both inputs are 1
OR Y =A+ B 7432 Output is 1 if any input is 1
NOT Y=Ā 7404 Output is the complement of input
NAND Y = (A·B)’ 7400 Complement of AND
NOR Y = (A + B)’ 7402 Complement of OR
XOR Y = A⊕B 7486 Output is 1 when inputs differ
XNOR Y = (A⊕B)’ 4077 Output is 1 when inputs are same

Truth Tables:
(i) Basic Gates:
A B AND OR NAND NOR XOR XNOR
0 0 0 0 1 1 0 1
0 1 0 1 1 0 1 0
1 0 0 1 1 0 1 0
1 1 1 1 0 0 0 1

(ii) NOT Gate:

A Y=Ā
0 1
1 0

Verification of Universal Gates:

(a) NAND Gate as Universal Gate

 NOT using NAND:

Connect both inputs of NAND gate together.
Output = (A·A)’ = Ā
 AND using NAND:
Y = ((A·B)’)’ = A·B
 OR using NAND:
Y = ((A’)·(B’))’ = A + B

(b) NOR Gate as Universal Gate

 NOT using NOR:

Connect both inputs of NOR gate together.
Output = (A + A)’ = Ā

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DEPARTMENT OF ELECTRONIC’S ENGINEERING

 OR using NOR:
Y = ((A + B)’)’ = A + B
 AND using NOR:
Y = ((A’) + (B’))’ = A·B

Circuit Diagrams:

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DEPARTMENT OF ELECTRONIC’S ENGINEERING

Procedure:
1. Connect the IC on the breadboard carefully.
2. Give +5V supply to Vcc and GND to ground pins.
3. Connect inputs A and B to switches or logic inputs.
4. Observe output using LED or logic probe.
5. Verify output with the truth table.
6. Repeat for all the gates and universal gate combinations.

Observations:

Result:
1. Truth tables for all logic gates were verified successfully.
2. NAND and NOR gates were proved to be universal gates.

Conclusion:
All basic logic gates and their operations were studied using ICs. It is verified that NAND and NOR
gates can be used to implement any other gate, proving they are universal logic gates.

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 SHRI SWAMI SAMARTH COLLEGE OF ENGINEERING, MALWADI ,BOTA.
DEPARTMENT OF ELECTRONIC’S ENGINEERING

Digital Electronics

Implement AND, OR, NOT, XOR, XNOR using NAND

Experiment No: 2 Page
gates

AIM: Implement AND, OR, NOT, XOR, XNOR using NAND gates.

Objective:
To design and verify the logic circuits of AND, OR, NOT, XOR, and XNOR gates using only
NAND gates.

Apparatus Required:
Sr. No. Component IC Number Quantity
1 NAND Gate IC 7400 1
2 Breadboard – 1
3 Connecting wires – As required
4 Power supply (5V DC) – 1
5 LEDs / Logic probe – As required

Theory:
The NAND gate is a universal gate — meaning all other logic functions can be implemented using
only NAND gates.

The Boolean expression for a NAND gate is:

Y= (A⋅B) ′Y = (A . B)'Y=(A⋅B)′

Implementation Using NAND Gates:

Logic Diagram / Formula Using NAND

Gate Expression
Gates
1. NOT Connect both inputs of a NAND gate Y=(A⋅A)′=AˉY = (A \cdot A)' =
Gate together. \bar{A}Y=(A⋅A)′=Aˉ
2. AND Output of NAND is inverted using another Y=((A⋅B)′)′=A⋅BY = ((A \cdot B)')' = A \cdot

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DEPARTMENT OF ELECTRONIC’S ENGINEERING

Logic Diagram / Formula Using NAND

Gate Expression
Gates
Gate NAND gate. BY=((A⋅B)′)′=A⋅B
Apply De Morgan’s theorem:
A+B=(Aˉ⋅Bˉ)′A + B = (\bar{A} \cdot
Y=((A⋅A)′⋅(B⋅B)′)′=A+BY = ((A \cdot A)'
3. OR \bar{B})'A+B=(Aˉ⋅Bˉ)′.
\cdot (B \cdot B)')' = A +
Gate Step 1: Invert A and B using NANDs.
BY=((A⋅A)′⋅(B⋅B)′)′=A+B
Step 2: Apply NAND to both inverted
outputs.
XOR = ABˉ+AˉBA \bar{B} + \bar{A}
BABˉ+AˉB.
Implementation with NANDs:
1. X1=(A⋅B)′X1 = (A \cdot B)'X1=(A⋅B)′
4. XOR 2. X2=(A⋅X1)′X2 = (A \cdot
Y=A⊕BY = A \oplus BY=A⊕B
Gate X1)'X2=(A⋅X1)′
3. X3=(B⋅X1)′X3 = (B \cdot
X1)'X3=(B⋅X1)′
4. Y=(X2⋅X3)′Y = (X2 \cdot
X3)'Y=(X2⋅X3)′
5.
XNOR Complement of XOR output using NAND. Y=(A⊕B)′Y = (A \oplus B)'Y=(A⊕B)′
Gate

Truth Tables:

A B AND OR NOT(A) XOR XNOR

0 0 0 0 1 0 1
0 1 0 1 1 1 0
1 0 0 1 0 1 0
1 1 1 1 0 0 1

Circuit Description:

1. NOT Gate: Connect both inputs of a NAND gate to same input A.

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DEPARTMENT OF ELECTRONIC’S ENGINEERING

2. AND Gate: Output of one NAND gate goes into another NAND gate configured as inverter.

3. OR Gate: Invert both inputs using NANDs and feed them to a third NAND.

4. XOR Gate: Use four NAND gates as per Boolean construction.

5. XNOR Gate: Connect XOR output to another NAND inverter.

Procedure:
1. Connect IC 7400 (NAND gate) on breadboard.
2. Give Vcc = +5V to pin 14 and GND to pin 7.

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 SHRI SWAMI SAMARTH COLLEGE OF ENGINEERING, MALWADI ,BOTA.
DEPARTMENT OF ELECTRONIC’S ENGINEERING

3. Connect input combinations for A and B using switches.

4. Observe the output on LED for each case.
5. Verify outputs with truth tables.

Observation Table:
Record outputs for all input combinations and compare with theoretical values.

Result:
All the logic gates (AND, OR, NOT, XOR, and XNOR) were successfully implemented and
verified using only NAND gates.

Conclusion:
The NAND gate is verified as a universal logic gate since it can be used to implement all basic and
derived logic functions.

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 SHRI SWAMI SAMARTH COLLEGE OF ENGINEERING, MALWADI ,BOTA.
DEPARTMENT OF ELECTRONIC’S ENGINEERING

Digital Electronics
Implement AND, OR, NOT, XOR, XNOR using NOR
Experiment No: 3 Page
gates.

AIM: Implement AND, OR, NOT, XOR, XNOR using NOR gates..

Objective:
To design and verify the logic circuits of AND, OR, NOT, XOR, and XNOR gates using only
NOR gates.

Apparatus Required:

Sr. No. Component IC Number Quantity

1 NOR Gate IC 7402 1
2 Breadboard – 1
3 Connecting wires – As required
4 Power supply (5V DC) – 1
5 LEDs / Logic probe – As required

Theory:
The NOR gate is also a universal gate, meaning we can implement all other logic functions using
only NOR gates.

The Boolean equation for a NOR gate is:

Y=(A+B)′Y = (A + B)'Y=(A+B)′

Implementation Using NOR Gates:

Logic Diagram / Formula Using NOR

Gate Expression
Gates
1. NOT Connect both inputs of a NOR gate Y=(A+A)′=AˉY = (A + A)' =
Gate together. \bar{A}Y=(A+A)′=Aˉ

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DEPARTMENT OF ELECTRONIC’S ENGINEERING

Logic Diagram / Formula Using NOR

Gate Expression
Gates
Y=((A+B)′)′=A+BY = ((A + B)')' = A +
2. OR Output of a NOR is inverted using another
BY=((A+B)′)′=A+B
Gate NOR gate.

Using De Morgan’s theorem:

A⋅B=(Aˉ+Bˉ)′A . B = (\bar{A} +
3. AND \bar{B})'A⋅B=(Aˉ+Bˉ)′. Y=((A+A)′+(B+B)′)′=A⋅BY = ((A + A)' + (B
Gate Step 1: Invert A and B using two NOR + B)')' = A \cdot BY=((A+A)′+(B+B)′)′=A⋅B
gates.
Step 2: Feed them to a third NOR gate.
XOR = ABˉ+AˉBA \bar{B} + \bar{A}
BABˉ+AˉB.
Implementation using NOR:
1. X1=(A+B)′X1 = (A + B)'X1=(A+B)′
4. XOR 2. X2=(A+X1)′X2 = (A +
Y=A⊕BY = A \oplus BY=A⊕B
Gate X1)'X2=(A+X1)′
3. X3=(B+X1)′X3 = (B +
X1)'X3=(B+X1)′
4. Y=(X2+X3)′Y = (X2 +
X3)'Y=(X2+X3)′
5.
Complement of XOR output using a NOR
XNOR Y=(A⊕B)′Y = (A \oplus B)'Y=(A⊕B)′
inverter.
Gate

Truth Tables:

A B AND OR NOT(A) XOR XNOR

0 0 0 0 1 0 1
0 1 0 1 1 1 0
1 0 0 1 0 1 0
1 1 1 1 0 0 1

Circuit Description:

1. NOT Gate: Both inputs of NOR gate connected to same input A.

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DEPARTMENT OF ELECTRONIC’S ENGINEERING

2. OR Gate: One NOR gate gives (A + B)’, next NOR gate inverts it.

3. AND Gate: Two NOR gates used as NOT gates for A and B, and one more NOR gate to
combine outputs.

4. XOR Gate: Four NOR gates connected as per Boolean realization.

5. XNOR Gate: XOR output passed through a NOR inverter.

Procedure:
1. Place IC 7402 (NOR gate) on the breadboard.

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DEPARTMENT OF ELECTRONIC’S ENGINEERING

2. Connect Vcc = +5V (Pin 14) and GND = Pin 7.

3. Connect input combinations for A and B using switches.
4. Observe output on LED for each configuration.
5. Verify outputs with the theoretical truth table.

Observation Table:

Record the observed output for each input combination and compare it with theoretical values.

Result:
All the basic and derived logic gates (AND, OR, NOT, XOR, and XNOR) were successfully
implemented and verified using only NOR gates.

Conclusion:
It is verified that the NOR gate is a universal gate, as it can be used to construct all other logic
gates.

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DEPARTMENT OF ELECTRONIC’S ENGINEERING

Digital Electronics

Experiment No: 4 Verifying De Morgan's laws. (Using Logic gates) Page

AIM: Verifying De Morgan's laws. (Using Logic gates)

Objective
1. To verify De Morgan’s first law: (A⋅B)′=A′+B′(A . B)' = A' + B'(A⋅B)′=A′+B′.
2. To verify De Morgan’s second law: (A+B)′=A′⋅B′(A + B)' = A' . B'(A+B)′=A′⋅B′.
3. To implement both laws using (a) basic gates (AND, OR, NOT) and (b) only NAND or only
NOR gates, and compare outputs.

Apparatus / Components
 Breadboard
 Power supply +5 V DC
 ICs: 7408 (AND), 7432 (OR), 7404 (NOT) — or equivalently 7400 (NAND) and 7402
(NOR) if implementing with only NAND/NOR
 LEDs (with 330Ω resistors) or logic probes (2)
 Push switches or toggle switches for inputs A and B (2)
 Connecting wires/jumpers
 (Optional) IC datasheets for pin numbers

Theory / Statements to Verify

1. First law: (A⋅B)′=A′+B′

(A . B)' = A' + B'(A⋅B) ′=A′+B′

— The complement of an AND is the OR of the complements.

2. Second law: (A+B)′=A′⋅B′

3. (A + B)' = A' .B'(A+B)′=A′⋅B′

— The complement of an OR is the AND of the complements.

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DEPARTMENT OF ELECTRONIC’S ENGINEERING

We will prove both by (a) building left-hand and right-hand circuits and comparing outputs
(LEDs/logic probe) for all input combinations, and (b) truth tables.

Implementation — Circuits
A. Implementation with basic gates (AND, OR, NOT)

1) First law — left side (LHS):

 Circuit LHS1 = NAND of A and B followed by NOT: simpler to use a NOT on output of
AND then observe (or directly use NAND as (A·B)')
 If using basic gates: connect AND gate output to NOT gate → output = (A·B)'

1) First law — right side (RHS):

 Invert A with NOT → A'

 Invert B with NOT → B'
 Feed A' and B' into OR → output = A' + B'

2) Second law — left side (LHS):

 LHS2 = NOT of OR: connect OR(A,B) → NOT → output = (A + B)'

2) Second law — right side (RHS):

 A' = NOT(A), B' = NOT(B)

 AND(A', B') → output = A' · B'

Wire LEDs (with resistors) to the outputs of LHS and RHS for each law (label them LHS1, RHS1,
LHS2, RHS2).

B. Implementation using only NAND gates (alternate)

First law with NAND-only:

 LHS: Single NAND on A,B produces (A·B)'.

 RHS: produce A' by NAND(A,A); produce B' by NAND(B,B); then NAND(A', B') gives
(A'·B')' — but we need A' + B'. Use De Morgan: A' + B' = ( (A')·(B') )' so NAND(A',B')
already gives RHS. So with NAND-only:
o A' = NAND(A,A)
o B' = NAND(B,B)
o RHS = NAND(A', B') → equals A' + B' (same as LHS)

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Second law with NAND-only:

 LHS: NAND(NAND(A,B), NAND(A,B)) to invert (A·B)'? Simpler to use NOR-only for

second law; but you can still build:
o OR under NAND formulation is trickier — you can implement OR using NAND
(A+B = NAND(NAND(A,A), NAND(B,B))) then invert for LHS as needed.
(Complete steps below in procedure.)

(If you prefer, implement NAND-only for first law and NOR-only for second law — both
demonstrate universality and De Morgan.)

Pin / IC suggestions
 7408 (AND): Vcc pin 14, GND pin 7
 7432 (OR): Vcc 14, GND 7
 7404 (NOT): Vcc 14, GND 7
 7400 (NAND), 7402 (NOR): same Vcc/GND pins

(If you want, I can give exact pin numbers for each gate within the IC packages for drawing.)

Truth Table (verify both laws)

Create a table for inputs A, B and outputs:

A B (A·B)' (LHS1) A' B' A' + B' (RHS1) Match? (A+B)' (LHS2) A'·B' (RHS2) Match?
0 0 1 1 1 1 YES 1 1 YES
0 1 1 1 0 1 YES 0 0 YES
1 0 1 0 1 1 YES 0 0 YES
1 1 0 0 0 0 YES 0 0 YES

You should observe identical outputs for LHS and RHS columns in each law.

Procedure (step-by-step)
1. Place ICs on the breadboard and connect Vcc (+5V) and GND properly.
2. Connect input switches for A and B (0 = open or ground, 1 = +5V through pull-up/pull-
down as per your wiring). Use debounced switches or stable logic levels.
3. Basic-gate build for first law:
o Connect A and B to AND gate output.

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o Feed AND output into NOT gate → wire LED to this output (label LHS1).
o Separately, feed A to NOT → A', feed B to NOT → B', then OR(A',B') → wire LED
(RHS1).
4. Toggle A,B through all 4 combinations and record states of LHS1 and RHS1 (LED on/off or
logic probe high/low). Fill truth-table.
5. Basic-gate build for second law:
o Connect A and B to OR gate, feed OR output to NOT → LED (LHS2).
o Feed A to NOT → A', B to NOT → B', then AND(A',B') → LED (RHS2).
6. Toggle inputs through all combinations and record LHS2 and RHS2. Fill truth-table.
7. Optional: Repeat both verifications using only NAND gates and only NOR gates to show
universality:
o For NAND-only (first law): A' = NAND(A,A), B' = NAND(B,B), RHS1 =
NAND(A',B') and LHS1 = NAND(A,B).
o For NOR-only (second law): A' = NOR(A,A), B' = NOR(B,B), RHS2 = NOR(A',B')
and LHS2 = NOR(A,B).
8. Confirm outputs match for all input combos.

Observations
 For every combination of A and B, outputs of LHS and RHS for each law are identical.
 Record LED states (ON = 1, OFF = 0) in the table above.

Result
 De Morgan’s laws (A⋅B)′=A′+B′(A. B)' = A' + B'(A⋅B)′=A′+B′ and (A+B)′=A′⋅B′(A + B)' =
A' . B'(A+B)′=A′⋅B′ are verified experimentally using logic gates.
 They also hold when implemented using only NAND or only NOR gates, confirming the
logical equivalences and the universality of NAND/NOR.

Conclusion:
The practical verifies De Morgan’s theorems for all input combinations. Implementation using both
basic gates and universal gates (NAND/NOR) shows the identities hold in real logic circuits and
confirms that inversion distributes across AND/OR as De Morgan states.

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DEPARTMENT OF ELECTRONIC’S ENGINEERING

Digital Electronics
Implement the given Boolean expressions using minimum
Experiment No: 5 Page 1/10
number of gates.

Aim: - Implement the given Boolean expressions using minimum number of gates.

APPARATUS REQUIRED:
 Breadboard
 Connecting wires
 Power supply (5V)
 Logic ICs (as required):
o IC 7408 – AND gate
o IC 7432 – OR gate
o IC 7404 – NOT gate
o IC 7400 – NAND gate (optional for NAND-only implementation)
o IC 7402 – NOR gate (optional)

THEORY:
A Boolean expression can often be implemented using fewer gates by simplifying it using Boolean
algebra rules and Karnaugh Maps (K-maps).
The simplified expression reduces the number of gates, ICs, propagation delay, and overall cost of
the circuit.
Universal gates (NAND / NOR) can implement any Boolean function and often reduce gate count.

PROCEDURE:
1. Write the given Boolean expressions.
2. Simplify each expression using Boolean algebra and/or Karnaugh Map (K-map).
3. Draw the simplified logic circuit.
4. Implement the circuit on the breadboard using ICs.
5. Apply all combinations of inputs and note the outputs in the truth table.
6. Verify the correctness of the implemented circuit.

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EXAMPLE IMPLEMENTATIONS

Example 1
Given Expression:
F=AB+AC F = AB + AC F=AB+AC
Simplification:
F=A(B+C) F = A(B + C) F=A(B+C)
Minimum Gates Required:
 1 OR gate (2-input)
 1 AND gate

Logic Diagram:
A → AND → F
B,C → OR → AND input

Example 2
Given Expression:
F=A′B+AB′F = A'B + AB'F=A′B+AB′
Simplification:
F=A⊕B F = A ⊕B F=A⊕B
Minimum Gates Required:
 1 XOR gate
(or 4 NAND gates if using NAND-only)

Logic Diagram:
A,B → XOR → F

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Example 3
Given Expression:
F=Σ(1,3,5,7)

F = ∑(1,3,5,7)

F=Σ(1,3,5,7)
K-map Simplification:

F=B⊕C

Minimum Gates Required:

 1 XOR gate
(or 4 NAND gates)

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TRUTH TABLE :
A B C F
0 0 0 0
0 0 1 1
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 1
1 1 1 0

OBSERVATION:
The output observed from the hardware implementation matches the truth table of the simplified
Boolean expression.

RESULT:
The given Boolean expressions were successfully simplified and implemented using the minimum
number of logic gates. The output was verified using the truth table.

CONCLUSION:
Simplifying Boolean expressions before implementation reduces gate count, hardware complexity,
power consumption, and propagation delay. The experiment demonstrates practical gate-level
optimization.

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Digital Electronics

Experiment No: 6 Design and implement Half adder and Full adder Page 1/4

AIM:

Design and implement Half adder and Full adder

2. Apparatus Required
Sr. No. Equipment / Component Specification / IC No. Quantity
1 AND Gate IC 7408 1
2 OR Gate IC 7432 1
3 XOR Gate IC 7486 1
4 NOT Gate (if required) IC 7404 1
5 LED 5V 2
6 Resistor 330 Ω 2
7 Breadboard – 1
8 Connecting wires – As required
9 DC Power Supply +5V 1

3. Theory
Half Adder
A Half Adder is a combinational circuit that performs addition of two single-bit binary numbers.
It produces two outputs:

 Sum (S)
 Carry (C)

Truth Table:
A B Sum (S) Carry (C)
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Boolean Expressions:

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 Sum = A ⊕ B = A'B + AB'

 Carry = A · B

Logic Diagram:

 Sum → XOR gate

 Carry → AND gate

Full Adder
A Full Adder is a combinational circuit that adds three binary inputs (A, B, Cin) and produces:

 Sum (S)
 Carry (Cout)

Truth Table:
A B Cin Sum (S) Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Boolean Expressions:

 Sum = A ⊕ B ⊕ Cin
 Carry = AB + ACin + BCin

Implementation Using Two Half Adders and One OR Gate:

1. First Half Adder → adds A and B → produces (S₁, C₁)

2. Second Half Adder → adds S₁ and Cin → produces (S, C₂)
3. OR gate → combines carries: Cout = C₁ + C₂

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4. Logic Diagram
(a) Half Adder

(b) Full Adder

5. Circuit Diagram
(Draw neatly— use proper logic symbols for AND, OR, XOR.)

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6. Procedure
1. Connect +5V and GND to all ICs (Pin 14 → Vcc, Pin 7 → GND).
2. Connect inputs (A, B, Cin) using switches or jumpers.
3. For Half Adder:
o Connect A, B to inputs of XOR gate (7486) → Sum output.
o Connect A, B to inputs of AND gate (7408) → Carry output.
4. For Full Adder:
o Implement as two Half Adders + OR gate:
 A, B → First Half Adder → S₁, C₁
 S₁, Cin → Second Half Adder → S, C₂
 C₁, C₂ → OR gate → Cout
5. Connect output LEDs to Sum and Carry through 330 Ω resistors.
6. Apply all combinations of input and verify the output with the truth table.

7. Observations

Inputs Half Adder Outputs Full Adder Outputs

A B S
--- --- ---
0 0 0
0 1 1
1 0 1
1 1 0
– – –

(Verify practically and tick outputs.)

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8. Result

 Half Adder and Full Adder circuits are successfully designed and implemented using basic
logic gates.
 The experimental results match the theoretical truth table.

9. Applications
 Used in Arithmetic Logic Units (ALU).
 Binary addition in digital computers.
 Basis for designing adders, subtractors, and multipliers.

10. Conclusion
The Half Adder and Full Adder circuits were successfully implemented using logic gates. The
outputs were verified and found correct as per Boolean expressions and truth tables.

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Digital Electronics

Experiment No: 7 Design and implement 4:1 multiplexer. Page 1/4

AIM: Design and implement 4:1 multiplexer.

1. Aim
To design, implement and test a 4:1 Multiplexer using basic logic gates / IC 74153.

2. Apparatus Required
Sr. No. Component / Equipment Specifications / IC No.
1 AND Gate IC 74LS08 / 74HC08
2 OR Gate IC 74LS32 / 74HC32
3 NOT Gate IC 74LS04 / 74HC04
4 Multiplexer IC (optional) 74153 (Dual 4:1 MUX)
5 LEDs 5 mm + 330Ω resistors
6 Breadboard & Wires —
7 DC Power Supply +5V (TTL)

3. Theory
A Multiplexer (MUX) is a combinational circuit that selects one input from multiple inputs and
routes it to a single output line.
A 4:1 MUX has 4 input lines (I0–I3), 2 select lines (S1, S0), and one output Y.

The select inputs decide which data input is transferred to the output.

Truth Table
S1 S0 Selected Input Output Y
0 0 I0 I0
0 1 I1 I1
1 0 I2 I2
1 1 I3 I3

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4. Boolean Expression

This expression is implemented using NOT, AND, and OR gates.

5. Circuit Diagram (Gate Level)

Block Description:

 Two NOT gates generate S1’ and S0’

 Four AND gates generate the product terms
 One OR gate combines all terms to produce output Y

6. Pin Diagram (for IC 74153 – optional method)

If using IC 74153 Dual 4:1 Multiplexer:

 Connect /EN = 0 to enable the multiplexer.

 Inputs: I0, I1, I2, I3
 Select lines: S1, S0
 Output: Y

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7. Procedure
1. Connect 5V power supply to all ICs (Vcc to pin 14, GND to pin 7 for TTL ICs).
2. Connect NOT gates to generate S1' and S0'.
3. Connect the corresponding NOT outputs and input lines to each AND gate as per Boolean
equation.
4. Combine AND gate outputs using an OR gate to generate Y.
5. Connect LEDs to I0–I3 and Y to observe selected output.
6. Apply all combinations of select inputs (00, 01, 10, 11).
7. Verify that the output Y follows the selected input.
8. Record the observations.

8. Observation Table
I3 I2 I1 I0 S1 S0 Expected Y Observed Y
0 0 0 1 0 0 1
0 0 1 0 0 1 1
0 1 0 0 1 0 1
1 0 0 0 1 1 1

(Add more rows if needed)

9. Result
The 4:1 Multiplexer was successfully designed and implemented using logic gates / IC 74153.
The output Y correctly follows the selected input as per the truth table.

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Digital Electronics
Design and implement 1:4 Demultiplexer. Study of IC
Experiment No: 8 Page
74139

AIM: Design and implement 1:4 Demultiplexer. Study of IC 74139

APPARATUS :-
Digital trainer kit, Connecting probes, Digital IC tester, DMM etc

1. Aim
Design and implement a 1-to-4 demultiplexer and study the operation and pin-out of the 74139
(dual 2→4 decoder / demultiplexer) IC.

2. Components / Apparatus
Sr.
Item Example / Part No. Qty
No.
74LS139 / 74HC139 /
1 Dual 2→4 decoder / demux IC 1
SN74xx139
Hex inverter (if required for active-high
2 7404 / 74HC04 1
outputs)
3 Breadboard — 1
4 DC power supply +5 V (for TTL) 1
4 (for
5 LEDs 5 mm
outputs)
6 Resistors 330 Ω (for each LED) 4
7 Toggle switches / jumpers for D, S1, S0 as required
8 Connecting wires — as required
9 Logic probe (optional) — 1

3. Theory (short)
A 1:4 demultiplexer routes a single data input D to one of four outputs Y0..Y3 depending on select
lines S1 (MSB) and S0 (LSB).

Canonical behaviour (active-HIGH outputs):

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The 74139 is a dual 2→4 decoder/demultiplexer: it contains two independent sections (call them
Section A and Section B). Each section has:

 two address/select inputs (A0, A1),

 four active-LOW outputs Y0'..Y3' (i.e. the selected output goes LOW),
 an active-LOW enable (E_bar) that must be LOW to enable a section. The enable input can
be used as the data input for demultiplexer applications. Build Electronic Circuits+1

Note: Because the 74139 outputs are active-LOW, the selected output goes LOW when enabled.
For active-HIGH demux outputs, either invert the 74139 outputs (using 7404) or interpret LOW as
the asserted output.

4. IC 74139 — Pin mapping (16-pin DIP, top view)

Pins (top view):

 Pin 1 — 1-E (enable for section A) (active LOW: enable when 0)

 Pin 2 — 1-A0 (address / select bit 0 for section A)
 Pin 3 — 1-A1 (address / select bit 1 for section A)
 Pin 4 — 1-Y0 (output 0) (active LOW)
 Pin 5 — 1-Y1 (output 1) (active LOW)
 Pin 6 — 1-Y2 (output 2) (active LOW)
 Pin 7 — 1-Y3 (output 3) (active LOW)
 Pin 8 — GND
 Pin 9 — 2-Y3 (section B output 3) (active LOW)
 Pin 10 — 2-Y2 (active LOW)
 Pin 11 — 2-Y1 (active LOW)
 Pin 12 — 2-Y0 (active LOW)
 Pin 13 — 2-A1 (section B A1)
 Pin 14 — 2-A0 (section B A0)
 Pin 15 — 2-E (section B enable, active LOW)
 Pin 16 — Vcc (+5 V)

4. Truth table (1:4 demux, desired active-HIGH outputs)

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S1 S0 Y3 Y2 Y1 Y0
0 0 0 0 0 D
0 1 0 0 D 0
1 0 0 D 0 0
1 1 D 0 0 0

With 74139 (active-LOW outputs), the actual outputs will be inverted: Yk' = 0 for selected output
when enabled and D=1 (or when enable indicates data). See implementation notes below.

6. Implementation methods (practical)

Method A — Use 74139 directly as active-LOW 1:4 demux (no output
inversion)
 Connect select inputs: A0 = S0 → Pin 2, A1 = S1 → Pin 3 (for section A).
 Use the Enable (Pin 1) as the inverted data input: tie E = NOT(D) (i.e. connect pin 1 to the
logic level that is LOW when you want the output active).
o If D = 1 (logic HIGH), set E = 0 (LOW) so the addressed output goes LOW.
o If D = 0, set E = 1 (HIGH) so no outputs are active (all outputs remain HIGH).
 The outputs (Pins 4–7) will be active-LOW: the selected output will be 0 when D=1; others
will be 1.
 Useful when you are OK with active-LOW signalling (or your next stage is active-LOW).

Wiring summary (section A):

 Pin 16 → +5V, Pin 8 → GND

 Pin 2 ← S0 (LSB)
 Pin 3 ← S1 (MSB)
 Pin 1 ← NOT(D) (i.e., if D logic HIGH = 1, connect Pin1 to 0 via inverter or drive Pin1
with D through an inverter)
 Pins 4–7 → outputs (Y0'..Y3') → LEDs (with resistors) note LEDs will light when output =
LOW only if LED tied to Vcc via resistor (use correct polarity)

Important: Because outputs are active LOW, to display output with LEDs in conventional active-
HIGH style (LED ON when output asserted), you can connect LED anode to +5V via resistor and
LED cathode to the 74139 output pin. The LED will light when output = LOW (current flows from
+5V through resistor → LED → 74139 output to GND). (This is normal for active-LOW outputs;
take care with polarity and current limits.)

Method B — Active-HIGH outputs (make 74139 behave as standard demux)

Two options:

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1. Invert the 74139 outputs with hex inverter (7404 or 74HC04): feed pins 4–7 to 4 of the
7404 inputs; outputs from 7404 are active HIGH and can drive LEDs normally. (Simple,
reliable.)
2. Or invert E and invert outputs logically (less common). Best practice: use 7404 on outputs.

Wiring summary for Method B (active-HIGH outputs):

 Use Method A wiring, but feed each 74139 output (pins 4–7) into an inverter (7404) input;
take inverted outputs from the 7404 to drive LEDs or downstream logic.

7. Circuit diagrams (conceptual)

A — 74139 used as 1:4 demux (active-LOW outputs; E = NOT(D))

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B — For active-HIGH outputs: add 7404 inverters:

74139 Y0' --(to 7404)--> Y0 (active HIGH)
74139 Y1' --(to 7404)--> Y1
...

8. Procedure (step-by-step)
1. Power & placement
o Insert 74139 on breadboard; connect Vcc (Pin16) → +5V, GND (Pin8) → 0V.
o If using 7404 for inversion, place it and wire Vcc/GND (7404 pin14 → +5V, pin7 →
GND for 14-pin 7404).
2. Inputs
o Connect S0 to Pin2 and S1 to Pin3 (section A). Use toggle switches or jumpers to
apply 0/1.
o Prepare Data input D (0 or 1) using a switch or jumper.
3. Enable wiring
o For active-LOW output operation (Method A): drive Pin1 with NOT(D) (use a 7404
inverter between D and Pin1, or wire Pin1 to the opposite logic level manually).
o If you don't have inverter, you can toggle enable and D appropriately to observe
effect.
4. Outputs
o Connect LEDs (with 330 Ω resistors) to pins 4–7.
 If showing active-LOW directly: connect LED anode → +5V via 330 Ω,
cathode → 74139 output pin. LED lights when output = 0.
 If using 7404 to invert outputs (active-HIGH): connect LED anode → 7404
output via resistor → LED cathode → GND (normal polarity).
5. Test
o For each combination of S1,S0 (00, 01, 10, 11), set D = 1 and verify the
corresponding output becomes active (LOW if not inverted, HIGH if inverted).
o Set D = 0 and verify no output is asserted (all outputs inactive: HIGH for 74139
outputs).
6. Record observations (use table below).

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Observation table (sample to fill during experiment)

Test S1 S0 D Expected (active-LOW outputs) Observed (pin4..pin7) Remarks

1 0 0 1 Y0' = 0, others = 1
2 0 1 1 Y1' = 0, others = 1
3 1 0 1 Y2' = 0, others = 1
4 1 1 1 Y3' = 0, others = 1
5 x x 0 all outputs = 1 (disabled)

9. Result
 On following the wiring and procedure, the 74139 section correctly demultiplexed the data
input to the selected output: when D=1 and S1,S0 set to a combination, the addressed output
became active (active-LOW at 74139 output, or active-HIGH after inversion).
 When D=0, no outputs were asserted (all outputs inactive).

Conclusion:

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Digital Electronics
Design of 3-bit synchronous counter using 7473 and required
Experiment No: 9 Page
gates

AIM
Design of 3-bit synchronous counter using 7473 and required gates

APPARATUS / ICs REQUIRED

 IC 7473 (Dual JK flip-flop with asynchronous clear) — 2 nos. (one will have one flip-flop
unused) Alldatasheet+1
 IC 7408 (2-input AND gates) — 1 no. (or any equivalent 2-input AND gate)
 LEDS (3) with series resistors (≈ 330 Ω) — for Q2,Q1,Q0 indicators
 Connecting wires, breadboard, +5 V DC regulated supply, ground
 SPST push-button (optional) for clock source or function generator / clock module
 Pull-up resistors (10 kΩ) for asynchronous CLEAR pins (if required)
 Decoupling capacitor 0.1 µF across VCC–GND near ICs

THEORY & DESIGN PRINCIPLE:

A synchronous binary up-counter with JK flip-flops uses the JK inputs to control whether each bit
toggles on a clock pulse. For an n-bit binary up counter:

 LSB (Q0) toggles on every clock → J0 = K0 = 1

 Next bit (Q1) toggles when Q0 = 1 → J1 = K1 = Q0
 Next bit (Q2) toggles when Q1 & Q0 = 1 → J2 = K2 = Q1 · Q0

So for a 3-bit counter (Q2 Q1 Q0):

J0 = 1, K0 = 1
J1 = Q0, K1 = Q0
J2 = Q1·Q0,K2 = Q1·Q0

Because for JK flip-flops: J=K=1 → toggle; J=1,K=0 → set; J=0,K=1 → reset; J=K=0 → no
change. (Use the JK excitation behavior when deriving inputs.)

TRUTH TABLE (DESIRED COUNT SEQUENCE)

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Present (Q2 Q1 Q0) Next (Q2⁺ Q1⁺ Q0⁺)

000 001
001 010
010 011
011 100
100 101
101 110
110 111
111 000

(You will verify this in the observations.)

EXCITATION / INPUTS FOR JK FLIP-FLOPS

From the design principle:

 For FF0 (LSB): tie J0 = K0 = HIGH (logic 1). (This makes Q0 toggle each clock.)
 For FF1: J1 = K1 = Q0.
 For FF2: J2 = K2 = Q1 · Q0 (one 2-input AND gate required).

Thus only one 2-input AND gate is required externally.

LOGIC EQUATIONS (SUMMARY)

J0 = 1
K0 = 1

J1 = Q0
K1 = Q0

J2 = Q1 AND Q0
K2 = Q1 AND Q0

IC / GATE CONNECTION SUMMARY (practical wiring notes)

1. Power & decoupling

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o Connect VCC of each IC to +5 V and GND to 0 V. Place 0.1 µF decoupling

capacitor across VCC–GND near the IC.
2. Clock
o All three flip-flops share the same clock input (synchronous design). Tie the clock
pins of all three FFs together and feed the clock source (push-button with
debouncing OR a stable square wave generator). Remember 7473 triggers on falling
edge. Alldatasheet
3. Asynchronous CLEAR (CLR)
o Tie each CLR pin HIGH (+5 V) via a 10 kΩ resistor. If you want an active reset
push-button, place a normally-open pushbutton that when pressed pulls CLR LOW
to reset all outputs.
4. FF0 (Q0)
o Tie J0 and K0 to logic HIGH (+5 V). (If using TTL ICs, tie to VCC through small
resistor or directly as per datasheet practice.)
5. FF1 (Q1)
o Connect J1 and K1 to Q0.
6. FF2 (Q2)
o Use one 2-input AND gate (from 7408): inputs = Q1 and Q0. Output of that AND
fed to both J2 and K2.
7. Outputs
o Connect Q0, Q1, Q2 to LEDs (through 330 Ω resistors) to observe count in binary
(LSB = Q0). If your 7473 variant gives complementary outputs (/Q), use whichever
Q output is convenient.

MINIMUM GATES / ICS REQUIRED

 7473: two ICs (each contains two JK flip-flops) — to realize 3 flip-flops (one flip-flop on
the second IC unused).
 7408 (2-input AND) — one gate package (can use a single gate inside a 7408 IC; 7408
contains 4 independent 2-input ANDs).

Total external gates: 1 two-input AND (plus wiring and pull-ups). The 7473 provides JK
functionality so no other gates for J/K are required.

CONNECTION / CIRCUIT DIAGRAM (schematic overview)

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PROCEDURE (Step-by-Step)
1. Place two 7473 ICs and one 7408 on the breadboard. Connect VCC and GND on each IC to
+5 V and GND. Add decoupling caps. Alldatasheet
2. Tie each CLR pin HIGH via 10 kΩ pull-ups. Optionally add a pushbutton to pull CLR LOW
for global reset.
3. Tie the clock pins of the three flip-flops together (use the CLK pins for the three flip-flops in
the two 7473 chips). Connect clock source (pushbutton with debouncing or square-wave
generator). Remember the 7473 is negative-edge triggered (output changes at falling edge).
Alldatasheet
4. Connect J0 and K0 to HIGH (+5 V) so Q0 toggles on every falling clock edge.
5. Connect J1 and K1 to Q0 (wire Q0 output to J1 and K1).
6. Connect a 2-input AND gate (one gate of 7408) with inputs Q1 and Q0; feed its output to J2
and K2.
7. Put LEDs on Q0, Q1, Q2 via 330 Ω resistors to observe the count.
8. Apply power. Start clock pulses and observe LED sequence; record the observed sequence
and verify it matches the truth table.

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OBSERVATION
 LEDs for Q2,Q1,Q0 should show the binary count sequence 000 → 001 → 010 → ... → 111
→ 000 on successive falling clock edges.
 If any unwanted states or glitches occur, check: clock debouncing, that CLR is not floating,
and that setup/hold times are respected (change inputs only when clock is not active).

RESULT
A 3-bit synchronous binary up-counter was designed and implemented using two 7473 dual JK flip-
flop ICs and one 2-input AND gate. The counter advances binary values 0–7 synchronously on each
falling edge of the clock.

Conclusion:

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Digital Electronics
Study of IC 7490, 7492, 7493 and designing mod-n
Experiment No: 10 Page
counters using these.

Aim: Study of IC 7490, 7492, 7493 and designing mod-n counters using these.:

Aim
1. To study the operation and pin configuration of ICs 7490, 7492, and 7493.
2. To implement and test Mod-N counters (examples: Mod-2, Mod-5, Mod-10, Mod-12, Mod-
16) using these ICs.
3. To demonstrate reset/feedback methods for obtaining arbitrary modulus counters from these
ICs.

Apparatus / Components
Sr. No. Component Example / Part No. Qty
1 Decade counter IC 74LS90 / SN7490A 1
2 Divide-by-12 counter IC 74LS92 / SN7492 1
3 4-bit binary counter IC 74LS93 / SN7493 1
4 Breadboard — 1
5 +5 V DC power supply 5 V regulated 1
6 LEDs + 330 Ω resistors — 4 (for outputs)
7 Push switches / jumpers — as required
8 Connecting wires, decoupling capacitor 0.1 μF — as required
9 Logic probe / oscilloscope (optional) — 1

Short Theory & Features (summary)

 IC 7490 (74LS90) — Decade / BCD counter internally arranged as a divide-by-2 stage and
a divide-by-5 stage; it can be configured to provide divide-by-10 (count 0–9) or other counts
by wiring/resetting the appropriate pins. It has reset/set inputs to force count states. Basic
Electronics Tutorials+1
 IC 7492 (74LS92) — Divide-by-12 counter (a divide-by-2 stage + divide-by-6 stage
internally). Useful for implementing mod-12 or cascading for clock hours, etc. Build
Electronic Circuits+1
 IC 7493 (74LS93) — 4-bit binary counter (effectively divide-by-2 and divide-by-8
sections: can be configured as a mod-16 counter or used as separate divide-by-2 / divide-by-
8 blocks). It has asynchronous resets and two clock pins for the two sections. Jotrin
Electronics+1

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These ICs are asynchronous (ripple) counters — count advances propagate through flip-flops, so
there’s ripple propagation delay you should be aware of when cascading or observing fast clocks.

Typical Pinouts (14-pin DIP) — verify with your datasheet before

wiring
Important: pin numbers below are typical for SN74LS90, SN74LS92, SN74LS93 families.
Always confirm with the exact datasheet on the chip you have (the functional description below
follows TI datasheet conventions). Texas Instruments+1

IC 74LS90 / 7490 — (typical pins / functions)

(14-pin)

 Pin 14 — CLK A (or CLKA) (clock input for ÷2 stage)

 Pin 1 — CLK B (clock input for ÷5 stage)
 Pins labelled R1, R2, R3, R4 or Reset / Set — asynchronous reset / set inputs (used to
preset or clear)
 Four Q outputs: QA, QB, QC, QD (binary weighted outputs; QA = LSB). Typical pin
mapping shown on datasheets.
 Pin 10 or 11 often GND; VCC is usually pin 5 or 16 depending on package variant — check
your package.

(Reason: 74xx families have variations; consult the manufacturer datasheet for exact pin numbers in
your package.) Microcontrollers Lab+1

IC 74LS92 / 7492 — (typical pins / functions)

 Dual-block counter: divide-by-2 block and divide-by-6 block to make divide-by-12.
 Pins include: CP1 (clock input 1), CP2 (clock input 2), reset inputs, and four outputs
Q0..Q3. Pin numbers and enable/reset specifics in the datasheet. [Link]+1

IC 74LS93 / 7493 — (typical pins / functions)

 Contains a ÷2 stage and a ÷8 stage (combined mod-16).
 Two clock inputs: one for the ÷2 stage (clock A) and one for the ÷8 stage (clock B).
 Reset pins (clear) — asynchronous clear inputs.
 Four outputs Q0 (LSB) .. Q3 (MSB) available. Jotrin Electronics+1

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Internal block (conceptual) — how these chips are organized

 7490: flip-flop A (÷2) → feed its output as clock to the ÷5 chain; the ÷2 and ÷5 combine to
produce divide-by-10 behavior when properly tied. You can also configure it as divide-by-2
only, divide-by-5 only, or BCD (0–9) by wiring resets appropriately. Basic Electronics
Tutorials
 7492: ÷2 block + ÷6 block internally; combine to get ÷12. Use resets/feedback to implement
other mod counts up to 12. makeyourownchip
 7493: separate ÷2 and ÷8 sections — by providing a clock to the ÷2 input only, and routing
outputs appropriately, you can get mod-2, mod-8 or mod-16 behavior. Build Electronic
Circuits

Designing Mod-N Counters — general method (feedback reset)

These TTL counters are asynchronous (ripple). To make a counter of modulus N (< the natural
modulus of the IC), common method is feedback reset:

1. Let the IC count naturally (e.g., 0..9 for 7490).

2. Detect the binary count state equal to N (or to the first state you want to eliminate) using a
small AND / NAND gate tree on the Q outputs (select the Q outputs that are 1 for that binary
pattern).
3. Feed that detection output to the asynchronous reset (or clear) inputs of the counter (active
level depends on the chip — check datasheet). On the next clock (or immediately for
asynchronous clears), the IC resets to 0 — thus the counter cycles through 0..N-1 and
repeats.
4. When using asynchronous resets, ensure the detection logic and reset pulse timing do not
create metastability — simplest is to make the detection high for longer than the propagation
delays, or use gating to synchronize resets on the clock edge if required.

We’ll demonstrate specific Mod-N designs below.

Example implementations (wiring & explanations)

Note: below I give functional wiring diagrams and the typical wiring of detect-and-reset. For exact
pin numbers on your specific chip/package, confirm with the datasheet (links cited).

Using 7490 (74LS90) — Mod-10 (Decade counter) — standard use

 Connect the chip as recommended by datasheet: supply clocks to CLKA (÷2 input) and
connect QA (output of ÷2) to CLKB (÷5 input) to cascade ÷2 → ÷5 giving ÷10.
 Tie reset pins so device counts 0..9. Example wiring and explanation in many tutorials; see
references. Build Electronic Circuits+1

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Procedure (mod-10):

 Connect CLKA (pin) to clock source.

 Connect QA (LSB) to CLKB (the input for the ÷5 section) as the datasheet recommends.
 Ensure reset inputs R1..Rn are tied to inactive level (usually LOW) for normal counting.
 Observe QA..QD representing binary counts 0000..1001 (0..9). Use LEDs for QA..QD.
Basic Electronics Tutorials

Using 7490 — implement Mod-5 (divide-by-5)

 The 7490 contains a ÷5 section — you can use only the ÷5 block by applying the clock to
the proper clock input (the ÷5 clock) and leaving the ÷2 section unused or held inactive per
the datasheet.
 Typical easy method: feed clock to the ÷5 input (the CP1/CP2 pin used for the ÷5 section
per datasheet) and tie/reset the ÷2 section (or ignore QA). Result: outputs reflect 0..4 then
reset. Basic Electronics Tutorials

Using 7490 — implement Mod-2 (divide by 2)

 Use the ÷2 output (QA) — give clock to CLKA and take QA as output; ignore other outputs.
This gives divide-by-2 (toggle) behavior. Basic Electronics Tutorials

Using 7493 (74LS93) — implement Mod-16 (0..15)

 Feed clock to the ÷2 clock input and allow the ÷8 section to cascade — the four outputs
Q0..Q3 give binary 0..15 count naturally. Tie reset inputs inactive. Use Q0..Q3 to display
count. Build Electronic Circuits

Using 7493 — implement Mod-8 or Mod-2

 For divide-by-8: feed clock to the ÷8 clock input and use Q0..Q2 (three outputs) as bits
(counts 0..7).
 For divide-by-2: use Q0 (LSB) as toggle output (feed clock to CLKA). Microcontrollers Lab

Using 7492 — implement Mod-12

 Use the internal ÷2 + ÷6 blocks: feed clock to correct pin (CP1) and use outputs Q0..Q3 for
0..11 counting; reset inactive. The 7492 is provided specifically for divide-by-12 operation.
makeyourownchip

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Example: Building a Mod-6 counter from 7493 (illustration of reset

feedback)
Suppose you want an N = 6 counter (0..5) using 7493 (which naturally can do up to 16). Steps:

1. The binary pattern for 6 is 0110 (Q3Q2Q1Q0 = 0110) but we want to reset when the count
reaches 6, or alternatively detect when count = 6 and reset to 0 so cycle length = 6.
2. Build a detection gate that outputs a HIGH when Q2=1 and Q1=1 and Q3=0 and Q0=0 (i.e.,
the pattern bits for 6). Usually we detect the first unwanted state, so often we detect N (here
6) and use it to clear. For asynchronous clears, you must feed detection to the reset pins
(active level per datasheet).
3. Connect detection logic (AND / NAND as required) to the asynchronous reset inputs of the
7493. On the next clock, the counter resets to 0 — giving counts 0..5.
4. Verify with LEDs at Q0..Q2, stepping the clock and recording observations.

Practical tip: using NAND to drive active-LOW reset is convenient — invert detection logic if reset
is active-LOW. Always check the polarity of the reset inputs on your IC.

Wiring & Breadboard Procedure (generic)

1. Place the chosen IC (7490 / 7492 / 7493) on the breadboard. Connect Vcc (+5 V) and GND
to the IC power pins (see datasheet for exact pin numbers). Add a 0.1 μF decoupling
capacitor across Vcc–GND close to the IC. Texas Instruments
2. Connect clock source (push button for manual stepping or a square-wave clock generator) to
the appropriate clock input pin. Start with low frequency (≤ 1kHz) so LEDs visibly toggle.
3. Tie reset pins to inactive level (usually LOW) unless using them. Use 7404 if you need to
invert the detection signal for active-LOW resets.
4. Connect output LEDs (with 330 Ω resistors) between each Q output and GND (or Vcc
depending on sink/source characteristics). For TTL LS devices, sinking current (LED anode
→ +5 V via resistor, cathode → output) is common — check datasheet for safe current
limits. Build Electronic Circuits
5. For Mod-N designs requiring detection logic, build the small AND / NAND gate using
discrete gates (7408/7400) or small transistor logic. Feed detection to reset inputs as
required.
6. Test for all expected states and record the observed sequences.

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Observation Tables (example to fill)

Example: 7490 configured as Mod-10 (0..9)

Clock pulse # Q3 Q2 Q1 Q0 Decimal count

0 0 0 0 0 0
1 0 0 0 1 1
2 0 0 1 0 2
... ... ... ... ... ...
9 1 0 0 1 9
10 0 0 0 0 0

Example: 7492 as Mod-12

Clock Q3 Q2 Q1 Q0 Decimal
0 0000 0
1 0001 1
... ... ...
11 1011 11
12 0000 0

(Record observed LED states and compare with theory.)

Result
 Using the 74xx counters, you should be able to implement and verify the Mod-N counters
shown above. The 7490 is convenient for decimal/B D C / ÷10 counts; 7493 is a flexible 4-
bit binary counter (÷16); 7492 is for ÷12. Using feedback to reset lets you get arbitrary
moduli < device max state.

COLCLUSION:-
-------------------------------------------------------------------------------------------------------------------------

-------------------------------------------------------------------------------------------------------------------------

-------------------------------------------------------------------------------------------------------------------------

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Digital Electronics

Experiment No: 10 Design and implement a 2-bit by 2-bit multiplier. Page 1/4

AIM: Design and implement a 2-bit by 2-bit multiplier.

Apparatus / Components
Sr.
Component / IC Example / Part No. Qty
No.
1 Breadboard — 1
+5 V (TTL) or +5 V (HC as per
2 DC power supply 1
IC)
4 (for
3 LEDs 5 mm
P3..P0)
4 Resistors 330 Ω 4
5 AND gates 7408 (Quad 2-input AND) 1
6 XOR gates 7486 (Quad 2-input XOR) 1
Optional: Half-Adder IC or 7408+7486 used
7 — —
as HAs
8 Connecting wires, switches (for A & B inputs) — —
9 Decoupling capacitor 0.1 µF 1

Note: If using CMOS (74HCxx) family, use +5V for 74HC series and make sure Vcc/GND pins are
correct.

Theory / Algorithm
Let A = A1 A0 and B = B1 B0 (A1 & B1 are MSBs). Binary multiplication is done by forming
partial products and adding them:

Partial products (ANDs):

 pp0 = A0 · B0
 pp1 = A1 · B0
 pp2 = A0 · B1
 pp3 = A1 · B1

Add partial products appropriately:

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 P0 = pp0
 Add pp1 and pp2 → use a half adder:
o P1 = pp1 ⊕ pp2
o carry1 = pp1 · pp2
 Add carry1 and pp3 → use another half adder:
o P2 = pp3 ⊕ carry1
o P3 = pp3 · carry1

So final product bits:

P0=A0B0P1=(A1B0)⊕(A0B1)carry1=(A1B0)⋅(A0B1)P2=(A1B1)⊕carry1P3=(A1B1)⋅carry1\begi
n{aligned} P_0 &= A_0B_0 \\ P_1 &= (A_1B_0) \oplus (A_0B_1) \\ \text{carry}_1 &=
(A_1B_0)\cdot(A_0B_1) \\ P_2 &= (A_1B_1) \oplus \text{carry}_1 \\ P_3 &=
(A_1B_1)\cdot\text{carry}_1 \end{aligned}P0P1carry1P2P3=A0B0=(A1B0)⊕(A0B1)=(A1B0
)⋅(A0B1)=(A1B1)⊕carry1=(A1B1)⋅carry1

(This is a minimal combinational realization using 4 two-input ANDs, 2 XORs and 3 ANDs if you
implement XOR as gates — note half-adder reuse reduces explicit gate count.)

Truth Table (complete)

Inputs A1 A0 × B1 B0 (16 combinations) — product (decimal shown for clarity)

A1 A0 B1 B0 Product (binary P3 P2 P1 P0) Decimal

00 00 0000 0
00 01 0000 0
00 10 0000 0
00 11 0000 0
01 00 0000 0
01 01 0001 1
01 10 0010 2
01 11 0011 3
10 00 0000 0
10 01 0010 2
10 10 0100 4
10 11 0110 6
11 00 0000 0
11 01 0011 3
11 10 0110 6

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A1 A0 B1 B0 Product (binary P3 P2 P1 P0) Decimal

11 11 1001 9

(You can fill this table in the lab by observing P3..P0 for each input combination.)

Logic Diagram (block / gate level)

Block-level (recommended)
1. Generate partial products with four 2-input AND gates:
o pp0 = A0 & B0 → P0
o pp1 = A1 & B0
o pp2 = A0 & B1
o pp3 = A1 & B1
2. Use a Half-Adder (HA1) to add pp1 and pp2:
o HA1: inputs pp1, pp2 → SUM1 (=P1), C1 (=carry1)
3. Use a Second Half-Adder (HA2) to add pp3 and C1:
o HA2: inputs pp3, C1 → SUM2 (=P2), C2 (=P3)

(Use HA implementation: SUM = XOR(inputs), C = AND(inputs).)

Gate-level (explicit)
 4 × 2-input ANDs: produce pp0..pp3
 1 × XOR for P1 (pp1 ⊕ pp2)
 1 × AND for carry1 (pp1 & pp2)
 1 × XOR for P2 (pp3 ⊕ carry1)
 1 × AND for P3 (pp3 & carry1)

Total recommended components (using basic gates):

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 AND gates: 4 (partial products) + 2 (for carry generation if you use half-adder formulas) but
counted above → effectively 5–6 depending on XOR internal gates
 XOR gates: 2
 AND gates for carry: 2 (carry1 and P3)

If using two half-adders (each = 1 XOR + 1 AND), the required gates are:

 4 ANDs (pp0..pp3) + 2 XORs (HA1, HA2) + 2 ANDs (HA1 carry and HA2 carry output
used as P3) → total 8 basic gates (counting 2-input AND/XOR only). Many ICs combine
gates per chip so one 7408 + one 7486 suffice.

ICs & Pin suggestions (practical)

Recommended ICs (standard 14-pin TTL):

 7408 — Quad 2-input AND (use for partial products and carries)
o Vcc = pin 14, GND = pin 7; gate1: inputs pin1, pin2 → out pin3; gate2: pins4,5→6;
gate3: pins9,10→8; gate4: 11,12→13.
 7486 — Quad 2-input XOR (use for half-adders)
o Vcc = pin 14, GND = pin 7; gate1: inputs pin1,2 → out pin3; gate2: pins4,5→6;
gate3: pins9,10→8; gate4: pins11,12→13.
 7404 — Hex inverter if you need inversions (not required for this design).
 LEDs + 330 Ω resistors for P0..P3.

Circuit wiring (practical step-by-step)

A. Wiring the components on breadboard
1. Place the 7408 and 7486 ICs on the breadboard. Connect their Vcc pins to +5V and GND
pins to 0V. Add a 0.1 µF decoupling capacitor near the ICs.
2. Connect input switches/jumpers for A1, A0, B1, B0. Tie unused inputs to GND when not
used.
3. Partial products:
o AND gate 1: A0 (pin) & B0 → output = P0 (connect to LED through 330 Ω to
GND).
o AND gate 2: A1 & B0 → output = pp1.
o AND gate 3: A0 & B1 → output = pp2.
o AND gate 4: A1 & B1 → output = pp3.
4. Half-Adder 1 (HA1):
o XOR gate: inputs pp1, pp2 → SUM1 → connect to LED P1 (through resistor).
o AND gate: inputs pp1, pp2 → carry1 (C1).
5. Half-Adder 2 (HA2):
o XOR gate: inputs pp3, C1 → SUM2 → connect to LED P2.

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o AND gate: inputs pp3, C1 → carry2 → connect to LED P3 (MSB).

6. Check all wiring, then power ON. Test all 16 combinations of A1A0 × B1B0 and record
outputs.

B. Example wiring mapping (logical — not pin-to-pin)

 A0 → 7408 input gate1a
 B0 → 7408 input gate1b → gate1 out = P0 LED
 A1/B0 → 7408 gate2 → out = pp1 → to 7486 input1 and 7408 carry gate
 A0/B1 → 7408 gate3 → out = pp2 → to 7486 input1 and 7408 carry gate
 A1/B1 → 7408 gate4 → out = pp3 → to 7486 input and carry gate

(If you want an exact pin-to-pin table for the two ICs you have, say which package labels you have
and I will provide exact pin numbers.)

Truth-table verification / Observation table

Use this table while testing. Fill P3..P0 observed for each input combination.

A1 A0 B1 B0 Expected Dec Expected P3P2P1P0 Observed P3P2P1P0 Remarks

00 00 0 0000
00 01 0 0000
00 10 0 0000
00 11 0 0000
01 00 0 0000
01 01 1 0001
01 10 2 0010
01 11 3 0011
10 00 0 0000
10 01 2 0010
10 10 4 0100
10 11 6 0110
11 00 0 0000
11 01 3 0011
11 10 6 0110
11 11 9 1001

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Gate count & chip use (summary)

Using two half-adders + four ANDs:

 ANDs (partial products): 4 (one per pp) → use 7408 (has 4 ANDs)
 Half adders: each HA = 1 XOR + 1 AND → HA1 uses one 7486 XOR + one 7408 AND
(carry); HA2 uses another 7486 XOR + 7408 AND (carry).
 Total logical gates used (2-input): AND = 6 (4 pp + 2 carries), XOR = 2. That fits in one
7408 and one 7486 (7408 has 4 ANDs — you need 6 ANDs so use one 7408 + one
additional AND from another 7408 or reuse spare gates across ICs or use NAND to
implement extra ANDs). Practical arrangement: use two 7408 ICs (8 ANDs total) plus one
7486 (4 XORs).

Procedure (step-by-step — lab)

1. Read and understand the circuit. Gather ICs and components. Place ICs on the breadboard.
2. Wire Vcc and GND to all ICs (+5 V to pin 14, GND to pin 7 for standard 14-pin TTL). Add
0.1 µF decoupling near each IC.
3. Wire the inputs A1, A0, B1, B0 to switches; tie unused inputs to GND.
4. Form partial products with AND gates as above. Connect pp0 to P0 LED.
5. Build HA1: XOR(pp1,pp2) → P1; AND(pp1,pp2) → C1.
6. Build HA2: XOR(pp3,C1) → P2; AND(pp3,C1) → P3.
7. Power on. Step through all 16 input combinations and fill the observation table. Verify
results match expected product.
8. Turn off power and tidy up wiring.

Result
 The 2-bit × 2-bit multiplier was successfully implemented. Observed outputs matched the
theoretical product for all input combinations (fill in your observation table entries).

Conclusion
A 2-bit by 2-bit combinational multiplier can be implemented with simple AND gates and half-
adders. The design uses 4 partial products then adds them using two half-adders to form the 4-bit
product. The circuit is small and suitable for learning bitwise multiplication and combinational
design.

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Digital Electronics

Experiment No: 10 Design and implement a 2-bit comparator. Page 1/4

AIM: Design and implement a 2-bit comparator.

Components / Apparatus
Sr.
Component / IC Example part Qty
No.
7486 (XOR) + 7404 (inverter) or
1 XOR/XNOR (for equality) 1
74266/4077 (XNOR)
2 AND gate 7408 (quad 2-input AND) 1
3 OR gate 7432 (quad 2-input OR) 1
4 NOT gate 7404 (hex inverter) — if needed 1
Breadboard, +5V supply, wires, LEDs, 330Ω
5 — —
resistors, switches
6 Decoupling capacitor 0.1 µF — 1

If you have a 7486 (XOR) but not XNOR, use XOR + inverter to form XNOR: XNOR(A,B) =
NOT( XOR(A,B) ).

Theory & Truth Table

Complete truth table (16 rows):

A1 A0 B1 B0 A>B A=B A<B

0 0 0 0 0 1 0
0 0 0 1 0 0 1
0 0 1 0 0 0 1
0 0 1 1 0 0 1
0 1 0 0 1 0 0
0 1 0 1 0 1 0
0 1 1 0 0 0 1
0 1 1 1 0 0 1
1 0 0 0 1 0 0

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A1 A0 B1 B0 A>B A=B A<B

1 0 0 1 1 0 0
1 0 1 0 0 1 0
1 0 1 1 0 0 1
1 1 0 0 1 0 0
1 1 0 1 1 0 0
1 1 1 0 1 0 0
1 1 1 1 0 1 0

Minimal Boolean Expressions (derived using logic

reasoning / K-map)
Equality (A = B)
E=Eq=(A1⊙B1)⋅(A0⊙B0)E = Eq = (A_1 \odot B_1)\cdot(A_0 \odot B_0)E=Eq=(A1⊙B1)⋅(A0
⊙B0)

(XNOR each bit, then AND them.)

Greater (A > B)
A is greater than B when either:

 MSB of A is 1 and MSB of B is 0 → A1B1ˉA_1\bar{B_1}A1B1ˉ, OR

 MSBs equal, and LSB of A is 1 and LSB of B is 0 → (A1⊙B1)⋅A0B0ˉ(A_1 \odot
B_1)\cdot A_0\bar{B_0}(A1⊙B1)⋅A0B0ˉ

So:

G=A>B=A1B1‾ + (A1⊙B1) A0B0‾G = A>B = A_1\overline{B_1} \;+\; (A_1\odot

B_1)\,A_0\overline{B_0}G=A>B=A1B1+(A1⊙B1)A0B0
Less (A < B)
Symmetrically:

L=A<B=A1‾B1 + (A1⊙B1) A0‾B0L = A<B = \overline{A_1}B_1 \;+\; (A_1\odot

B_1)\,\overline{A_0}B_0L=A<B=A1B1+(A1⊙B1)A0B0

These expressions are minimal and implement the usual hierarchical (MSB-first) comparator.

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Logic / Gate-level Implementation (recommended)

Use the following building blocks:

 Two XNOR gates (or XOR+NOT) to form E1E_1E1 and E0E_0E0.

 One AND to form Eq=E1⋅E0Eq = E_1 \cdot E_0Eq=E1⋅E0 → this is EEE.
 For G:
o AND1: A1A_1A1 AND B1‾\overline{B_1}B1
o AND2: A0A_0A0 AND B0‾\overline{B_0}B0
o AND3: E1E_1E1 AND AND2 (i.e. E1⋅A0B0ˉE_1\cdot A_0\bar{B_0}E1⋅A0B0ˉ)
o OR: AND1 OR AND3 → G
 For L: symmetric (swap A/B)

Block diagram (text)

Gate count (using 2-input primitives)

 XNOR (or XOR+NOT): 2 XNORs (or 2 XOR + 2 NOT)
 Eq: 1 AND
 NOTs: 2 (for B1', B0') and 2 (for A1', A0') if building L path separately (but you can reuse
inverters) — clever wiring reuses complements.
 ANDs: term1 (A1·B1'), term2base (A0·B0'), term2 (E1·term2base), similarly for L: A1'·B1,
B0·A0', E1·(B0·A0') → many ANDs but some shareable.
 ORs: 2 (one for G, one for L)

Total physical gates depends on available multi-input gates / XNOR availability. With standard
chips: one 74266 (XNOR quad) or 7486+7404 simplifies equality.

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Suggested ICs & mapping (practical)

Function Preferred IC Notes

74266 or 4077 (2-input XNOR) or use 74266 is quad XNOR variants; 4077 is CMOS
XNOR
7486 + 7404 XNOR/XNOR
7486 (if you want to make XNOR by
XOR XNOR = NOT(XOR)
inverting XOR)
AND 7408 Quad 2-input AND
OR 7432 2-input OR gates
NOT 7404 Hex inverter (if needed)

Example chip arrangement (one possible):

 1 × 74266 (or 4077) for E1 & E0 XNORs

 1 × 7408 for the ANDs (Eq, term1, term2base, term2, and L-path ANDs; you may need 2 ×
7408 depending on reuse)
 1 × 7432 for ORs
 7404 for inverters if XNOR not available

Procedure (breadboard implementation)

1. Power & setup: Place ICs on breadboard. Connect Vcc (+5 V) to pin 14 and GND to pin 7
for standard 14-pin TTLs. Add 0.1 μF decoupling near ICs.
2. Inputs: Connect four switches for A1, A0, B1, B0. Use pull-down resistors or make
switches that connect to +5V when ON and to GND when OFF. Do not leave inputs
floating.
3. Equality (E):
o Wire XNOR gate for E1 = XNOR(A1,B1).
o Wire XNOR for E0 = XNOR(A0,B0).
o Wire AND of E1 & E0 → LED_E through 330 Ω to GND (or active-high LED).
4. Greater (G):
o Invert B1 and B0 (use 7404) → B1', B0'.
o AND1 = A1 & B1' → feed to OR.
o AND2 = A0 & B0' → feed AND with E1 → AND3 = E1 & AND2.
o OR(AND1,AND3) → LED_G.
5. Less (L):
o Similarly invert A1, A0 to get A1', A0'.
o AND1_L = A1' & B1 → AND2_L = B0 & A0' → AND3_L = E1 & AND2_L
o OR(AND1_L,AND3_L) → LED_L.
6. Test: Apply all 16 combinations of A and B. For each combination, record LED states and
verify with truth table.

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 SHRI SWAMI SAMARTH COLLEGE OF ENGINEERING, MALWADI ,BOTA.
DEPARTMENT OF ELECTRONIC’S ENGINEERING

Observation Table (to fill during experiment)

A1 A0 B1 B0 Expected G Expected E Expected L Observed G Observed E Observed L

00 00 0 1 0
00 01 0 0 1
... ... ... ... ...
11 11 0 1 0

(Complete for all 16 rows.)

Result
On implementing the circuit and testing all input combinations, the LEDs for A>BA>BA>B,
A=BA=BA=B, and A<BA<BA<B should match the expected outputs from the truth table. This
verifies the 2-bit comparator functionality.

Conclusion & Remarks

 The hierarchical comparator approach (compare MSBs first; if equal, compare LSBs) yields
compact, readable logic.
 Using XNOR gates for bit equality drastically reduces logic and wiring: equality becomes a
single AND of two XNOR outputs.
 Gate/IC reuse: compute complements (A1',B1', etc.) once and reuse across G and L logic to
reduce chips.
 If you need to implement a multi-bit comparator (n-bit), the design naturally scales: chain
MSB comparison and use propagate/equal signals to decide lower bits.
 For compactness, dedicated magnitude comparator ICs (e.g., 7485 series) implement n-bit
comparators directly — useful for larger bit widths.

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