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NPTEL » Analog Ic Design
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Week 1
Week 2
Week 3
Week 4
Week 5
Week 6
Feedforward compensated opamp; typical opamp data
sheet
Opamp offset and CMRR; Transimpedance amplifier
using an opamp
Components available in a CMOS process
Assignment-6 solutions
Week 6 Feedback Form : Analog Ic Design
Quiz: Week 6 : Assignment 6
Week 7
Week 8
Week 9
Week 10
Week 11
Week 12
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Problem Solving Session - Jan 2025
Week 6 :
Assignment 6
The due date for submitting this assignment has
passed.
Due on 2025-03-05, 23:59 IST.
Assignment submitted on
2025-03-05, 23:39 IST
Figure 1 for Problems 1-3: Opamps can have non-
idealities in the form of input bias currents as well as input
offset current and input offset voltage. In the non-inverting
amplifier of Fig. 1, let R1 = 10 Ω, R2 =10 kΩ, and vS =0. The
output v O is monitored with a voltmeter and is found to be
0.480 V. Inserting a 1 MΩ resistor in series with the non-
inverting input pin gives vO = 0.780 V. Inserting the 1 MΩ
resistor in series with the inverting input pin gives vO =
0.230 V.
1) Determine the magnitude of the input bias current of
the opamp in pA.
290
Yes, the answer is correct.
Score: 1
Accepted Answers:
(Type: Range) 260,290
1 point
2) Determine the magnitude of the input offset current of
the opamp in pA.
50
Yes, the answer is correct.
Score: 1
Accepted Answers:
(Type: Range) 40,60
1 point
3) Determine the magnitude of the input offset voltage of
the opamp in μV.
480
Yes, the answer is correct.
Score: 1
Accepted Answers:
(Type: Range) 460,500
1 point
Figure 2 for Problems 4-10: An engineer tries to use three
identical CMOS inverters to implement a quick 3-stage
opamp in inverting amplifier configuration, as shown in Fig.
2. Each inverter has gm = 10 mA/V, ro = 2 kΩ, and an
equivalent capacitance Co = 10pF between its output node
and ground (due to transistor parasitic capacitance).
Assume R2 = 2R1 = 20 kΩ.
4) What is the magnitude of the DC (low-frequency) gain
of the opamp in V/V?
8000
Yes, the answer is correct.
Score: 1
Accepted Answers:
(Type: Range) 7500,8000
1 point
5) What is the phase margin of the closed loop amplifier
in degrees?
-80
Yes, the answer is correct.
Score: 1
Accepted Answers:
(Type: Range) -85,-70
1 point
A capacitance C is now connected between the output
node of I 1 and ground to stabilize the circuit.
6) Determine the value of C in nF that results in a phase
margin of 70° for the loop gain. You may assume that the
phase from the dominant pole at the unity-gain frequency
is -90°.
151
No, the answer is incorrect.
Score: 0
Accepted Answers:
(Type: Range) 120,145
1 point
7) Determine the position of the dominant pole of the
loop gain transfer function in Hz.
526
No, the answer is incorrect.
Score: 0
Accepted Answers:
(Type: Range) 550,650
1 point
8) Determine the position of the first non-dominant pole
of the loop gain transfer function in MHz.
Yes, the answer is correct.
Score: 1
Accepted Answers:
(Type: Range) 7.5,8.5
1 point
9) Determine the position of the second non-dominant
pole of the loop gain transfer function in MHz.
Yes, the answer is correct.
Score: 1
Accepted Answers:
(Type: Range) 8,9
1 point
10) Determine the value of the closed loop bandwidth in
MHz.
1.41
Yes, the answer is correct.
Score: 1
Accepted Answers:
(Type: Range) 0.9,2.5
1 point