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MODULE-5
ACCESSING I/O DEVICES
A simple arrangement to connect I/O devices to a computer is to use a single bus structure. It
consists of three sets of lines to carry
• Address
• Data
• Control Signals.
When the processor places a particular address on address lines, the devices that recognize this
address responds to the command issued on the control lines.
The processor request either a read or write operation and the requested data are transferred over
the data lines.
When I/O devices & memory share the same address space, the arrangement is called memory
mapped I/O.

Eg:-
Move DATAIN, Ro - Reads the data from DATAIN then into processor register Ro. Move Ro,
DATAOUT - Send the contents of register Ro to location DATAOUT. DATAIN - Input buffer
associated with keyboard.
DATAOUT - Output data buffer of a display unit / printer.

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Address Decoder: It enables the device to recognize its address when the address appears on
address lines.
Data register - It holds the data being transferred to or from the processor.
Status register - It contains information relevant to the operation of the I/O devices.

• The address decoder, data & status registers and the control circuitry required to co-
ordinate I/O transfers constitute the device’s I/O interface circuit.
• For an input device, SIN status flag is used SIN = 1, when a character is entered at the
keyboard, SIN = 0, once the char is read by processor.
• For an output device, SOUT status flag is used.
• Eg: Registers used in the data transfer operations

DIRQ - Interrupt Request for display.

KIRQ - Interrupt Request for keyboard.
KEN - Keyboard enable.
DEN - Display Enable.
SIN, SOUT - Status flags.
The data from the keyboard are made available in the DATAIN register & the data sent to the
display are stored in DATAOUT register.

PROGRAM

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EXPLANATION:
• This program, reads a line of characters from the keyboard & stores it in a memory buffer
starting at locations LINE.
• Then it calls the subroutine “PROCESS” to process the input line. As each character is
read, it is echoed back to the display.
• Register Ro is used as a pointer to memory buffer area. The contents of R0 are updated
using Auto – increment mode so that successive characters are stored in successive memory
location.
• Each character is checked to see if there is carriage return (CR), char, which has the ASCII
code 0D (hex).
• If it is, a line feed character (ASCII character 0A) is sent to move the cursor one line down
on the display & subroutine PROCESS is called. Otherwise, the program loops back to
wait for another character from the keyboard.
Different modes of Data transfer
1) Programmed I/O
• Data is exchanged between processor and input output module
• When processors is executing a program and encounter an instruction relating to
input-output, it executes that instruction by using a command to that appropriate I/O module.
Then the I/O module will perform the requested action and set the appropriate bit in the I/O
status register.
• I/O command issued by the processor to the I/O modules are
1. Test
2. Control

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3. Read
4. Write

2) Memory mapped I/O

• There is a single address space for a memory location and the I/O device
• Here a single read command or write command along with the I/O commands are needed on
the bus
• These command lines specifies whether the address refer to the memory location or I/O
device
• Most CPU uses memory mapped I/O
• Always CPU assigns some address from its address space to the memory and the rest of its
space assign to I/O devices
3) Interrupt driven I/O
• Here the program issues an I/O command and then execute it until it is interrupted by I/O
hardware to signal the end of the operation. Example:-printer
• Here the program enters a wait loop in which it repeatedly checks the performing
device’s status. During this process, the processor is not performing any useful computation.
• This situation can be overcomed by sending an alert message to the processor when it
becomes ready
• It is done by sending a hardware signal called interrupt. The routine executed in response
to an interrupt request is called interrupt service routine(ISR)
• The processor first completes execution of instruction then it loads the PC with address of
first instruction of ISR
4) Direct Memory Access
• In this method, the I/O devices read or write information from the main memory without
interference from the CPU through the system bus

INTERRUPTS
• When a program enters a wait loop, it will repeatedly check the device status. During this
period, the processor will not perform any function. There are many situations where other
tasks can be performed while waiting for an I/O device to become ready. To allow this to
happen, we can arrange for the I/O device to alert the processor when it becomes ready.
• It can do so by sending a hardware signal called an interrupt to the processor. At least one
of the bus control lines called an interrupt request line is usually dedicated for this
purpose.
• Since the processor is no longer required to continuously check the status of external
devices, it can use the waiting period to perform other useful functions. Indeed by using
interrupts such waiting periods can ideally be eliminated.
• The routine executed in response to an interrupt request is called Interrupt Service
Routine.

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• Assume that an interrupt requests arrives during the execution of instruction i.

• The processor first completes the execution of instruction i. Then it loads the PC (Program
Counter) with the address of the first instruction of the ISR.
• After the execution of ISR, the processor has to come back to instruction i + 1.
• Therefore, when an interrupt occurs, the current contents of PC which point to i+1 is put
in temporary storage in a known location.
• A return from interrupt instruction at the end of ISR reloads the PC from that temporary
storage location, causing the execution to resume at instruction i+1.
• When the processor is handling the interrupts, it must inform the device that its request has
been recognized so that it remove its interrupt requests signal.
• This may be accomplished by a special control signal called the interrupt acknowledge
signal.
• The task of saving and restoring the information can be done automatically by the
processor.
• The processor saves only the contents of program counter & status register ie; it saves only
the minimal amount of information to maintain the integrity of the program execution.
• Saving registers also increases the delay between the time an interrupt request is received
and the start of the execution of the ISR. This delay is called the Interrupt Latency.
• Generally, the long interrupt latency in unacceptable.

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• The concept of interrupts is used in Operating System and in Control Applications, like
real-time processing.

• A single interrupt request line may be used to serve n devices. All devices are connected
to the line via switches to ground.
• To request an interrupt, a device closes its associated switch, the voltage on INTR line
drops to 0(zero).
• If all the interrupt request signals (INTR1 to INTRn) are inactive, all switches are open
and the voltage on INTR line is equal to Vdd..
• When a device requests an interrupt by closing its switch, the voltage on the line drops to
0, causing INTR request signal received by the processor to go to 1.
• Since closing one or more switches will cause line voltage to drop to 0, the value of INTR
is the logical OR of the requests from individual devices. ie;
INTR = INTR1+… +INTRn
INTR - It is used to name the INTR signal on common line it is active in the low voltage state. In
figure special gates called,
• Open collector (bipolar ckt) or Open drain (MOS circuits) is used to drive INTR line.
The Output of the Open collector (or) Open drain control is equal to a switch to the ground
that is open when gates input is in “0” state and closed when the gates input is in “1”state.
• Resistor “R” is called a pull-up resistor because it pulls the line voltage upto the high
voltage state when the switches are open.

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DIRECT MEMORY ACCESS (DMA)

A special control unit may be provided to allow the transfer of large block of data at high speed
directly between the external device and main memory, without continuous Intervention by the
processor. This approach is called DMA.
DMA transfers are performed by a control circuit called the DMA Controller.
DMA controller is controlled by the processor with the help of a program to perform the DMA
operations.
1. To initiate the transfer of a block of words, processor sends a starting address, number of words
in the blocks and the direction of the transfer.
2. The DMA controller proceeds to perform the requested operation with the help of above
Information
3. When the entire block has transferred, the controller informs the processor by raising an interrupt
signal.
4. While DMA transfer is taking place, the program that requested the transfer cannot continue,
and the processor can be used to execute another program
5. After the DMA transfer is completed, the processor can return to the program that requested the
transfer.
6. OS is responsible for suspending the execution of one program and starting another.
Thus, for an I/O operation involving DMA, the OS puts the program that requested the transfer in
the blocked state, initiates the DMA operation and starts the execution of another
7. When transfer is completed, DMA controller informs the processor by sending an interrupt
request
8. In response, OS puts the suspended program in the Runnable state so that it can be selected by
the scheduler to continue execution.

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It is part of I/O device interface. To initiate the transfer of a block of words, the processor sends,
[Link] address
[Link] of words in the block
[Link] of transfer.
✓ When a block of data is transferred, the DMA controller increment the memory address for
successive words and keep track of number of words and it also informs the processor by
raising an interrupt signal.
✓ While DMA control is taking place, the program requested the transfer cannot continue
and the processor can be used to execute another program.
✓ After DMA transfer is completed, the processor returns to the program that requested the
transfer.
R/W-Determines the direction of transfer
When
R/W =1, DMA controller read data from memory to I/O device.
R/W =0, DMA controller perform write operation.
Done Flag=1, the controller has completed transferring a block of data and is ready to receive
another command.
IE=1, it causes the controller to raise an interrupt (interrupt Enabled) after it has completed
transferring the block of data.
IRQ=1, it indicates that the controller has requested an interrupt.

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• DMA controller connects a high speed network to the computer bus .

• The disk controller which controls two disks, also has DMA capability and it provides two DMA
channels.
• To start a DMA transfer of a block of data from main memory to one of the disks, the program
writes the address and the word count information into the registers of the corresponding channel
of the disk controller.
• When DMA transfer is completed, it will be recorded in status and control registers of the DMA
channel (ie) Done bit=IRQ=IE=1.
➢ Cycle Stealing:
• Requests by DMA devices for using the bus are having higher priority than processor
requests
• Top priority is given to high speed peripherals such as Disk, High speed Network Interface
and Graphics display device.
• Since the processor originates most memory access cycles, the DMA controller can be said
to steal the memory cycles from the processor.
• This interviewing technique is called Cycle stealing.

➢ Burst Mode:
The DMA controller may be given exclusive access to the main memory to transfer a block of
data without interruption. This is known as Burst/Block Mode
Bus Master:

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The device that is allowed to initiate data transfers on the bus at any given time is called the bus
master.
Bus Arbitration:
It is the process by which the next device to become the bus master is selected and the bus
mastership is transferred to it.
Types:
There are 2 approaches to bus arbitration. They are,
Centralized arbitration (A single bus arbiter performs arbitration)
Distributed arbitration (all devices participate in the selection of next bus master).

Centralized Arbitration:
• Here the processor is the bus master and it may grants bus mastership to one of its DMA
controller.
• A DMA controller indicates that it needs to become the bus master by activating the Bus
Request line (BR) which is an open drain line.
• The signal on BR is the logical OR of the bus request from all devices connected to it.
• When BR is activated, the processor activates the Bus Grant Signal (BGI) and indicated
the DMA controller that they may use the bus when it becomes free.
• This signal is connected to all devices using a daisy chain arrangement.
• If DMA requests the bus, it blocks the propagation of Grant Signal to other devices and it
indicates to all devices that it is using the bus by activating open collector line, Bus Busy
(BBSY).
• Hence after receiving the Bus-grant signal, a DMA controller waits for Bus-Busy to
become inactive, and then assumes mastership of the bus. At this time, it activates Bus-
Busy to prevent other devices from using the bus at the same time.
➢ The timing diagram shows the sequence of events for the devices connected to the
processor is shown.
➢ DMA controller 2 requests and acquires bus mastership and later releases the bus.
During its tenure as bus master, it may perform one or more data transfer.
➢ After it releases the bus, the processor resources bus mastership

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Fig: below shows Sequence of signals during transfer of bus mastership for the devices

Distributed Arbitration:
It means that all devices waiting to use the bus have equal responsibility in carrying out the
arbitration process without using a central arbiter.
• Each device on the bus is assigned a 4 bit id.
• When one or more devices request the bus, they assert the Start-Arbitration signal & place
their 4 bit ID number on four open collector lines, ARB0 to ARB3.
• A winner is selected as a result of the interaction among the signals transmitted over these
lines.
• The net outcome is that the code on the four lines represents the request that has the highest
ID number.

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• The drivers are of open collector type. Hence, if the input to one driver is equal to 1, the
input to another driver connected to the same bus line is equal to 0, then bus will be in low-
voltage state.

Example
• Assume two devices A & B have their ID 5 (0101), 6(0110). They are requesting the use
of bus.
• Device A transmits the pattern 0101 and B transmits 0110. The code seen by both devices
is 0111.
• Each devices compares the pattern on the arbitration line to its own ID starting from MSB.
• If it detects a difference at any bit position, it disables the drivers at that bit position and
for all lower order bits.
• It does this by placing 0 at the input of these drivers.
• In our example. A detects a difference in line ARB1, hence it disables the drivers on lines
ARB1 & ARB0.
• This causes the pattern on the arbitration line to change to 0110 which means that B has
won the contention.
• Note that since the code on the priority line is 0111 for a shorter period, device B may be
temporarily disable its driver on line ARB0. However, it will enable this driver once it sees
a 0 on line ARB1 resulting from the action by device A.
Advantages:
• Highly reliable – because operation of the bus is not dependent on any single device.

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MEMORY

MEMORY SYSTEM
1) BASIC CONCEPTS
The maximum size of the memory that can be used in any computer is determined by the
addressing scheme.
Examples of Address Memory Locations are: -
1) 16 Bit computer ->2^16= 64 K memory locations are available
2) 32 Bit computer -> 2^32 = 4G (Giga) memory locations
3) 40 Bit computer->2^40= 1 T (Tera) memory locations
Most modern computers are byte addressable. The big endian arrangement is used in the 68000
processors. The little endian arrangement is used in Intel processors. ARM architecture can be
configured to use either arrangements.
Memory is designed to store and retrieve data in word-length. Consider a byte-addressable
computer whose instructions generate 32-bit addresses. When a 32-bit address is sent from
processor to the memory unit, high order 30 bits determine which word will be accessed, lower
order 2 bits of address specify which byte location is involved.
In a read operation, other bytes may be fetched from the memory, but they are ignored by
the processor. In write operation, the control circuitry of the memory must ensure that the
contents of other bytes of the same word are not changed.
Figure: - connection of the memory to the processor

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• If MAR is k bits long and MDR is n bits long, then the memory may contain upto 2K
addressable locations and the n-bits of data are transferred between the memory and
processor.
• This transfer takes place over the processor bus.
• The processor bus has,
➢ Address Line
➢ Data Line
➢ Control Line (R/W, MFC – Memory Function Completed)
• The control line is used for co-ordinating data transfer.
• The processor reads the data from the memory by loading the address of the required
memory location into MAR and setting the R/ W line to 1.
• The memory responds by placing the data from the addressed location onto the data lines
and confirms this action by asserting MFC signal.
• Upon receipt of MFC signal, the processor loads the data onto the data lines into MDR
register.
• The processor writes the data into the memory location by loading the address of this
location into MAR and loading the data into MDR sets the R/W line to 0.
Memory Access Time → It is the time that elapses between the initiation of an operation and
completion of that operation
Memory Cycle Time → It is the minimum time delay that required between the
Initiation of the two successive memory operations.

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1.1) RAM (Random Access Memory):

In RAM, if any location that can be accessed for a Read/Write operation in fixed amount
of time, it is independent of the location’s address.
Cache Memory:
It holds the currently active segments of a program and their data.
Virtual memory:
✓ It is a small, fast memory that is inserted between the larger slower main memory and the
processor.
✓ The address generated by the processor does not directly specify the physical locations in
the memory.
✓ The address generated by the processor is referred to as a virtual / logical address.
✓ The virtual address space is mapped onto the physical memory where data are actually
stored.
✓ The mapping function is implemented by a special memory control circuit is often called
the memory management unit.
✓ Only the active portion of the address space is mapped into locations in the physical
memory.
✓ The remaining virtual addresses are mapped onto the bulk storage devices used, which are
usually magnetic disk.
✓ As the active portion of the virtual address space changes during program execution, the
memory management unit changes the mapping function and transfers the data between
disk and memory.
✓ Thus, during every memory cycle, an address processing mechanism determines whether
the addressed in function is in the physical memory unit.
✓ If it is, then the proper word is accessed and execution proceeds.
✓ If it is not, a page of words containing the desired word is transferred from disk to memory.
✓ This page displaces some page in the memory that is currently inactive.

2) SEMI CONDUCTOR RAM MEMORIES:

Semi-Conductor memories are available is a wide range of speeds.
Their cycle time ranges from 100ns to 10ns
2.1) INTERNAL ORGANIZATION OF MEMORY CHIPS:
➢ Memory cells are usually organized in the form of array, in which each cell is capable of
storing one bit of information.

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➢ Each row of cells constitutes a memory word and all cells of a row are connected to a
common line called as word line.
➢ The cells in each column are connected to Sense / Write circuit by two bit lines.
➢ The Sense / Write circuits are connected to data input or output lines of the chip.
➢ During a Read operation, these circuits sense, or read the information stored in the cells
selected by a word line and transmit this information to the output data lines.
➢ During a write operation, the sense / write circuit receive input information and store it in
the cells of the selected word.
➢ The data input and data output of each senses / write circuit are connected to a single
bidirectional data line that can be connected to a data bus of the computer
• Two control lines are used: -.
R / W →Specifies the required operation.
CS →Chip Select input selects a given chip in the multi-chip memory system
In below example, we have very small memory chip consisting of 16 words of 8 bits each. This is
referred to as a 16*8 organization

Fig: Organization of bit cells in a memory chip

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Above figure stores 128 bits (16 words*8 bit) and requires 14 external connections for address,
data, and control lines. It also needs two lines for power supply and ground connections.

Consider larger memory circuit, which has 1K (1024) memory cells. This circuit can be organized
as a 128*8 memory, requiring a total of 19 external connections. Alternatively, same number of
cells can be organized into 1K* 1 format. In this this case, 10-bit address is needed, but there is
only one data lines, resulting in 15 external connections.
The below figure shows such an organization.

• Required 10-bit address is divided into 2 groups of 5 bit each to form the row and column
addresses for the cell array.

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• Row address selects a row of 32 cells, all of which are accessed in parallel. But only one
of these cells is connected to the external data lines by the output multiplexer and input
demultiplexer.
• Larger chips have the same organization as above figure, but use a larger memory cell array
and have more external connections
• For example, a 4M bit chip may have a 512K * 8 organization, in which case 19 address
and 8 data input/output pins are needed.
2.2) STATIC MEMORIES:
Memories that consists of circuits capable of retaining their state as long as power is applied are
known as static memory (SRAM).
▪ Two inverters are cross-connected to form a latch.
▪ The latch is connected to 2 bit lines by transistors T1 and T2.
▪ These transistors act as switches that can be opened or closed under control of the word
line.
▪ When the word line is at ground level, the transistors are turned off and the latch retains its
state.
▪ Example: -Assume that the cell is in state 1 if the logic value at point X is 1 and at point Y
is 0. This state is maintained as long as the signal on word line is at ground level.

When the word line is at ground level, the transistors are turned off and the latch retain its state.
Read Operation:
➢ Word line is activated to close switches T1 and T2

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➢ If the cell is in state 1, the signal on bit line b is high and the signal on the bit line b’ is low.
The opposite is true if the cell is in state 0. Thus b and b’ are complement of each other.
➢ Sense / write circuit at the end of the bit lines monitors the state of b and b’ and set the
output accordingly.
Write Operation:
➢ The state of the cell is set by placing appropriate value on bit line b and its compliment on
b’, and then activating the word line. This forces the cell into the corresponding state.
➢ The required signal on the bit lines are generated by Sense / Write circuit.

CMOS CELL (Complementary Metal Oxide Semi-Conductor)

Transistors pairs (T3, T5) and (T4, T6) form the inverters in the latch. The state of the cell is read
or written as just above.
Example: - In state 1, voltage at point X is maintained high by having transistors T3 and T6 on,
while T4 and T5 are off. Thus, if T1 and T2 are turned on (closed), bit lines b and b’ will have
high and low signals respectively.
Power supply voltage, Vsupply is 5V in older CMOS SRAM and 3.3 V in new low-voltage
versions. The continuous power is needed for the cell to retain its state.

If power is interrupted, the cell’s contents will be lost. When power is restored, the latch will settle
into a stable state, but will not be the same state as it was before the interruption. Hence SRAM

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are said to be volatile memories

Advantages of CMOS SRAM
➢ Very low power consumption because current flows in the cell only when the cell is being
accessed.
Advantages of SRAM
Static RAMs can be accessed quickly. It access time is few nanoseconds.
Demerit:
SRAMs are said to be volatile memories because their contents are lost when the power is
interrupted.
2.3) ASYNCHRONOUS DRAMS
Dynamic RAMs (DRAM)
• Static RAMS are fast, but they come in high cost because they use several transistors.
• Less expensive RAMs can be implemented if simpler cells are used. Such cells cannot
retain their state indefinitely. Hence they are called Dynamic RAMs (DRAM).

• The information stored in a dynamic memory cell in the form of a charge on a capacitor
and this charge can be maintained only for tens of Milliseconds.
• The contents must be periodically refreshed by restoring this capacitor charge to its full
value.
• Example of a dynamic memory cell is as follows:

• It consists of capacitor C and a transistor T

• In order to store information in the cell, the transistor T is turned on and the appropriate
voltage is applied to the bit line, which charges the capacitor.

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• After the transistor is turned off, the capacitor begins to discharge, which is caused by the
capacitor’s own leakage resistance and by the fact that the transistor continues to conduct
a tiny amount of current

• Hence the information stored in the cell can be retrieved correctly before the threshold
value of the capacitor drops down.
• During a read operation, the transistor in a selected cell is turned on and a sense amplifier
connected to the bit line detects whether the charge stored on the capacitor is above the
threshold value.
➢ If charge on capacitor > threshold value -> it drives the Bit line to a full voltage that
represent logic value 1. This voltage recharges the capacitor to the full charge that
corresponds to logic value 1
➢ If charge on capacitor < threshold value ->it pulls the Bit line to ground level, which
ensures that the capacitor will have no charge, representing logic value 0.
➢ Reading the contents of the cell automatically refreshes its contents. All cells in a selected
row are read at the same time, which refreshes the contents of the entire row.
16 mega bit DRAM chip, configured as 2M * 8 as follows: -

• Cells are organized in form of a 4K *4K array.

• 4096 cells in each row are divided into 512 groups of 8, so that a row can store 512 bytes
of data.

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• 12 address bits are needed to select a row.

• Another 9 bits are needed to specify a group of 8 bits in the selected row.
• Thus 21-bit address is needed to access a byte in this memory.
• The high-order 12 bits and low-order 9 bits of the address constitute the row and column
addresses.
During read operation, row address is applied first. It is loaded into the row address latch in
response to a signal pulse on the Row Address Strobe(RAS) input of the chip. Then a Read
operation is initiated, in which all cells on the selected row are read and refreshed.
After the Row address is loaded,Column address is applied to the address pins and loaded into
the column address latch under control of column Address Strobe(CAS) signal
• Information in this latch is decoded and appropriate group of 8 sense/write circuits are
selected.
• If R/W control signal indicate a read operation, output values of selected circuits are
transferred to the data lines D7-0.
During write operation, information on D7-0 lines is transferred to selected circuits. This
information is then used to overwrite the contents of selected cells in the corresponding 8 columns.

Note: - Applying a row address causes all cells on the corresponding row to be read and refreshed
during both read and write operations. To ensure that the contents of a DRAM are maintained,
each row of cells must be accessed periodically. A Refresh circuit performs this function
automatically.
➢ DRAMS are used in memory units of computers
➢ Available chip size range from 1M to 256M bits
➢ Eg:- 64 M bit chip may be organized as 16M *4,8M * 8 or 4M * 16

ASYNCHRONOUS DRAMS
Note: - Figure as above
• Timing of memory device is controlled asynchronously.
• A specialised memory controller circuit provides necessary control signals, RAS and CAS
that govern the timing
• Processor takes into account the delay in the response of the memory.
• Such memories are referred to as Asynchronous DRAMS.

FAST PAGE MODE

In above figure, contents of all 4096 cells in selected row are sensed, but only 8 bits are
placed on the data lines D7-0. This byte is selected by the column address bits A8-0. Here,
a latch can be added at the output of the sense amplifier in each column. Row address will
load the latches corresponding to all bits in the selected row. Then, it is only necessary to
apply different column addresses to place the different bytes on data lines.
✓ Transfer of bytes in sequential order is achieved by applying a consecutive
sequence of column address under the control of successive CAS signals. This
scheme allows transferring a block of data at a much faster rate than can be achieved
for transfers involving random addresses.
✓ Block transfer capability is referred to as fast page mode feature
2.4) SYNCHRONOUS DRAM (SDRAM)

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•SDRAM is the DRAM whose operation is directly synchronized with a clock

signal.
• Address and data connections are buffered using registers
• Output of sense amplifier is connected to a latch
• Read operation causes the contents of all cells in the selected row to be loaded into
these latches.
• But if an access is made for refreshing purpose only, it will not change the contents
of these latches, it will just refresh the contents
• Data held in latches that correspond to the selected columns are transferred into the
data output register, thus becoming available on the data output pins
➢ SDRAM have built-in refresh circuitry, a part of which is a refresh counter, which
provides the addresses of the row that are selected for refreshing.
• Each row must be refreshed every 64ms.
• SDRAMS can be used with clock speeds above 100 MHz
➢ SDRAM has different modes of operations which is selected by writing control
information into mode register
• Example, burst operations use block transfer capability
➢ In SDRAM it is not necessary to provide pulses on CAS line to select columns, the
necessary signals are provided using column counter and clock signal

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In following timing diagram,

• Row address is latched under control of RAS signal
• Memory takes 2 or 3 clock cycles to activate the selected row
• Column address is latched under control of CAS signal
• After delay of one clock cycle, the 1st set of data bits is placed on the data lines
• SDRAM automatically increments the column address to access the 3 sets of bits
in selected row, which are placed on the data lines in the next 3 clock cycles.

LATENCY & BANDWIDTH:

Transfer between the memory and the processor involve single words of data or small blocks of
words. The speed and efficiency of these transfers have a large impact on the performance of a
computer system. A good indication of performance is given by two parameters. They are,
➢ Latency

➢ Bandwidth Latency

• Memory latency is used to refer to the amount of time it takes to transfer a word of data
to or from the memory.
• In Reading or writing a single word of data, the latency provides a complete indication of
memory performance.
• For a block transfer, the latency denotes the time it takes to transfer the first word of data.

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• In above timing diagram, the access cycle begins with the assertion of RAS signal.
• 1st word of data is transferred 5 clock cycles later. Thus, latency is 5 clock cycles.
• The remaining 3 words are transferred in consecutive clock cycles.
Since blocks is of variable size, it is useful to define a performance in terms of no: of bits
or bytes that can be transferred in one second.
Bandwidth:
➢ It is defined as the number of bits or bytes that can be transferred in one second.

• Bandwidth mainly depends upon the speed of access to the stored data & on the number of
bits that can be accessed in parallel (no: of wires)
• Thus, bandwidth is the product of rate at which data are transferred (and accessed) and
width of data bus
Double Data Rate SDRAM(DDR-SDRAM):
• The standard SDRAM performs all actions on the rising edge of the clock signal.
• The double data rate SDRAM transfer data on both the edges (loading edge, trailing edge).
➢ Latency is same for SDRAM and DDR-SDRAM.
➢ The Bandwidth of DDR-SDRAM is doubled for long burst transfer.
• To make it possible to access the data at high rate, the cell array is organized into two
banks.
• Each bank can be accessed separately.
• Such interleaving of words allows simultaneous access to two words that are transferred
on successive edge of the clock

2.5) STRUCTURE OF LARGER MEMORY

• Larger memories are formed by connecting many memory chips

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STATIC MEMORY SYSTEMS

• Consider memory consisting of 2M(2,097,152) words of each 32 bits.
• This can be implemented using 512K* 8 static memory chips
• Each column consists of 4 chips, which implement 1 byte.
• Four of these set provide required 2 M * 32 memory
• Each chip has a control input called chip select (CS)
• When CS is 1, it enables the chip to accept data from or to place data on this data lines.
• Only the selected chip places data on the data output line.
• 21 address bits are needed to select 32-bit word in this memory
• High-order 2 bit of address are decoded to determine which of 4 CS control signals should
be activated, and remaining 19 address bit are used to access specific byte locations inside
each chip of selected row
• R/ W inputs of all chips are tied together to provide a common read/write control

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DYNAMIC MEMORY SYSTEMS

• The organisation of larger dynamic memory systems is same as the above static memory
chips
• The physical implementation is done in the form of Memory Modules.
• Personal computer have atleast 32 M bytes of memory.
• Work stations have atleast 128 M bytes of memory
• Larger memory leads to better performance because more data and programs can be held
in memory rather than in secondary storage.
• If a large memory is built by placing DRAM chips directly on the main system printed
circuit board that contains the processor (Motherboard), it will occupy large amount of
space on the board.
• These packaging consideration have led to the development of larger memory units
known as SIMM’s & DIMM’s .
1. SIMM-Single Inline Memory Module
2. DIMM-Dual Inline Memory Module
➢ Such modules is an assembly of several memory chips on a separate small board that plugs
vertically into a socket on the motherboard.
➢ SIMMs and DIMMs of different sizes are designed to use the same size socket.
➢ To reduce the number of pins, the dynamic memory chips use multiplexed address inputs
✓ For eg:-
✓ 4 M *32, 16 M * 32 and 32M* 32 bit DIMMS all use the same 100 pin socket

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✓ Similarly, 8M*64, 16M*64, 32M*72 DIMMs use 168 pin socket

✓ Such modules occupy a smaller amount of space on a mother board and they allow easy
expansion by replacement if a larger module uses the same socket as the smaller one.
NOTE: - FOR DETAIL STUDY
✓ A SIMM (Single In-Line Memory Module) has a single line of connectors. Connectors
on each side of the Board are the same. SIMMs are now obsolete.
✓ A DIMM (Dual In-Line Memory Module) has 2 lines of connectors. Connectors on
each side of the board are not connected. The most popular types of DIMM are DDR,
DDR2 and DDR3

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MEMORY SYSTEM CONSIDERATIONS

The choice of a RAM chip for a given application depends on several factors: Cost, speed, power,
size etc. SRAMs are faster, more expensive and smaller. In the case of DRAMs are slower, cheaper
and larger.
If speed is the primary requirement static RAMS are the most appropriate one. Static RAMs are
mostly used in cache memories. If cost is the prioritized factor then we are going for dynamic
RAMs. Dynamic RAMs are used for implementing computer main memories.
Memory Controller

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To reduce the number of pins, the dynamic memory chips use multiplexed address inputs.
The address is divided into two parts. They are,
➢ High Order Address Bit which Select a row in cell array & it is provided first and latched
into memory chips under the control of RAS signal.
➢ Low Order Address Bit which Selects a column and they are provided on same address pins
and latched using CAS signals.
The Multiplexing of address bit is usually done by Memory Controller Circuit.
The CS signal is usually active low, hence it is shown as CS.

✓ The Controller accepts a complete address & R/W signal from the processor, under the
control of a Request signal which indicates that a memory access operation is needed.
✓ The Controller then forwards the row & column portions of the address to the memory and
generates RAS & CAS signals. The controller provides the RAS-CAS timing, in addition
to its address multiplexing function.
✓ It also sends R/ W &CS signals to the memory.
✓ CS signal is usually active low.
✓ Data lines are connected directly between the processor and the memory.
✓ The clock signal is needed in SDRAM chips
✓ When used with DRAM chips, the memory controller has to provide all the information
needed to control the refreshing process.
✓ It contains a refresh counter that provides successive row address.
✓ Its function is to cause the refreshing of rows to be done within the period specified for a
particular device
Refresh Overhead:
All dynamic memories have to be [Link] DRAM, the period for refreshing all rows is 16ms
whereas 64ms in SDRAM.

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Eg: Given a SDRAM whose cell are arranged in 8K(= 8192) rows.
It takes 4 Clock cycles to access (read) each row. Then it takes 8192×4=32,768 cycles to refresh
all rows; if the clock rate is 133 MHz, then it takes 32,768/(133×10 ^ 6)=246×10^ -6 seconds;
suppose the typical refreshing period is 64ms, then the refresh overhead is
0.246/64=0.0038<0.4% of the total time available for accessing the memory.

READ ONLY MEMORY (ROM) ( conti.. of Memory Systems)

➢ Both SRAM and DRAM chips are volatile, which means that they lose the stored
information if power is turned off.
➢ Many applications require Non-volatile memory (which retain the stored information if
power is turned off).
➢ Eg: Operating System software has to be loaded from disk to memory which requires the
program that boots the Operating System i.e. it requires non-volatile memory.
➢ Non-volatile memory is used in embedded system.
➢ Since the normal operation involves only reading of stored data, a memory of this type is
called ROM.
Fig: ROM cell

At Logic value ‘0’ - Transistor (T) is connected to the ground point (P). Transistor switch is closed
& voltage on bit line nearly drops to zero.
At Logic value ‘1’ - Transistor switch is open. The bit line remains at high voltage.
➢ To read the state of the cell, the word line is activated.
➢ A Sense circuit at the end of the bit line generates the proper output value.

Types of ROM:
Different types of non-volatile memory are,
1. PROM
2. EPROM
3. EEPROM
4. Flash Memory

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1) Programmable Read-Only Memory (PROM):

➢ PROM allows the data to be loaded by the user. Programmability is achieved by inserting
a “fuse” at point P in a ROM cell.
➢ Before it is programmed, the memory contains all 0’s.
➢ The user can insert 1’s at the required location by burning out the fuse at these locations
using high-current pulse. This process is irreversible.
➢ The PROMs provides flexibility and faster data access. It is less expensive because they
can be programmed directly by the user.

2) Erasable Reprogrammable Read-Only Memory (EPROM):

➢ EPROM allows the stored data to be erased and new data to be loaded.
➢ In an EPROM cell, a connection to ground is always made at “P” and a special transistor
is used, which has the ability to function either as a normal transistor or as a disabled
transistor that is always turned “off”.
➢ During programming, an electrical charge is trapped in an insulated gate region.
➢ The charge is retained for more than 10 years because the charge has no leakage path. For
erasing this charge, ultra-violet light is passed through a quartz crystal window (lid).
This exposure to ultra-violet light dissipates the charge. During normal use, the quartz lid
is sealed with a sticker.
➢ EPROM can be erased by exposing it to ultra-violet light for duration of up to 40 minutes.
Usually, an EPROM eraser achieves this function.

Merits: It provides flexibility during the development phase of digital system. It is capable of
retaining the stored information for a long time.
Demerits: The chip must be physically removed from the circuit for reprogramming and its entire
contents are erased by UV light.

3) Electrically Erasable Programmable Read-Only Memory (EEPROM):

➢ EEPROM is programmed and erased electrically.
➢ It can be erased and reprogrammed about ten thousand times.
➢ Both erasing and programming take about 4 to 10 ms (millisecond).
➢ In EEPROM, any location can be selectively erased and programmed.
➢ EEPROMs can be erased one byte at a time, rather than erasing the entire chip. Hence,
the process of reprogramming is flexible but slow.
Merits: It can be both programmed and erased electrically. It allows the erasing of all cell contents
selectively.
Demerits: It requires different voltage for erasing, writing and reading the stored data.

4) Flash Memory:
➢ In EEPROM, it is possible to read & write the contents of a single cell.
➢ In Flash device, it is possible to read the contents of a single cell but it is only possible to
write the entire contents of a block.
➢ Prior to writing, the previous contents of the block are erased.

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➢ Eg:- In MP3 player, the flash memory stores the data that represents sound.
➢ Single flash chips cannot provide sufficient storage capacity for embedded system
application.
➢ There are 2 methods for implementing larger memory modules consisting of number of
chips. They are,
• Flash Cards
• Flash Drives.

Merits:
➢ Flash drives have greater density which leads to higher capacity & low cost per bit.
➢ It requires single power supply voltage & consumes less power in their operation.

Flash Cards:
➢ One way of constructing larger module is to mount flash chips on a small card.
➢ Such flash card has standard interface.
➢ The card is simply plugged into a conveniently accessible slot.
➢ Its memory size is of 8, 32,64MB, etc.
➢ Eg: A minute of music can be stored in 1MB of memory. Hence 64MB flash cards can
store an hour of music.
Flash Drives:
➢ Larger flash memory module can be developed by replacing the hard disk drive.
➢ The flash drives are designed to fully emulate the hard disk.
➢ The flash drives are solid state electronic devices that have no movable parts.
Merits:
➢ They have shorter seek and access time which results in faster response. They have low
power consumption which makes them attractive for battery driven application.
➢ They are insensitive to vibration.
Demerit:
➢ The capacity of flash drive (<1GB) is less than hard disk (>1GB).
➢ It leads to higher cost per bit.

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SPEED, SIZE AND COST

A big challenge in the design of a computer system is to provide a sufficiently large memory, with
a reasonable speed at an affordable cost.
Static RAM: Very fast, but expensive, because a basic SRAM cell has a complex circuit making
it impossible to pack a large number of cells onto a single chip.
Dynamic RAM: Simpler basic cell circuit, hence are much less expensive, but significantly slower
than SRAMs.
Magnetic disks: Storage provided by DRAMs is higher than SRAMs, but is still less than what is
necessary. Secondary storage such as magnetic disks provides a large amount of storage, but is
much slower than DRAMs.

CACHE MEMORIES
➢ Processor is much faster than the main memory. As a result, the processor has to spend
much of its time waiting while instructions and data are being fetched from the main
memory. These create a major obstacle towards achieving good performance.
➢ Speed of the main memory cannot be increased beyond a certain point.
➢ Cache Memory is a special very high-speed memory.
➢ It is used to speed up and synchronizing with high-speed CPU.

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➢ Cache memory is costlier than main memory or disk memory but economical than CPU
registers.
➢ Cache memory is an extremely fast memory type that acts as a buffer between RAM and
the CPU.
➢ It holds frequently requested data and instructions so that they are immediately available
to the CPU when needed.
➢ Cache memory is used to reduce the average time to access data from the Main memory.
➢ The cache is a smaller and faster memory which stores copies of the data from frequently
used main memory locations.

➢ Cache memory is based on the property of computer programs known as “locality of

reference”. Prefetching the data into cache before the processor needs it. It needs to predict
processor future access requirement [Locality of Reference].
Locality of Reference
Analysis of programs indicates that many instructions in localized areas of a program are executed
repeatedly during some period of time, while the others are accessed relatively less frequently.
These instructions may be the ones in a loop, nested loop or few procedures calling each other
repeatedly. This is called “locality of reference”.
• Temporal locality of reference: Recently executed instruction is likely to be executed
again very soon.
• Spatial locality of reference: Instructions with addresses close to a recently instruction are
likely to be executed soon.
Basic Cache Operations
Processor issues a Read request; a block of words is transferred from the main memory to the
cache, one word at a time. Subsequent references to the data in this block of words are found in
the cache.
At any given time, only some blocks in the main memory are held in the cache, which blocks in
the main memory in the cache is determined by a “mapping function”.
When the cache is full, and a block of words needs to be transferred from the main memory, some
block of words in the cache must be replaced. This is determined by a “replacement algorithm”.

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✓ Cache hit : Existence of a cache is transparent to the processor. The processor issues Read
and Write requests in the same manner. If the data is in the cache, it is called a Read or
Write hit.
✓ Read hit: The data is obtained from the cache.
✓ Write hit: Cache has a replica of the contents of the main memory. Contents of the cache
and the main memory may be updated simultaneously. This is the write-through protocol.
Update the contents of the cache, and mark it as updated by setting a bit known as the dirty
bit or modified bit. The contents of the main memory are updated when this block is
replaced. This is write-back or copy-back protocol.
✓ Cache miss: If the data is not present in the cache, then a Read miss or Write miss occurs.
✓ Read miss: Block of words containing this requested word is transferred from the memory.
After the block is transferred, the desired word is forwarded to the processor. The desired
word may also be forwarded to the processor as soon as it is transferred without waiting
for the entire block to be transferred. This is called load-through or early restart.
✓ Write-miss: Write-through protocol is used, and then the contents of the main memory are
updated directly. If write-back protocol is used, the block containing the addressed word is
first brought into the cache. The desired word is overwritten with new information.
MAPPING FUNCTIONS
The mapping functions are used to map a particular block of main memory to a particular block
of cache. This mapping function is used to transfer the block from main memory to cache
memory. Mapping functions determine how memory blocks are placed in the cache.
Three mapping functions:
1. Direct mapping.
2. Associative mapping.
3. Set-associative mapping.
1) Direct Mapping
• A particular block of main memory can be brought to a particular block of cache
memory. So, it is not flexible. The simplest way of associating main memory blocks
with cache block is the direct mapping technique.
• In this technique, block k of main memory maps into block k modulo m of the cache
(k % m), where m is the total number of blocks in cache. In this example, the value of
m is 128.
• In direct mapping technique, one particular block of main memory can be transferred
to a particular block of cache which is derived by modulo function.
Example:
Block j of the main memory maps to ( j modulo 128) of the cache.
Block 0, 128, 256 of main memory is maps to block 0 of cache memory.
Block1, 129, 257 of main memory maps to block 1 of cache memory & so on.

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More than one memory block is mapped onto the same position in the cache. This may lead to
contention for cache blocks even if the cache is not full. Resolve the contention by allowing
new block to replace the old block, leading to a trivial replacement algorithm.

Memory address is divided into three fields:

• Low order 4 bits determine one of the 16 words in a block.
• When a new block is brought into the cache, the next 7 bits determine which cache block
this new block is placed in.
• High order 5 bits determine which of the possible32 blocks is currently present in the
cache. These are tag bits.
➢ As execution proceeds, the high order 5 bits of the address are compared with tag bits
associated with that cache location.
➢ If they match, then the desired word is in that block of the cache.
➢ If there is no match, then the block containing the required word must be first read from
the main memory and loaded into the cache.

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Merit: It is easy to implement.

Demerit: It is not very flexible.

2) Associative mapping
➢ In the associative mapping technique, a main memory block can potentially reside in any
cache block position.
➢ In this case, the main memory address is divided into two groups, a low-order bit identifies
the location of a word within a block and a high-order bit identifies the block.
➢ The tag bits of an address received from the processor are compared to the tag bits of each
block of the cache to see if the desired block is present. This is called associative mapping.
➢ It gives complete freedom in choosing the cache location.
➢ A new block that has to be brought into the cache has to replace (eject) an existing block
if the cache is full.
➢ In this method, the memory has to determine whether a given block is in the cache.
➢ A search of this kind is called an associative Search.
Merit: It is more flexible than direct mapping technique.
Demerit: Its cost is high.
In the example 1:-,
➢ 12 tag bits will identify a memory block when it is resolved in the cache.

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Example 2:- 11 bits are required to identify a main memory block when it is resident in the cache,
high-order 11 bits are used as TAG bits and low-order 5 bits are used to identify a word within a
block.
• The TAG bits of an address received from the CPU must be compared to the TAG bits of
each block of the cache to see if the desired block is present.

In the associative mapping, any block of main memory can go to any block of cache, so it has got
the complete flexibility.
It might not be practical to use this complete flexibility of associative mapping technique due to
searching overhead, because the TAG field of main memory address has to be compared with the
TAG field of the entire cache block.
In this example, there are 128 blocks in cache and the size of TAG is 11 bits.
3) Set-Associative Mapping:
• It is the combination of direct and associative mapping.
• The blocks of the cache are grouped into sets and the mapping allows a block of the main
memory to reside in any block of the specified set.

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• In this case, the cache has two blocks per set, so the memory blocks 0,64,128……...4032
maps into cache set “0” and they can occupy either of the two block position within the
set.
Example 1:-
• 6 bit set field- Determines which set of cache contains the desired block.
• 6-bit tag field- The tag field of the address is compared to the tags of the two blocks of
the set to clock if the desired block is present.

✓ The cache which contains 1 block per set is called direct Mapping. cache that has “k‟
blocks per set is called as “k-way set associative cache”. Each block contains a control
✓ bit called a valid bit.
✓ The Valid bit indicates that whether the block contains valid data.
✓ The dirty bit indicates that whether the block has been modified during its cache residency.
✓ Valid bit=0-When power is initially applied to system
✓ Valid bit =1-When the block is loaded from main memory at first time.
✓ If the main memory block is updated by a source & if the block in the source is already
exists in the cache, then the valid bit will be cleared to “0‟.
✓ If Processor & DMA uses the same copies of data then it is called as the Cache Coherence
Problem.
Merit:
The Contention problem of direct mapping is solved by having few choices for block placement.

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The hardware cost is decreased by reducing the size of associative search.

Example 2:-
Consider the same cache memory and main memory organization another example.
✓ Organize the cache with 4 blocks in each set.
✓ The TAG field of associative mapping technique is divided into two groups, one is termed
as SET bit and the second one is termed as TAG bit.
✓ Each set contains 4 blocks, total number of set is 32.
✓ The main memory address is grouped into three parts: low-order 5 bits are used to
identifies a word within a block.
✓ Since there are total 32 sets present, next 5 bits are used to identify the set. High-order 6
bits are used as TAG bits.

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CONTENT ADDRESSABLE MEMORY (CAM)/ ASSOCIATIVE MEMORY

Many data-processing applications require the search of items in a table stored in memory.
An assembler program searches the symbol address table in order to extract the symbol’s binary
equivalent.
An account number may be searched in a file to determine the holder’s name and account status.
✓ The established way to search a table is to store all items where they can be addressed in
sequence.
✓ The search procedure is a strategy for choosing a sequence of addresses, reading the
content of memory at each address, and comparing the information read with the item being
searched until a match occurs.
✓ The number of accesses to memory depends on the location of the item and the efficiency
of the search algorithm.
✓ The time required to find an item stored in memory can be reduced considerably if stored
data can be identified for access by the content of the data itself rather than by an address.
✓ A memory unit accessed by content is called an associative memory or Content
Addressable Memory (CAM).
➢ This type of memory is accessed simultaneously and in parallel on the basis of data content
rather than by specific address or location.
➢ When a word is written in an associative memory, no address is given.
➢ The memory is capable of finding an empty unused location to store the word.
➢ When a word is to be read from an associative memory, the content of the word, or part of
the word, is specified.
➢ The memory locaters all words which match the specified content and marks them for
reading.
➢ Because of its organization, the associative memory is uniquely suited to do parallel
searches by data association.
➢ An associative memory is more expensive then a random access memory because each cell
must have storage capability as well as logic circuits for matching its content with an
external argument.
➢ For this reason, associative memories are used in applications where the search time is very
critical and must be very short.
HARDWARE ORGANIZATION
The block diagram of an associative memory consists of a memory array and logic from words
with n bits per word.
➢ The argument register A and key register K each have n bits, one for each bit of a word.
➢ The match register M has m bits, one for each memory word. Each word in memory is
compared in parallel with the content of the argument register.

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• The words that match the bits of the argument register set a corresponding bit in the match
register.
• After the matching process, those bits in the match register that have been set indicate the
fact that their corresponding words have been matched.
• Reading is accomplished by a sequential access to memory for those words whose
corresponding bits in the match register have been set.
• The key register provides a mask for choosing a particular field or key in the argument
word.
• The entire argument is compared with each memory word if the key register contains all
1’s.
• Otherwise, only those bits in the argument that have 1’s in their corresponding position of
the key register are compared.
• Thus the key provides a mask or identifying piece of information which specifies how the
reference to memory is made.
To illustrate with a numerical example:-Suppose that the argument register A and the key
register K have the bit configuration shown below. Only the three leftmost bits of A are compared
with memory words because K has 1’s in these positions. Word 2 matches the unmasked argument
field because the three leftmost bits of the argument and the word are equal.

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The relation between the memory array and external registers in an associative memory is shown
in below figure.

• The cells in the array are marked by the letter C with two subscripts.
• The first subscript gives the word number and the second specifies the bit position in the
word. Thus cell Cij is the cell for bit j in word i.
• A bit A j in the argument register is compared with all the bits in column j of the array
provided that K j =1. This is done for all columns j = 1, 2,…,n.
• If a match occurs between all the unmasked bits of the argument and the bits in word i, the
corresponding bit Mi in the match register is set to 1.
• If one or more unmasked bits of the argument and the word do not match, Mi is cleared to
0.
• The input bit is transferred into the storage cell during a write operation.
• The bit stored is read out during a read operation.
• The match logic compares the content of the storage cell with the corresponding unmasked
bit of the argument and provides an output for the decision logic that sets the bit in Mi.
READ OPERATION
• The matched words are read in sequence by applying a read signal to each word line whose
corresponding Mi bit is a 1.
• In most applications, the associative memory stores a table with no two identical items
under a given key.

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• In this case, only one word may match the unmasked argument field.
• By connecting output Mi directly to the read line in the same word position (instead of the
M register), the content of the matched word will be presented automatically at the output
lines and no special read command signal is needed.
• Furthermore, if we exclude words having a zero content, an all-zero output will indicate
that no match occurred and that the searched item is not available in memory.
WRITE OPERATION
• If the entire memory is loaded with new information at once prior to a search operation
then the writing can be done by addressing each location in sequence.
• This will make the device a random-access memory for writing and a content addressable
memory for reading.
• The advantage here is that the address for input can be decoded as in a random-access
memory.
• Thus instead of having m address lines, one for each word in memory, the number of
address lines can be reduced by the decoder to d lines, where m = 2d.

➢ If unwanted words have to be deleted and new words inserted one at a time, there is a need
for a special register to distinguish between active and inactive words. This register,
sometimes called a tag register, it have as many bits as there are words in the memory.
➢ For every active word stored in memory, the corresponding bit in the tag register is set to
1.
➢ A word is deleted from memory by clearing its tag bit to 0.
➢ Words are stored in memory by scanning the tag register until the first 0 bit is encountered.
This gives the first available inactive word and a position for writing a new word.
➢ After the new word is stored in memory it is made active by setting its tag bit to 1.
➢ An unwanted word when deleted from memory can be cleared to all 0’s if this value is
used to specify an empty location.

Prepared by Krishna C.J Module 5 Dept. of CSE, SNGIST