0% found this document useful (0 votes)

2 views4 pages

Verilog Adder Module with Delays

The document contains multiple Verilog modules for a half adder, showcasing different implementations with varying delays for the sum (s) and carry (c) outputs. It includes testbench modules that simulate the half adder's behavior with various input combinations. Additionally, it presents examples of both rise and fall delays in the signal assignments.

Uploaded by

jaisowmiyar

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as DOCX, PDF, TXT or read online on Scribd

0% found this document useful (0 votes)

2 views4 pages

Verilog Adder Module with Delays

Uploaded by

jaisowmiyar

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as DOCX, PDF, TXT or read online on Scribd

module adderhalf(

input a,b, output s,c);

assign #5 s=a^b;

assign #3 c=a&b;

endmodule

module adderh_tb;

reg a,b;

wire s,c;

adderhalf a1(.a(a),.b(b),.s(s),.c(c));

initial

begin

a=0;b=0; #5;

a=0;b=1; #5;

a=0;b=0; #5;

a=0;b=1; #5;

a=1;b=1; #5;

a=1;b=0; #5;

a=1;b=1; #5;

a=0;b=1; #5;

a=1;b=0; #5;

$finish;

end

endmodule
module adderhalf(

input a,b, output s,c);

assign #2 s=a^b;

assign #3 c=a&b;

endmodule

module adderh_tb;

reg a,b;

wire s,c;

adderhalf a1(.a(a),.b(b),.s(s),.c(c));

initial

begin

a=0;b=0; #1;

a=0;b=1; #1;

a=0;b=0; #1;

a=0;b=1; #1;

a=1;b=1; #1;

a=1;b=0; #1;

a=1;b=1; #1;

a=0;b=1; #1;

a=1;b=0; #1;
$finish;

end

endmodule

Fall delay

module adderhalf(

input a,b, output s,c);

buf #(0,3) b1(s,a);

and a1(c,a,b);

endmodule
Raise and Fall delay

module adderhalf(

input a,b, output s,c);

buf #(1,2) b1(s,a);

and a1(c,a,b);

endmodule

Verilog Modules for Arithmetic Circuits
No ratings yet
Verilog Modules for Arithmetic Circuits
61 pages
01
No ratings yet
01
4 pages
Verilog Code for Adders and Multipliers
No ratings yet
Verilog Code for Adders and Multipliers
20 pages
Verilog Code Examples for Digital Circuits
No ratings yet
Verilog Code Examples for Digital Circuits
15 pages
Verilog Code for Logic Gates and Adders
No ratings yet
Verilog Code for Logic Gates and Adders
2 pages
Verilog Logic Gates and Circuits Implementation
No ratings yet
Verilog Logic Gates and Circuits Implementation
23 pages
Tài Liệu Không Có Tiêu Đề
No ratings yet
Tài Liệu Không Có Tiêu Đề
9 pages
HDL Projects: Multiplexer, Adder, Flip-Flops
No ratings yet
HDL Projects: Multiplexer, Adder, Flip-Flops
14 pages
F1 2020 and 2019 Crackwatch Insights
No ratings yet
F1 2020 and 2019 Crackwatch Insights
8 pages
VLSI DESIGN AND TESTING LAB Manual
No ratings yet
VLSI DESIGN AND TESTING LAB Manual
16 pages
Verilog Program
No ratings yet
Verilog Program
34 pages
Verilog Code for Logic Gates and Adders
No ratings yet
Verilog Code for Logic Gates and Adders
20 pages
VLSI Lab Verilog Code Examples
No ratings yet
VLSI Lab Verilog Code Examples
4 pages
Disl Lab4
No ratings yet
Disl Lab4
13 pages
Verilog Counter and Adder Modules
No ratings yet
Verilog Counter and Adder Modules
6 pages
Verilog Code for Logic Gates and Adders
No ratings yet
Verilog Code for Logic Gates and Adders
31 pages
Fpga Pgmss
No ratings yet
Fpga Pgmss
10 pages
4-Bit Adder and ALU Design Examples
No ratings yet
4-Bit Adder and ALU Design Examples
3 pages
Verilog HDL Adders and Subtractors Guide
No ratings yet
Verilog HDL Adders and Subtractors Guide
18 pages
Verilog Modules for Arithmetic Operations
No ratings yet
Verilog Modules for Arithmetic Operations
28 pages
Full Adder Design and Testbench Code
No ratings yet
Full Adder Design and Testbench Code
2 pages
Verilog Code for Logic Gates and FFs
No ratings yet
Verilog Code for Logic Gates and FFs
10 pages
Design of Adders and Subtractors
No ratings yet
Design of Adders and Subtractors
26 pages
Verilog Modules for Flip-Flops and ALU
No ratings yet
Verilog Modules for Flip-Flops and ALU
8 pages
Full Adder, Ripple Adder, and ALU Code
No ratings yet
Full Adder, Ripple Adder, and ALU Code
9 pages
Half and Full Adder Verilog Modules
No ratings yet
Half and Full Adder Verilog Modules
2 pages
Digital Circuit Testbenches Overview
No ratings yet
Digital Circuit Testbenches Overview
7 pages
Digital Logic Design Modules in Verilog
No ratings yet
Digital Logic Design Modules in Verilog
35 pages
B221302CS
No ratings yet
B221302CS
13 pages
Combinational - Circuit 1st Part
No ratings yet
Combinational - Circuit 1st Part
48 pages
Logic Gates and Counters in Verilog
No ratings yet
Logic Gates and Counters in Verilog
11 pages
Verilog Code for Basic Logic Gates
No ratings yet
Verilog Code for Basic Logic Gates
68 pages
Verilog Testbenches for Digital Circuits
No ratings yet
Verilog Testbenches for Digital Circuits
13 pages
RTL Addr - Subtrctr.Mux
No ratings yet
RTL Addr - Subtrctr.Mux
16 pages
Combinational Circuits Lab
No ratings yet
Combinational Circuits Lab
9 pages
Digital Logic Design Modules in Verilog
No ratings yet
Digital Logic Design Modules in Verilog
17 pages
Digital Logic Lab Programs Overview
No ratings yet
Digital Logic Lab Programs Overview
14 pages
Verilog Code Examples for Digital Gates
No ratings yet
Verilog Code Examples for Digital Gates
25 pages
Adders Design and Simulation Guide
No ratings yet
Adders Design and Simulation Guide
9 pages
32-bit ALU and FSM Verilog Modules
No ratings yet
32-bit ALU and FSM Verilog Modules
4 pages
Digital Logic Circuits and Functions
No ratings yet
Digital Logic Circuits and Functions
32 pages
Full Adder and Half Adder Design
No ratings yet
Full Adder and Half Adder Design
10 pages
Implementing Adders and Subtractors in Verilog
No ratings yet
Implementing Adders and Subtractors in Verilog
24 pages
Verilog Testbenches for Digital Circuits
No ratings yet
Verilog Testbenches for Digital Circuits
10 pages
4-Bit Adder/Subtractor Verilog Code
No ratings yet
4-Bit Adder/Subtractor Verilog Code
3 pages
Digital System Design Lab Manual
No ratings yet
Digital System Design Lab Manual
37 pages
Verilog Adder and FSM Implementation
No ratings yet
Verilog Adder and FSM Implementation
9 pages
Verilog Counter and Adder Modules
No ratings yet
Verilog Counter and Adder Modules
8 pages
DSD Lab - Verilog Code
No ratings yet
DSD Lab - Verilog Code
20 pages
Logic Gates and Flip-Flops in Verilog
No ratings yet
Logic Gates and Flip-Flops in Verilog
11 pages
ASIC Design Lab Reports
No ratings yet
ASIC Design Lab Reports
16 pages
A Few Examples of Codes Using Behavioral Modeling
No ratings yet
A Few Examples of Codes Using Behavioral Modeling
16 pages
DLD Lab Report: Verilog Experiments
No ratings yet
DLD Lab Report: Verilog Experiments
40 pages
Verilog HDL VLSI Project Collection
No ratings yet
Verilog HDL VLSI Project Collection
23 pages
Verilog Code for Digital Circuits
No ratings yet
Verilog Code for Digital Circuits
18 pages
VD LAB 9 Final
No ratings yet
VD LAB 9 Final
7 pages

Verilog Adder Module with Delays

Uploaded by

Verilog Adder Module with Delays

Uploaded by

module adderhalf(

input a,b, output s,c);

input a,b, output s,c);

input a,b, output s,c);

buf #(0,3) b1(s,a);

input a,b, output s,c);

buf #(1,2) b1(s,a);

You might also like