Regulation – 2022 (CBCS Scheme) BEC303-Electronic Principles and Circuits

MODULE 2

Biasing in MOS Amplifier Circuits

An essential step in the design of a MOSFET amplifier circuit is the establishment of an appropriate
dc operating point for the transistor. This step is known as biasing or bias design. An appropriate
dc operating point or bias point is characterized by a stable and predictable dc drain current ID and
by a dc drain-to-source voltage VDS that ensures operation in the saturation region for all expected
input-signal levels.
Biasing by Fixing VGS
To bias a MOSFET is to fix its gate-to-source voltage VGS to the value required to provide the
desired ID. This voltage value can be derived from the power-supply voltage VDD through the use
of an appropriate voltage divider. Alternatively, it can be derived from another suitable reference
voltage that might be available in the system. Independent of how the voltage VGS may be generated,
it is not a good approach to biasing a MOSFET. To understand the reason for this statement, recall
that

and note that the values of the threshold voltage Vt, the oxide-capacitance Cox, and (to a lesser
extent) the transistor aspect ratio vary widely among devices of supposedly the same size and type.
This is certainly the case for discrete devices, in which large spreads in the values of these
parameters occur among devices of the same manufacturer’s part number. The spread is also large
in integrated circuits, especially among devices fabricated on different wafers and certainly between
different batches of wafers. Furthermore, both Vt and μn depend on temperature, with the result
that if we fix the value of VGS, the drain current ID becomes very much temperature dependent. To
emphasize the point that biasing by fixing VGS is not a good technique, we showin Fig. 1.9 two
iD– VGS characteristic curves representing extreme values in a batch of MOSFETs of the same type.
Observe that for the fixed value of VGS, the resultant spread in the values of the drain current can
be substantial.

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 Regulation – 2022 (CBCS Scheme) BEC303-Electronic Principles and Circuits

Fig.1.9 The use of fixed bias (constant VGS) can result in a large variability in the value of ID.
Devices 1 and 2 represent extremes among units of the same type.

1.5.1 Biasing by Fixing VG and Connecting a Resistance in the Source

An excellent biasing technique for discrete MOSFET circuits consists of fixing the dc
voltage at the gate, VG, and connecting a resistance in the source lead, as shown in Fig. 1.10(a).
For this circuit we can write

36
Now, if VG is much greater than VGS, ID will be mostly determined by the values of VG and RS.
However, even if VG is not much larger than VGS, resistor RS provides negative feedback, which
acts to stabilize the value of the bias current ID.
Equation (36) indicates that since VG is constant, VGS will have to decrease. This in turn results in
a decrease in ID, a change that is opposite to that initially assumed.

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 Regulation – 2022 (CBCS Scheme) BEC303-Electronic Principles and Circuits

Fig. 1.10 Biasing using a fixed voltage at the gate, VG, and a resistance in the source lead, RS: (a)
basic arrangement; (b) reduced variability in ID; (c) practical implementation using a single
supply; (d) coupling of a signal source to the gate using a capacitor CC1; (e) practical
implementation using two supplies.

Thus the action of RS works to keep ID as constant as possible. This negative feedback action of
RS gives it the name degeneration resistance. Figure 1.10(b) provides a graphical illustration of the
effectiveness of this biasing scheme. The iD– VGS characteristics for two devices that represent the
extremes of a batch of MOSFETs. Superimposed on the device characteristics is a straight line
represents the constraint imposed by the bias circuit—namely, Eq. (36). The intersection of this
straight line with the iD– VGS characteristic curve provides the coordinates (ID and VGS) of the bias
point. Compared to the case of fixed VGS, here the variability obtained in ID is much smaller. The
variability decreases as VG and RS are made larger (thus providing a bias line that is less steep). Two
possible practical discrete implementations of this bias scheme are shown in Fig. 1.10(c) and (e).
The circuit in Fig. 1.10(c) utilizes one power-supply VDD and derives VG through a voltage divider

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 Regulation – 2022 (CBCS Scheme) BEC303-Electronic Principles and Circuits

(RG1, RG2). Since IG = 0, RG1 and RG2 can be selected to be very large (in the megohm range),
allowing the MOSFET to present a large input resistance to a signal source that may be connected
to the gate through a coupling capacitor, as shown in Fig. 1.10(d). Here capacitor CC1 blocks dc and
thus allows us to couple the signal vsig to the amplifier input without disturbing the MOSFET dc
bias point. The value of CC1 should be selected large enough to approximate a short circuit at all
signal frequencies of interest. In the circuit of Fig. 1.10(c), resistor RD is selected to be as large as
possible to obtain high gain but small enough to allow for the desired signal swing at the drain while
keeping the MOSFET in saturation at all times. When two power supplies are available, as is often
the case, the somewhat simpler bias arrangement of Fig. 1.10(e) can be utilized. This circuit is an
implementation of Eq. (36), with VG replaced by VSS. Resistor RG establishes a dc ground at the
gate and presents a high input resistance to a signalsource that may be connected to the gate through
a coupling capacitor.
1.5.1 Biasing Using a Drain-to-Gate Feedback Resistor
A simple and effective discrete-circuit biasing arrangement utilizing a feedback resistor connected
between the drain and the gate is shown in Fig. 1.11. Here the large feedback resistance RG (usually
in the megohm range) forces the dc voltage at the gate to be equal to that at the drain (because IG
= 0). Thus we can write
VGS = VDS = VDD – ID RD
VDD = VGS + ID RD ---------------------------------------------------------------------------- 37
which is identical in form to Eq. (36), which describes the operation of the bias scheme .
If ID for some reason changes, say increases, then Eq. (37) indicates that VGS must decrease. The
decrease in VGS in turn causes a decrease in ID, a change that is opposite in direction to the one
originally assumed. Thus the negative feedback or degeneration provided by RG works to keep the
value of ID as constant as possible. The circuit of Fig. 1.11 can be utilized as an amplifier by
applying the input voltage signal to the gate via a coupling capacitor so as not to disturb the dc bias
conditions already established. The amplified output signal at the drain can be coupled to nother
part of the circuit, again via a capacitor.

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 Regulation – 2022 (CBCS Scheme) BEC303-Electronic Principles and Circuits

Fig 1.11 Biasing the MOSFET using a large drain to gate feedback resistance RG.
1.6 Small-Signal Operation and Models

Linear amplification can be obtained by biasing the MOSFET to operate in the saturation region
and by keeping the input signal small. The conceptual amplifier circuit shown in Fig. 1.12. The
MOS transistor is biased by applying a dc voltage VGS, and the input signal to be amplified, vgs,
is superimposed on the dc bias voltage VGS . The output voltage is taken at the drain.

Fig.1.12 Conceptual circuit utilized to study the operation of the MOSFET as a small-signal
amplifier

1.6.1 The DC Bias Point

The dc bias current ID can be found by setting the signal vgs to zero; thus

38
where we have neglected channel-length modulation (i.e., we have assumed λ = 0). Here

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 Regulation – 2022 (CBCS Scheme) BEC303-Electronic Principles and Circuits

is the overdrive voltage at which the MOSFET is biased to operate. The dc

voltage at the drain, VDS, will be

39
To ensure saturation-region operation, we must have

The total voltage at the drain will have a signal component superimposed on VDS, VDS has to be
sufficiently greater than to allow for the required signal swing.

1.6.2 The Signal Current in the Drain Terminal

The input signal vgs applied. The total instantaneous gate-to source voltage will be

40

41

The first term on the right-hand side of Eq. (41) can be recognized as the dc bias current ID (Eq. 38).
The second term represents a current component that is directly proportional to the input signal vgs.
The third term is a current component that is proportional to the square of the input signal. This last
component is undesirable because it represents nonlinear distortion. To reducethe nonlinear
distortion introduced by the MOSFET, the input signal should be kept small so that

Resulting in vgs

42

43

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 Regulation – 2022 (CBCS Scheme) BEC303-Electronic Principles and Circuits

If this small-signal condition is satisfied, we may neglect the last term in Eq. (41) and express iD
as

44

45
In terms of the overdrive voltage Vov

Fig. 1.13 Small signal operation of the MOSFET amplifier

1.6.3 The Voltage Gain

Returning to the circuit of Fig. 1.12, we can express the total instantaneous drain voltage vDS as

follows: --------------------------------------------------------------------------------------------------- 48

49

The minus sign in Eq. (49) indicates that the output signal vds is 180° out of phase with respect to
the input signal vgs. This is illustrated in Fig. 1.14, which shows vGS and vDS.
The input signal is assumed to have a triangular waveform with an amplitude much smaller than
2(VGS – Vt), the small-signal condition in Eq. (42), to ensure linear operation.
For operation in the saturation region at all times, the minimum value of vDS should not fall below
the corresponding value of vGS by more than Vt. Also, the maximum value of vDS should be
smaller than VDD; otherwise the FET will enter the cutoff region and the peaks of the output signal
waveform will be clipped off.

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 Regulation – 2022 (CBCS Scheme) BEC303-Electronic Principles and Circuits

Fig 1.14. Total instantaneous voltages VGS and VDS for the circuit given above.

1.6.4 Small-Signal Equivalent-Circuit Models

The FET behaves as a voltage-controlled current source. It accepts a signal vgs between gate and
source and provides a current gmvgs at the drain terminal. The input resistance of this controlled
source is very high—ideally, infinite. The output resistance—that is, the resistance looking into the
drain—also is high, and we have assumed it to be infinite thus far.

Fig. 1.15(a), which represents the small-signal operation of the MOSFET and is thus a small- signal
model or a small-signal equivalent circuit. In the analysis of a MOSFET amplifier circuit, the
transistor can be replaced by the equivalent circuit model shown in Fig. 1.15(a). The rest of the
circuit remains unchanged except that ideal constant dc voltage sources are replaced by short
circuits. This is a result of the fact that the voltage across an ideal constant dc voltage source does
not change, and thus there will always be a zero voltage signal across a constant dc voltage source.
A dual statement applies for constant dc current sources; namely, the signal current of an

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 Regulation – 2022 (CBCS Scheme) BEC303-Electronic Principles and Circuits

ideal constant dc current source will always be zero, and thus an ideal constant dc current source
can be replaced by an open circuit in the small-signal equivalent circuit of the amplifier.

Fig 1.15 Small-signal models for the MOSFET: (a) neglecting the dependence of iD on vDS in
saturation (the channel-length modulation effect); and (b) including the effect of channel-length

modulation, modeled by output resistance

The circuit resulting can then be used to perform any required signal analysis, such as calculating
voltage gain. The most serious shortcoming of the small-signal model of Fig. 1.15(a) is that it
assumes the drain current in saturation to be independent of the drain voltage. The MOSFET
characteristics in saturation, we know that the drain current does in fact depend on vDS in a linear
manner.

50

where VA = 1/λ is a MOSFET parameter that either is specified or can be measured. For a given
process technology, VA is proportional to the MOSFET channel length. The current ID is the value
of the dc drain current without the channel-length modulation taken into account; that is,

51

Typically, ro is in the range of 10 kΩ to 1000 kΩ. The accuracy of the small signal model can be
improved by including ro in parallel with the controlled source, as shown in Fig. 1.15(b). The small-
signal model parameters gm and ro depend on the dc bias point of the MOSFET. Returning to the
amplifier of Fig. 1.11, we find that replacing the MOSFET with the small-signal model of Fig.
1.15(b) results in the voltage-gain expression

52

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 Regulation – 2022 (CBCS Scheme) BEC303-Electronic Principles and Circuits

Thus, the finite output resistance ro results in a reduction in the magnitude of the voltage gain.
Although the analysis above is performed on an NMOS transistor, the results, and the equivalent
circuit models of Fig. 1.15, apply equally well to PMOS devices, except for using │VGS│,
│Vt,││ Vov│and │VA│ and replacing kn with kp.

1.6.5 The Transconductance gm

The MOSFET transconductance given by Eq. (45), which we rewrite with kn = k ’n (W/L) as
follows:

53

gm is proportional to the process transconductance parameter and to the W / L ratio of

the MOS transistor; hence to obtain relatively large transconductance the device must be short
and wide. For a given device the transconductance is proportional to the overdrive voltage, , the
amount by which the bias voltage VGS exceeds the threshold voltage Vt. Increasing gm by
biasing the device at a larger VGS has the disadvantage of reducing the allowable voltage signal
swing at the drain.

Another useful expression for gm can be obtained by substituting for VOV in Eq. (53) by
[from Eq. (38)]:

54
This expression shows two things:
1. For a given MOSFET, gm is proportional to the square root of the dc bias current.
2. At a given bias current, gm is proportional to . √W / L

In contrast, the transconductance of the bipolar junction transistor (BJT) is proportional to the bias
current and is independent of the physical size and geometry of the device.

To gain some insight into the values of gm obtained in MOSFETs consider an integrated-circuit
device operating at ID = 0.5 mA and having kn’ = 120µA/v2. Equation (54) shows that for W / L =
1, gm = 0.35 mA/V, whereas a device for which W / L = 100 has gm = 3.5 mA/V. In contrast, a
BJT operating at a collector current of 0.5 mA has gm = 20 mA/V.

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 Regulation – 2022 (CBCS Scheme) BEC303-Electronic Principles and Circuits

Yet another useful expression for gm of the MOSFET can be obtained by substituting for
kn’(W /L) in Eq. (53) by 2ID/(VGS − Vt)2:

55
A convenient graphical construction that clearly illustrates this relationship is shown in
Fig. [Link] summary, there are three different relationships for determining gm—Eqs.
(53), (54), and (55)—and there are three design parameters—(W / L), VOV, and ID, any
two of which can be chosen independently. That is, the designer may choose to operate
the MOSFET with a certain overdrive voltage VOV and at a particular current ID; the
required W / L ratio can then be found and the resulting gm determined.

Fig. 1.16 The slope of the tangent at the bias point Q intersects the Vov axis at
1/2VovThus gm = Id/1/2Vov.
 Regulation – 2022 (CBCS Scheme) BEC303-Electronic Principles and Circuits

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 Regulation – 2022 (CBCS Scheme) BEC303-Electronic Principles and Circuits

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 Regulation – 2022 (CBCS Scheme) BEC303-Electronic Principles and Circuits

Prepared by [Link] Princye/ [Link], Sri Sairam College of Engineering, Anekal.

 Regulation – 2022 (CBCS Scheme) BEC303-Electronic Principles and Circuits

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 Regulation – 2022 (CBCS Scheme) BEC303-Electronic Principles and Circuits

Prepared by [Link] Princye/ [Link], Sri Sairam College of Engineering, Anekal.

Prepared by [Link] Princye/ [Link], Sri Sairam College of Engineering, Anekal.

 Regulation – 2022 (CBCS Scheme) BEC303-Electronic Principles and Circuits

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 Regulation – 2022 (CBCS Scheme) BEC303-Electronic Principles and Circuits

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 Regulation – 2022 (CBCS Scheme) BEC303-Electronic Principles and Circuits

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 Regulation – 2022 (CBCS Scheme) BEC303-Electronic Principles and Circuits

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 Regulation – 2022 (CBCS Scheme) BEC303-Electronic Principles and Circuits

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