Memory Organization in Computers
Memory Organization in Computers
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Classification of Memory
In the computer system, we need computer memory to store various types of data
like text, images, video, audio, documents, etc. We can retrieve it when the data is
required. For example, when we write and execute any computer program, it is
initially stored in primary memory. If the processor does not need particular items
for a longer time, the program or data is automatically saved into the permanent
or secondary memory. Then the data is called from secondary memory to main
memory and performs the execution of codes.
Features of Memory
Following are the different features of the memory system that includes:
o Internal memory: The transfer rate of bits is mostly equal to the word
size.
o External memory: The transfer rate of bit or unit is not equal to the
word length. It is always greater than a word or may be referred to
as blocks.
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o Memory Cycle Time: Total time required to access memory block and
additional required time before starting second access.
Classification of Memory
Primary memory is also known as the computer system's main memory that
communicates directly within the CPU, Auxiliary memory and the Cache memory.
Main memory is used to kept programs or data when the processor is active to use
them. When a program or data is activated to execute, the processor first loads
instructions or programs from secondary memory into main memory, and then the
processor starts execution. Accessing or executing of data from primary memory is
faster because it has a cache or register memory that provides faster response, and
it is located closer to the CPU. The primary memory is volatile, which means the
data in memory can be lost if it is not saved when a power failure occurs. It is
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costlier than secondary memory, and the main memory capacity is limited as
compared to secondary memory.
Random Access Memory (RAM) is one of the faster types of main memory accessed
directly by the CPU. It is the hardware in a computer device to temporarily store
data, programs or program results. It is used to read/write data in memory until
the machine is working. It is volatile, which means if a power failure occurs or the
computer is turned off, the information stored in RAM will be lost. All data stored
in computer memory can be read or accessed randomly at any time.
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o SRAM
o DRAM
Characteristics of DRAM
3. It is expensive.
5. Longer life
6. Large size
SRAM DRAM
The access time of SRAM is slow. The access time of DRAM is high.
It uses flip-flops to store each bit of It uses a capacitor to store each bit of
information. information.
Advantages of RAM
o The processor can read information faster than a hard disc, floppy, USB, etc.
Disadvantages of RAM
Types of ROM
MROM is the oldest type of read-only memory whose program or data is pre-
configured by the integrated circuit manufacture at the time of
manufacturing. Therefore, a program or instruction stored within the MROM
chip cannot be changed by the user.
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It is a type of digital read-only memory, in which the user can write any type
of information or program only once. It means it is the empty PROM chip in
which the user can write the desired content or program only once using the
special PROM programmer or PROM burner device; after that, the data or
instruction cannot be changed or erased.
It is the type of read only memory in which stored data can be erased and re-
programmed only once in the EPROM memory. It is a non-volatile memory
chip that holds data when there is no power supply and can also store data
for a minimum of 10 to 20 years. In EPROM, if we want to erase any stored
data and re-programmed it, first, we need to pass the ultraviolet light for 40
minutes to erase the data; after that, the data is re-created in EPROM.
5. Flash ROM:
Advantages of ROM
Disadvantages of ROM
1. Store data cannot be updated or modify except to read the existing data.
3. It takes around 40 minutes to destroy the existing data using the high charge
of ultraviolet light.
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RAM ROM
Read and write operations can be Only Read operation can be performed.
performed.
The size of the chip is bigger than the The size of the chip is smaller than the
ROM chip to store the data. RAM chip to store the same amount of
data.
Types of RAM: DRAM and SRAM Types of ROM: MROM, PROM, EPROM,
EEPROM
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Secondary Memory
o It can store large collections of different types, such as audio, video, pictures,
text, software, etc.
Hard Disk
Floppy Disk
A floppy disk is a secondary storage system that consisting of thin, flexible magnetic
coating disks for holding electronic data such as computer files. It is also known as
Floppy Diskette that comes in three sizes like 8 inches, 5.5 inches and 3.5 inches.
The stored data of a floppy disk can be accessed through the floppy disk drive.
Furthermore, it is the only way through a new program installed on a computer or
backup of the information. However, it is the oldest type of portable storage device,
which can store data up to 1.44 MB. Since most programs were larger, that required
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multiple floppy diskettes to store large amounts of data. Therefore, it is not used
due to very low memory storage.
CD (Compact Disc)
A CD is an optical disk storage device, stands for Compact Disc. It is a storage device
used to store various data types like audio, videos, files, OS, Back-Up file, and any
other information useful to a computer. The CD has a width of 1.2 mm and 12 cm
in height, which can store approximately 783 MB of data size. It uses laser light to
read and write data from the CDs.
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Types of CDs
1. CD-ROM (Compact Disc Read Only Memory): It is mainly used for bulk size
mass like audio CDs, software and computer games at the time of
manufacture. Users can only read data, text, music, videos from the disc, but
they cannot modify or burnt it.
2. CD-R (Compact Disc Recordable): The type of Compact Disc used to write
once by the user; after that, it cannot be modified or erased.
DVD Drive/Disc
DVD is an optical disc storage device, stands for Digital Video Display or Digital
Versatile Disc. It has the same size as a CD but can store a larger amount of data
than a compact disc. It was developed in 1995 by Sony, Panasonic, Toshiba and
Philips four electronics companies. DVD drives are divided into three types, such as
DVD ROM (Read Only Memory), DVD R (Recordable) and DVD RW (Rewritable or
Erasable). It can store multiple data formats like audio, videos, images, software,
operating system, etc. The storing capacity of data in DVD is 4.7 GB to 17 GB.
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Blu Ray is an Optical disc storage device used to store a large amount of data or
high definition of video recording and playing other media files. It uses laser
technology to read the stored data of the Blu-ray Disk. It can store more data at a
greater density as compared to CD/ DVD. For example, compact discs allow us to
store 700 MB of data, and in DVDs, it provides up to 8 GB of storage capacity, while
Blu-ray Discs provide 28 GB of space to store data.
Pen Drive
A pen drive is a portable device used to permanently store data and is also known
as a USB flash drive. It is commonly used to store and transfer the data connected
to a computer using a USB port. It does not have any moveable part to store the
data; it uses an integrated circuit chip that stores the data. It allows the users to
store and transfer data like audio, videos, images, etc. from one computer to any
USB pen drive. The storing capacity of pen drives from 64 MB to 128 GB or more.
Cache Memory
It is a small-sized chip-based computer memory that lies between the CPU and the
main memory. It is a faster, high performance and temporary memory to enhance
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the performance of the CPU. It stores all the data and instructions that are often
used by computer CPUs. It also reduces the access time of data from the main
memory. It is faster than the main memory, and sometimes, it is also called CPU
memory because it is very close to the CPU chip. The following are the levels of
cache memory.
3. L3 Cache: L3 cache levels are generally used with high performance and
capacity of the computer. It is built into a motherboard. Its speed is very
slow, and the maximum size up to 8 MB.
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2. It stores all data and instructions that are repeatedly used by the CPU for
improving the performance of a computer.
Register Memory
The register memory is a temporary storage area for storing and transferring the
data and the instructions to a computer. It is the smallest and fastest memory of a
computer. It is a part of computer memory located in the CPU as the form of
registers. The register memory is 16, 32 and 64 bits in size. It temporarily stores
data instructions and the address of the memory that is repeatedly used to provide
faster response to the CPU.
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Data can be access directly by the Data cannot be accessed directly by the
processor or CPU. I/O processor or CPU.
It required the power to retain the It does not require power to retain the
data in primary memory. data in secondary memory.
Memory Interleaving
CPU CPU
Cache Cache
Memory Memory
In high order memory interleaving, most significant bits of the memory address
decides, memory banks where a particular location resides. But, in low order
interleaving least significant bits of the memory address decides the memory
banks.
One major difference between high order and low order interleaving is,
consecutive memory location is found in the same memory module in high order
interleaving. But in low order interleaving consecutive memory location is found in
consecutive banks.
Memory Hierarchy
• Remote Storage
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Levels of memory:
• Level 1 or Register –
It is a type of memory in which data is stored and accepted that are
immediately stored in CPU. Most commonly used register is
accumulator, Program counter, address register etc.
• Level 2 or Cache memory –
It is the fastest memory which has faster access time where data is
temporarily stored for faster access.
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We can improve Cache performance using higher cache block size, higher
associativity, reduce miss rate, reduce miss penalty, and reduce the time to hit in
the cache.
access instructions whose addresses are near one another. The property of
locality of reference is mainly shown by loops and subroutine calls in a program.
Temporal locality means current data or instruction that is being fetched may be
needed soon. So we should store that data or instruction in the cache memory so
that we can avoid repeated searching in main memory for the same data.
Spatial locality means instruction or data near to the current memory location
that is being fetched, may be needed soon in the near future. This is slightly
different from the temporal locality. Here we are talking about nearly located
memory locations while in temporal locality we were talking about the memory
location that was being fetched repeatedly.
Cache Mapping
There are three different types of mapping used for the purpose of cache memory
which are as follows: Direct mapping, Associative mapping, and Set-Associative
mapping. These are explained below.
1. Direct Mapping
The simplest technique, known as direct mapping, maps each block of
main memory into only one possible cache line. or
In Direct mapping, assign each memory block to a specific line in the
cache. If a line is previously taken up by a memory block when a new block
needs to be loaded, the old block is trashed. An address space is split into
two parts index field and a tag field. The cache is used to store the tag
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field whereas the rest is stored in the main memory. Direct mapping`s
performance is directly proportional to the Hit ratio.
i = j modulo m
where
For purposes of cache access, each main memory address can be viewed
as consisting of three fields. The least significant w bits identify a unique
word or byte within a block of main memory. In most contemporary
machines, the address is at the byte level. The remaining s bits specify
one of the 2s blocks of main memory. The cache logic interprets these s
bits as a tag of s-r bits (most significant portion) and a line field of r bits.
This latter field identifies one of the m=2r lines of the cache.
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2. Associative Mapping
In this type of mapping, the associative memory is used to store content
and addresses of the memory word. Any block can go into any line of the
cache. This means that the word id bits are used to identify which word
in the block is needed, but the tag becomes all of the remaining bits. This
enables the placement of any word at any place in the cache memory. It
is considered to be the fastest and the most flexible mapping form.
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3. Set-associative Mapping –
This form of mapping is an enhanced form of direct mapping where the
drawbacks of direct mapping are removed. Set associative addresses the
problem of possible thrashing in the direct mapping method. It does this
by saying that instead of having exactly one line that a block can map to
in the cache, we will group a few lines together creating a set. Then a
block in memory can map to any one of the lines of a specific set..Set-
associative mapping allows that each word that is present in the cache
can have two or more words in the main memory for the same index
address. Set associative cache mapping combines the best of direct and
associative cache mapping techniques.
In this case, the cache consists of a number of sets, each of which
consists of a number of lines. The relationships are
m=v*k
i= j mod v
where
v=number of sets
Secondary Cache
Secondary cache is placed between the primary cache and the rest of the
memory. It is referred to as the level 2 (L2) cache. Often, the Level 2 cache is also
housed on the processor chip.
Cache Write Policies
• Write-through
• Write-around
• Write-back
Write-through
Suppose we design our cache to ensure consistency first. That is, we’d want to
update our backing store synchronously before sending the response back to the
client, we use write through policy.
In case the requested entry is not found in the cache, we create an entry in cache
storage first.
Write-around
Now, write-through provides the best outcome in case we expect written data to
be accessed soon. Depending on our cache usage pattern, this might not be true.
If we do not expect a read operation shortly after, the cache would become
polluted with the entries we’re not using. To avoid cache pollution, we may bypass
cache entry allocation in case of a cache miss.
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Write-back
While write-through provides us the best consistency, it does not help us with write
operation latency – the cache returns a response to the client only after the backing
storage is updated.
We may take advantage of our fast cache storage to streamline this as well. To do
this, we would have to return the response before updating the backing storage. In
this case, the backing storage update happens asynchronously in a separate
sequence.
We can kick off such a sequence in several ways – right before the response return,
periodically, or integrated into cache eviction based on cache entry dirty state. For
CPU caches, we use a dirty bit as a state indicator.
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Cache Coherency
In a shared memory system, multiple processors with a separate cache memory for
each processor, it is possible to have many copies of any one instruction operand:
one copy in the main memory and one in each cache memory. When one copy of
an operand is changed, the other copies of the operand must be changed also.
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Example :
Cache and the main memory may have inconsistent copies of the same object.
Suppose there are three processors, each having cache. Consider the following
scenario:-
• Again, processor 1 writes as X : 64, Its locally cached copy is updated. Now,
processor 3 reads X, what value should it get?
Cache coherence is the discipline that ensures that changes in the values of shared
operands are propagated throughout the system in a timely fashion.
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MESI Protocol:
The size of virtual storage is limited by the addressing scheme of the computer
system and the amount of secondary memory is available not by the actual
number of the main storage locations.
1. All memory references within a process are logical addresses that are
dynamically translated into physical addresses at run time. This means
that a process can be swapped in and out of the main memory such that
it occupies different places in the main memory at different times during
the course of execution.
2. A process may be broken into a number of pieces and these pieces need
not be continuously located in the main memory during execution. The
combination of dynamic run-time address translation and use of page or
segment table permits this.
If these characteristics are present then, it is not necessary that all the pages or
segments are present in the main memory during execution. This means that the
required pages need to be loaded into memory whenever required.
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Memory Management
A memory management unit (MMU) is responsible for translating the segment and
offset into a physical address, and for performing checks to make sure the
translation can be done and that the reference to that segment and offset is
permitted.
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Advantages of Segmentation
• No internal fragmentation
• Less overhead
• The segment table is of lesser size as compare to the page table in paging.
Disadvantages of Segmentation
Paging
It uses stack for managing the It uses heap for managing the
3
static allocation of memory dynamic allocation of memory
Non-Contiguous Memory
[Link]. Contiguous Memory Allocation Allocation
Non-Contiguous Memory
[Link]. Contiguous Memory Allocation Allocation
Why Paging ?
• First level table, known as Page Directory, contains 1K entries for the second
level table, known as Page Table
Cache Coherency
In a shared memory system, multiple processors with a separate cache memory for
each processor, it is possible to have many copies of any one instruction operand:
one copy in the main memory and one in each cache memory. When one copy of
an operand is changed, the other copies of the operand must also be changed.
Example:
Cache and the main memory may have inconsistent copies of the same object.
Suppose there are three processors, each having cache. Consider the following
scenario:-
Cache coherence is the discipline that ensures that changes in the values of shared
operands are propagated throughout the system in a timely fashion.
MESI Protocol:
• With shared memory and more than one processor, it is vital to ensure
that data in a processor's cache is an accurate reflection of main
memory.
• These are the extra bits stored with each cache line in order to track
its modification status within the shared memory system.
Present
Frame (1)/ Protection Reference Caching
Dirty
No Absent (R/W/X) (0/1) (Enable/Disable)
(0)
• The processor stores the most recently used page table entries in on-chip
cache called translation lookaside buffer or TLB.
• Most of the microprocessors has separate TLB's for the data and instruction
caches.
• Bus cycles to the page tables in memory are performed only when the TLBs
do not contain the translation information for a requested page
Paging Segmentation
Paging divides our program into Segmentation divides our program into
various fixed size pages. various variable size segments.
In this, the logical address is divided In this, the logical address is divided
into two things: page number and page into two things: segment number and
offset segment offset
The entry of the page table contains On the other hand, the entry of
frame number and flag bits so that it segment table contains base address,
can represent the details about the some protection bits of the segments
pages and segment offset
Page Fault – A page fault happens when a running program accesses a memory
page that is mapped into the virtual address space, but not loaded in physical
memory.
Since actual physical memory is much smaller than virtual memory, page faults
happen. In case of page fault, Operating System might have to replace one of the
existing pages with the newly needed page. Different page replacement algorithms
suggest different ways to decide which page to replace. The target for all algorithms
is to reduce the number of page faults.
This is the simplest page replacement algorithm. In this algorithm, the operating
system keeps track of all pages in the memory in a queue, the oldest page is in the
front of the queue. When a page needs to be replaced, page in the front of the
queue is selected for removal.
• Initially all slots are empty, so when 1, 3, 0 came they are allocated to the
empty slots —> 3 Page Faults.
Belady’s Anomaly– Belady’s anomaly proves that it is possible to have more page
faults when increasing the number of page frames while using the First in First Out
(FIFO) page replacement algorithm. For example, if we consider reference string
3, 2, 1, 0, 3, 2, 4, 3, 2, 1, 0, 4 and 3 frames, we get 9 total page faults, but if we
increase frames to 4, we get 10 page faults.
In this algorithm, pages are replaced which would not be used for the longest
duration of time in the future.
• Initially all slots are empty, so when 7 0 1 2 are allocated to the empty slots
—> 4 Page faults.
• When 3 came it will take the place of 7 because it is not used for the
longest duration of time in the future.—>1 Page fault.
• Now for the further page reference string —> 0 Page fault (Hit) because
they are already available in the memory.
Optimal page replacement is perfect, but not possible in practice as the operating
system cannot know future requests. The use of Optimal Page replacement is to
set up a benchmark so that other replacement algorithms can be analysed against
it.
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• Initially all slots are empty, so when 7 0 1 2 are allocated to the empty slots
—> 4 Page faults.
• When 3 came it will take the place of 7 because it is least recently used
—>1 Page fault.
• Now for the further page reference string —> 0 Page fault (Hit) because
they are already available in the memory.
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• As the name suggests, this algorithm works on the principle of “Last in First
out“.
• It replaces the newest page that arrived at last in the main memory.
• So, this algorithm may behave like any other algorithm like FIFO, LIFO, LRU,
Optimal etc.