Module II
Delay Models: Introduction, Definitions, Timing Optimization. RC Delay
Model: Effective Resistance, Gate and Diffusion Capacitance, Equivalent RC
Circuits, Elmore Delay, Layout Dependence of Capacitance, Determining
Effective Resistance. Linear Delay Model: Logical Effort, Parasitic Delay,
Delay in a Logic Gate. Logical Effort of Paths: Delay in Multistage Logic
Networks, Choosing the Best Number of Stages, Example.
Interconnect: Introduction, Wire Geometry, Interconnect Modelling:
Resistance, Capacitance, Inductance (Pi modelling). Interconnect Impact:
Delay, Energy, Crosstalk, Effective Resistance and Elmore Delay.
Clocks: Clock System Architecture, Global Clock Generation, Global Clock
Distribution, Local Clock Gaters, Adaptive Deskewing, PLLs and DLLs.
I/O: Basic I/O Pad Circuits, Electrostatic Discharge Protection.
Definitions
• When an input changes, the output will retain its old value for at least
the contamination delay and take on its new value in at most the
propagation delay.
• delays for the output rising, tpdr /tcdr, and the output falling, tpdf /tcdf
• Rise/fall times are also sometimes called slopes or edge rates.
Propagation and contamination delay times are also called max-time
and min-time, respectively.
• The gate that charges or discharges a node is called the driver and the
gates and wire being driven are called the load.
• Propagation delay is usually the most relevant value of interest, and is
often simply called delay
•
• The timing analyzer computes the arrival times at each node and
checks that the outputs arrive by their required time.
• The slack is the difference between the required and arrival times.
Positive slack means that the circuit meets timing. Negative slack
means that the circuit is not fast enough.
If the outputs are all required at 200
ps, the circuit has 60 ps of slack.
Timing Optimization
• There will be a number of critical paths that limit the operating speed of the system
and require attention to timing details. The critical paths can be affected at four
main levels:
• The architectural/micro-architectural level
• The logic level
• The circuit level
• The layout level
The most leverage is achieved with a good microarchitecture. This requires a broad
knowledge of both the algorithms that implement the function and the technology
being targeted, such as how many gate delays fit in a clock cycle, how quickly
addition occurs, how fast memories are accessed, and how long signals take to
propagate along a wire.
Trade-offs at the microarchitectural level include the number of pipeline stages, the
number of execution units (parallelism), and the size of memories.
• The next level of timing optimization comes at the logic level.
Trade-offs include types of functional blocks (e.g., ripple carry vs.
lookahead adders), the number of stages of gates in the clock cycle,
and the fan-in and fan-out of the gates.
• Once the logic has been selected, the delay can be tuned at the circuit
level by choosing transistor sizes or using other styles of CMOS logic.
Finally, delay is dependent on the layout.
• The floor plan (either manually or automatically generated) is of great
importance because it determines the wire lengths that can dominate
delay. Good cell layouts can also reduce parasitic capacitance.
• Many RTL designers never venture below the microarchitectural level.
• Timing analyzers are used to check timing closure, i.e., whether the
circuit meets all of the timing constraints.
• This module focuses on the logic and circuit optimizations of selecting
the number of stages of logic, the types of gates, and the transistor
sizes.
RC Delay Model
• RC delay models approximate the nonlinear transistor I-V and C-V characteristics
with an average resistance and capacitance over the switching range of the gate.
This approximation works remarkably well for delay estimation.
Effective Resistance
• The RC delay model treats a transistor as a switch in series with a resistor. The
effective resistance is the ratio of Vds to Ids averaged across the switching interval
of interest.
• A unit nMOS transistor is defined to have effective resistance R. The size of the
unit transistor is arbitrary but conventionally refers to a transistor with minimum
length and minimum contacted diffusion width.
• Alternatively, it may refer to the width of the nMOS transistor in a minimum-sized
inverter in a standard cell library. An nMOS transistor of k times unit width has
resistance R/k because it delivers k times as much current.
• A unit pMOS transistor has greater resistance, generally in the range of 2R–3R,
because of its lower mobility. we will use 2R for examples
• According to the long-channel model, current decreases linearly with
channel length and hence resistance is proportional to L. Moreover, the
resistance of two transistors in series is the sum of the resistances of
each transistor .
• However, if a transistor is fully velocity-saturated, current and
resistance become independent of channel length. Real transistors
operate somewhere between these two extremes.
• This also means that the resistance of transistors in series is somewhat
lower than the sum of the resistances, because series transistors see
smaller Vds and are less velocity-saturated. The effect is more
pronounced for nMOS transistors than pMOS
Gate and Diffusion Capacitance
• Each transistor also has gate and diffusion capacitance. We define C to
be the gate capacitance of a unit transistor of either flavor.
• A transistor of k times unit width has capacitance kC. Diffusion
capacitance depends on the size of the source/drain region.
• Wider transistors have proportionally greater diffusion capacitance.
Increasing channel length increases gate capacitance proportionally
but does not affect diffusion capacitance.
Equivalent RC Circuits
The pMOS transistor has approximately twice the
resistance of the nMOS transistor because holes have
lower mobility than electrons.
The pMOS capacitors are shown with VDD as their
second terminal because the n-well is usually tied high.
Sketch a 3-input NAND gate with transistor widths chosen to achieve effective rise
and fall resistance equal to that of a unit inverter (R). Annotate the gate with its gate
and diffusion capacitances. Assume all diffusion nodes are contacted.
Transient Response
This system is a good model of an inverter sized for equal rise
and fall delays. The system has a transfer function
Elmore Delay
•
Compute the Elmore delay for Vout in the 2nd order RC system
from Figure
Estimate tpd for a unit inverter driving m identical unit inverters.
Figure 4.12 shows an equivalent circuit for the falling transition. Each
load inverter presents 3C units of gate capacitance, for a total of 3mC.
The output node also sees a capacitance of 3C from the drain
diffusions of the driving inverter. This capacitance is called parasitic
because it is an undesired side-effect of the need to make the drain
large enough to contact.
The parasitic capacitance is independent of the load that the inverter is
driving. Hence, the total capacitance is (3 + 3m)C. The resistance is R,
so the Elmore delay is tpd = (3 + 3m)RC. The equivalent circuit for the
rising transition gives the same results.
Repeat above example if the driver is w times unit size.
The driver transistors are w times as wide, so the effective resistance
decreases by a factor of w . The diffusion capacitance increases by a
factor of w. The Elmore delay is
tpd = ((3w + 3m)C)(R/w) = (3 + 3m/w)RC.
Define the fanout of the gate, h, to be the ratio of the load
capacitance to the input capacitance. (Diffusion capacitance is not
counted in the fanout.)
The load capacitance is 3mC. The input capacitance is 3wC. Thus,
the inverter has a fanout of h = m/w and the delay can be written as
(3 + 3h)RC.
If a unit transistor has R = 10 kΩand C = 0.1 fF in a 65 nm process,
compute the delay, in picoseconds, of the inverter in Figure 4.14 with a
fanout of h = 4.
The RC product in the 65 nm process is (10 k
Ω)(0.1 fF) = 1 ps. For h = 4, the delay is (3 + 3h)(1
ps) = 15 ps. This is called the fanout-of-4 (FO4)
inverter delay and is representative of gate delays in
a typical circuit.
Remember that a picosecond is a trillionth of a
second. The inverter can switch about 66 billion
times per second. This stunning speed partially
explains the fantastic capabilities of integrated
circuits.
•
Estimate tpdf and tpdr for the 3-input NAND gate from Example 4.2 if
the output is loaded with h identical NAND gates.
Each NAND gate load presents 5 units of capacitance on a
given input. Figure 4.15(a) shows the equivalent circuit
including the load for the falling transition.
Node n1 has capacitance 3C and resistance of
R/3 to ground.
Node n2 has capacitance 3C and resistance (R/3 + R/3) to
ground.
Node Y has capacitance (9 + 5h)C and resistance (R/3 + R/3 +
R/3) to ground.
The Elmore delay for the falling output is the sum of these RC
products, tpdf = (3C)(R/3) + (3C)(R/3 + R/3) + ((9 + 5h)C)(R/3
+ R/3 + R/3) = (12 + 5h)RC.
• In the worst case, the two inner inputs are 1 and the outer input falls. Y is
pulled up to VDD through a single pMOS transistor
• The ON nMOS transistors contribute parasitic capacitance that slows the
transition. Node Y has capacitance (9 + 5h)C and resistance R to the VDD
supply. Node n2 has capacitance 3C. The relevant resistance is only R, not
(R + R/3), because the output is being charged only through R.
• This is what is meant by the resistance on the shared path from the source
(VDD) to the node (n2) and the leaf (Y).
• Similarly, node n1 has capacitance 3C and resistance R. Hence, the Elmore
delay for the rising output is tpdr = (15 + 5h)RC. The R/3 resistances do not
contribute to thisdelay.
• In all of the Examples, the delay consists of two components. The parasitic
delay is the time for a gate to drive its own internal diffusion capacitance.
Boosting the width of the transistors decreases the resistance but increases
the capacitance so the parasitic delay is ideally independent of the gate size.
• The effort delay depends on the ratio h of external load capacitance to input
capacitance and thus changes with transistor widths. It also depends on the
complexity of the gate. The capacitance ratio is called the fanout or
electrical effort and the term indicating gate complexity is called the logical
effort.
• For example, an inverter has a delay of d = h + 1, so the parasitic delay is 1
and the logical effort is also 1. The NAND3 has a worst case delay of d =
(5/3)h + 5. Thus, it has a parasitic delay of 5 and a logical effort of 5/3.
Layout Dependence of Capacitance
• In a good layout, diffusion nodes are shared wherever possible to
reduce the diffusion capacitance.
• Moreover, the uncontacted diffusion nodes between series transistors
are usually smaller than those that must be contacted. Such
uncontacted nodes have less capacitance
Figure 4.17(a) shows a layout of the 3-input NAND gate.A single drain diffusion region is
shared between two of the pMOS transistors. Estimate the actual diffusion capacitance from
the layout .
Figure 4.17(b) redraws the schematic with these
capacitances lumped to ground.
The output node has the
following diffusion capacitances: 3C from
the nMOS transistor drain, 2C from the
isolated pMOS transistor drain,and 2C
from a pair of pMOS drains that share a
contact.
Thus, the actual diffusion capacitance on
the output is 7C,
• The diffusion capacitance can also be decreased by folding wide
transistors.
• Figure 4.18(a) shows a conventional layout of a 24/12 λ inverter.
Because a unit (4λ) transistor has diffusion capacitance C, the inverter
has a total diffusion capacitance of 9C.
• The folded layout in Figure 4.18(b) constructs each transistor from
two parallel devices of half the width. Observe that the diffusion area
has shrunk by a factor of two, reducing the diffusion capacitance to
4.5C. In general, folded layouts offer lower parasitic delay than
unfolded layouts.
Determining Effective Resistance
• As mentioned the resistance is scaled by a factor of ln 2 so that
propagation delay can be written as an RC product.
• For the step response of a rising input, we are interested in the time for
the output to discharge from VDD to VDD / 2 through an nMOS
transistor.
• If the transistor is sufficiently velocity-saturated that Vdsat < VDD /
2, then the transistor will remain in the saturation region throughout
this transition and the current is roughly constant at Idsat. In such a
case, the effective resistance is
• Channel length modulation and DIBL cause the current to decrease
somewhat with Vds in a real transistor, slightly increasing the effective
resistance.
• More importantly, the input has a nonzero rise time and we are
interested in the time from when the input rises through VDD / 2 until
the output falls through VDD / 2.
• Assume that the input and output slopes are equal and that the output
starts to fall when the input passes through VDD / 2. Then, the output
will reach VDD / 2 when the input reaches VDD
•
Linear Delay Model
• The RC delay model showed that delay is a linear function of the
fanout of a gate. Based on this observation, designers further simplify
delay analysis by characterizing a gate by the slope and y-intercept of
this function.
• In general, the normalized delay of a gate can be expressed in units of
τ as : d = f + p
• p is the parasitic delay inherent to the gate when no load is attached. f
is the effort delay or stage effort that depends on the complexity and
fanout of the gate: f = gh
•
Figure plots normalized delay vs. electrical
effort for an idealized inverter and 3-input
NAND gate.
The y-intercepts indicate the parasitic
delay, i.e., the delay when the gate drives
no load.
The slope of the lines is the logical effort.
The inverter has a slope of 1 by definition.
The NAND has a slope of 5/3.
Logical Effort
• Logical effort of a gate is defined as the ratio of the input capacitance
of the gate to the input capacitance of an inverter that can deliver the
same output current.
• Equivalently, logical effort indicates how much worse a gate is at
producing output current as compared to an inverter, given that each
input of the gate may only present as much input capacitance as the
inverter
Figure shows inverter, 3-input NAND, and 3-input
NOR gates with transistor widths chosen to achieve
unit resistance, assuming pMOS transistors have
twice the resistance of nMOS transistors.
The inverter presents three units of input
capacitance. The NAND presents five units of
capacitance on each input, so the logical effort is
5/3.
Similarly, the NOR presents seven units of
capacitance, so the logical effort is 7/3. This matches
our expectation that NANDs are better than NORs
because NORs have slow pMOS transistors in
series.
Parasitic Delay
• The parasitic delay of a gate is the delay of the gate when it drives
zero load. It can be estimated with RC delay models. A crude method
good for hand calculations is to count only diffusion capacitance on
the output node.
• For example, consider the gates in Figure 4.22, assuming each
transistor on the output node has its own drain diffusion contact.
Transistor widths were chosen to give a resistance of R in each gate.
• The inverter has three units of diffusion capacitance on the output, so
the parasitic delay is 3RC = τ.
• The normalized parasitic delay is 1. In general, we will call the
normalized parasitic delay pinv . pinv is the ratio of diffusion
capacitance to gate capacitance in a particular process.
• It is usually close to 1 and will be considered to be 1 in many
examples for simplicity. The 3-input NAND and NOR each have 9
units of diffusion capacitance on the output, so the parasitic delay is
three times as great (3pinv, or simply 3).
Use the linear delay model to estimate the delay of the fanout-of-4 (FO4)
inverter from Example 4.6. Assume the inverter is constructed in a 65 nm
process with Y = 3 ps.
• The logical effort of the inverter is g = 1, by definition. The electrical
effort is 4 because the load is four gates of equal size.
• The parasitic delay of an inverter is pinv ~ 1.
• The total delay is d = gh + p = 1 × 4 + 1 = 5 in normalized terms, or
tpd = 15 ps in absolute terms.
A ring oscillator is constructed from an odd number of inverters, as
shown in Figure. Estimate the frequency of an N-stage ring oscillator
The logical effort of the inverter is g = 1, by definition. The electrical effort of
each inverter is also 1 because it drives a single identical load. The parasitic
delay is also 1.
The delay of each stage is d = gh + p = 1 × 1 + 1 = 2. An N-stage ring oscillator
has a period of 2N stage delays because a value must propagate twice around the
ring to regain the original polarity. Therefore, the period is T = 2 × 2N.
The frequency is the reciprocal of the period, 1/4N. A 31-stage ring oscillator in
a 65 nm process has a frequency of 1/(4 × 31 × 3 ps) = 2.7 GHz
Logical Effort of Paths
• Designers often need to choose the fastest circuit topology and gate
sizes for a particular logic function and to estimate the delay of the
design.
• The method of Logical Effort [Sutherland99] provides a simple
method “on the back of an envelope” to choose the best topology and
number of stages of logic for a function.
• Based on the linear delay model, it allows the designer to quickly
estimate the best number of stages for a path, the minimum possible
delay for the given topology, and the gate sizes that achieve this delay.
Delay in Multistage Logic Networks
• Figure shows the logical and electrical efforts of each stage in a
multistage path as a function of the sizes of each stage. The path of
interest (the only path in this case) is marked with the dashed blue line.
• Observe that logical effort is independent of size, while electrical
effort depends on sizes.
•
•
Consider a path from the primary input to one of the outputs.
The path logical effort is G = 1 × 1 = 1. The path electrical
effort is H = 90/5 = 18. Thus, GH = 18.
But F = f1 f2 = g1 h1 g2h 2 = 1 × 6 × 1 × 6 = 36. In other
words, F = 2GH in this path on account of the two-way branch.
•
•
•
•
Estimate the minimum delay of the path from A to B in Figure 4.31
and choose transistor sizes to achieve this delay. The initial NAND2
gate may present a load of 8λ of transistor width on the input and
the output load is equivalent to 45 λ of transistor width.
The transistor sizes in Figure 4.32 are chosen to give the desired
amount of input capacitance while achieving equal rise and fall
delays. For example, a 2-input NOR gate should have a 4:1 P/N
ratio. If the total input capacitance is 15, the pMOS width must
be 12 and the nMOS width must be 3 to achieve that ratio.
The NAND2 :d1 = g1h1 + p1 = (4/3) × (10 + 10 + 10)/8 + 2 = 7.
The NAND3: d2 = g2h2 + p2 = (5/3) × (15 + 15)/10 + 3 = 8
NOR2 :d3 = g3h3 + p3 = (5/3) × 45/15 + 2 = 7.
Hence, the path delay is 22
Choosing the Best Number of Stages
• Logical Effort tells us that NANDs are better than NORs and that
gates with few inputs are better than gates with many.
• In this section, Logical Effort is used to predict the best number of
stages to use. Logic designers sometimes estimate delay by counting
the number of stages of logic, assuming each stage has a constant
“gate delay.”
• This is potentially misleading because it implies that the fastest
circuits are those that use the fewest stages of logic. Of course, the
gate delay actually depends on the electrical effort, so sometimes using
fewer stages results in more delay.
A control unit generates a signal from a unit-sized inverter. The signal must drive unit-sized loads in
each bitslice of a 64-bit datapath. The designer can add inverters to buffer the signal to drive the large
load. Assuming polarity of the signal does not matter, what is the best number of inverters to add and
what delay canbe achieved?
•
• In general, you can always add inverters to the end of a path without
changing its function (save possibly for polarity).
• Let us compute how many should be added for least delay