221TEC006 CMOS VLSI
DESIGN
• CO 1 Design Basic CMOS Digital Circuits.
• CO 2 Demonstrate Delay Models, Interconnect, Power Analyses,
I/O and Clocking Issues of CMOS Digital Circuits.
• CO 3 Design Various Types of Static and Dynamic Digital CMOS
Circuits.
• CO 4 Demonstrate the Timing Concepts in Latch and Flip-Flops.
• CO 5 Design CMOS Data Path Subsystems and Memory Arrays.
Module I (7 Hrs)
• Introduction to CMOS technology: MOS Transistor operations (Enhancement and depletion type), Structured Design -Y
Diagram.
• ,StaticCMOS inverter, DC chara, Beta Ratio Effects, Noise Margin- Basics, Pass Transistor DC Characteristics.
• Power analysis: Types of Power Dissipation, On-Chip Power Distribution Network. On- Chip Bypass Capacitance, Power
Network Modelling, Power Supply Filtering, Charge Pumps. Energy Scavenging.
Module II (10 Hrs)
• Delay Models: Introduction, Definitions, Timing Optimization. RC Delay Model: Effective Resistance, Gate and Diffusion
Capacitance, Equivalent RC Circuits, Elmore Delay, Layout Dependence of Capacitance, Determining Effective Resistance. Linear
Delay Model: Logical Effort, Parasitic Delay, Delay in a Logic Gate. Logical Effort of Paths: Delay in Multistage Logic Networks,
Choosing the Best Number of Stages, Example.
• Interconnect: Introduction, Wire Geometry, Interconnect Modelling: Resistance, Capacitance, Inductance (Pi modelling).
Interconnect Impact: Delay, Energy, Crosstalk, Effective Resistance and Elmore Delay.
• Clocks: Clock System Architecture, Global Clock Generation, Global Clock Distribution, Local Clock Gaters, Adaptive Deskewing,
PLLs and DLLs.
• I/O: Basic I/O Pad Circuits, Electrostatic Discharge Protection.
Module III (7 Hrs)
• Combinational Circuit Design: Static CMOS circuits, Combinational logic circuits, Ratioed Circuits. Dynamic logic: Domino Logic,
Dual-Rail Domino Logic, Keepers, Multiple-Output Domino Logic (MODL), NP Domino logic (NORA).
• BiCMOS logic gates: Inverter, NAND, NOR. Introduction to Silicon-On-Insulator Circuit Design
Module IV (8 Hrs)
• Sequential Circuit Design: Sequencing Static Circuits-Flip-flops and latches.
• Sequencing Methods: Max-Delay Constraints, Min-Delay Constraints, Time Borrowing, Clock Skew. Circuit Design of Latches
and Flip-Flops: Conventional CMOS Latches, Conventional CMOS Flip-Flops, True Single-Phase-Clock (TSPC) Latches and
Flip-Flops.
Module V (8 Hrs)
• Data path Subsystems:
• Adders: Single-Bit Addition, Carry-Propagate Addition, Multiple-Input
Addition
• Multipliers: Unsigned Array Multiplication, Booth Encoding.
• Shifters: Funnel Shifter, Barrel Shifter. Comparators: Magnitude
Comparator.
• Counters: Binary Counters.
• Designing of memory and array structures: SRAM, DRAM, and
Embedded DRAM. Read-Only Memory.
• In 1958, Jack Kilby built the first integrated circuit flip-flop with two
transistors at Texas Instruments.
• In 2008, Intel’s Itanium microprocessor contained more than 2 billion
transistors and a 16 Gb Flash memory contained more than 4 billion
transistors.
• This corresponds to a compound annual growth rate of 53% over 50
years.
• No other technology in history has sustained such a high growth rate
lasting for so long.
• As of 2023, the highest transistor count in flash memory is Micron's
2 terabyte (3D-stacked) 16-die, 232-layer V-NAND flash memory chip, with
5.3 trillion floating-gate MOSFETs (3 bits per transistor).
• The highest transistor count in a single chip processor is that of the deep
learning processor Wafer Scale Engine 2 by Cerebras. It has 2.6 trillion
MOSFETs in 84 exposed fields (dies) on a wafer, manufactured using
TSMC's 7 nm FinFET process.
• As of 2023, the GPU with the highest transistor count is AMD's MI300X,
built on TSMC's N5 process and totalling 153 billion MOSFETs.
• The highest transistor count in a consumer microprocessor is 134 billion
transistors, in Apple's ARM-based dual-die M2 Ultra system on a chip,
which is fabricated using TSMC's 5 nm semiconductor manufacturing
process.
Number of
Year Component Name MOSFETs Remarks
(in trillions)
stacked
Micron's V-NAND package of sixteen
2022 Flash memory 5.3
chip 232-layer 3D
NAND dies
wafer-scale design
Wafer Scale
2020 any processor 2.6 of 84 exposed
Engine 2
fields (dies)
2023 GPU MI300X 0.153
dual-die SoC;
microprocessor entire M2 Ultra is
2023 M2 Ultra 0.134
(commercial) a multi-chip
module
Colossus Mk2 An IPU in contrast
2020 DLP 0.059
GC200 to CPU and GPU
MOSFET scaling
(process nodes)
•10 µm – 1971
•6 µm – 1974
•3 µm – 1977
• 1.5 µm – 1981
•1 µm – 1984
•800 nm – 1987
•600 nm – 1990
•350 nm – 1993
•250 nm – 1996
•180 nm – 1999
•130 nm – 2001
•90 nm – 2003
•65 nm – 2005
•45 nm – 2007
•32 nm – 2009
•22 nm – 2012
•14 nm – 2014
•10 nm – 2016
•7 nm – 2018
•5 nm – 2020
•3 nm – 2022
•Future2 nm ~ 2024
List of Top 10 Largest Semiconductor Companies
by and Country
Rank Company Country
1. Intel United States
2. Samsung South Korea
3. TSMC Taiwan
4. SK Hynix South Korea
5. Micron United States
6. Qualcomm United States
7. Broadcom United States
8. Nvidia United States
9. TI United States
10. Infineon Germany
Design Partitioning
• The greatest challenge in modern VLSI design is not in designing the
individual transistors but rather in managing system complexity.
• Modern System-On-Chip (SOC)designs combine memories,
processors, high-speed I/O interfaces, and dedicated
application-specific logic on a single chip.
• They use hundreds of millions or billions of transistors and cost tens
of millions of dollars (or more) to design. The implementation must
be divided among large teams of engineers and each engineer must
be highly productive.
• If the implementation is too rigidly partitioned, each block can be
optimized without regard to its neighbors, leading to poor system
results.
• Conversely, if every task is interdependent with every other task,
design will progress too slowly.
• Design managers face the challenge of choosing a suitable trade-off
between these extremes.
• Design proceeds through multiple levels of abstraction, hiding details
until they become necessary.
• The practice of structured design, which is also used in large software
projects, uses the principles of hierarchy, regularity, modularity, and
locality to manage the complexity.
Design Abstractions
• Digital VLSI design is often partitioned into five levels of abstractions:
architecture design, microarchitecture design, logic design, circuit design,
and physical design.
• Architecture describes the functions of the system. For example, the x86
microprocessor architecturespecifies the instruction set, register set, and
memory model.
• Microarchitecture describes how the architecture is partitioned into
registers and functional units.
• Logic describes how functional units areconstructed. For example, various
logic designs for a 32-bit adder in the x86 integer unitinclude ripple carry,
carry lookahead, and carry select.
• Circuit design describes how transistors are used to implement the
logic. For example, a carry lookahead adder can use static CMOS
circuits, domino circuits, or pass transistors.
• The circuits can be tailored to emphasize high performance or low
power.
• Physical design describes the layout of the chip. Analog and RF VLSI
design involves the same steps but with different layers of
abstraction.
• These elements are inherently interdependent and all influence each
of the design objectives.
• choices of microarchitecture and logic are strongly dependent on the
number of transistors that can be placed on the chip, which depends on the
physical design and process technology.
• Similarly, innovative circuit design that reduces a cache access from two
cycles to one can influence which microarchitecture is most desirable.
• The choice of clock frequency depends on a complex interplay of
microarchitecture and logic, circuit design, and physical design.
• To deal with these interdependencies, microarchitecture, logic, circuit, and
physical design must occur, at least in part, in parallel. Microarchitects
depend on circuit and physical design studies to understand the cost of
proposed micro-architectural features
Structured Design
• Hierarchy is a critical tool for managing complex designs. A large system can
be partitioned hierarchically into multiple cores. Each core is built from
various units.
• Each unit in turn is composed of multiple functional blocks. These blocks in
turn are built from cells, which ultimately are constructed from transistors.
• The system can be more easily understood at the top level by viewing
components as black boxes with well-defined interfaces and functions
rather than looking at each individual transistor.
• Logic, circuit, and physical views of the design should share the same
hierarchy for ease of verification. A design hierarchy can be viewed as a tree
structure with the overall chip as the root and the primitive cells as leafs.
• Regularity aids the management of design complexity by designing
the minimum number of different blocks. Once a block is designed
and verified, it can be reused in many places.
• Modularity requires that the blocks have well-defined interfaces to
avoid unanticipated interactions.
• Locality involves keeping information where it is used, physically and
temporally.
Behavioral, Structural, and Physical Domains
• An alternative way of viewing design partitioning is shown with the
Y-chart. The radial lines on the Y-chart represent three distinct design
domains: behavioral, structural, and physical.
• These domains can be used to describe the design of almost any
artifact. Within each domain there are a number of levels of design
abstraction that start at a very high level and descend eventually to
the individual elements that need to be aggregated to yield the top
level function.
• The behavioral domain describes what a particular system does.
• At each abstraction level, a corresponding structural description can
be developed.
• The structural domain describes the interconnection of modules
necessary to achieve a particular behavior.
• For each level of abstraction, the physical domain description explains how to
physically construct that level of abstraction. At high levels, this might consist of
an engineering drawing showing how to put together the keypad, tone generator
chip, battery, and speaker in the associated housing.
• At the top chip level, this might consist of a floorplan,and at lower levels, the
actual geometry of individual transistors.
• For each level of abstraction, the physical domain description explains how to
physically construct that level of abstraction.
• At high levels, this might consist of an engineering drawing showing how to put
together the keypad, tone generator chip, battery, andspeaker in the associated
housing.
• At the top chip level, this might consist of a floorplan, and at lower levels, the
actual geometry of individual transistors.