Outlines

 About Course
 Brief History and Introduction
 Overview of VLSI design methodology,
 VLSI design flow
 Design hierarchy
 Concept of regularity, Modularity, and Locality
 VLSI design style
 Design quality
 package technology
 introduction to FPGA and CPLD
 computer aided design technology

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 About Course
 Books:
 CMOS Digital Integrated circuits – Analysis and Design by
Sung – Mo Kang,Yusuf Leblebici, TATA McGraw-Hill Pub.
Company Ltd.
 Basic VLSI Design By Pucknell and Eshraghian, PHI,3rd ed.
 Introduction to VLSI Systems by Mead C and Conway,
Addison Wesley
 Introduction to VLSI Circuits & Systems – John P. Uyemura
 Fundamentals of Digital Logic Design with VHDL, Brown
and Vranesic

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 Brief History and Introduction

[Link] of transistor by John Bardeen, William shockely and Walter

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 Brief History and Introduction
 Vacuum tubes ruled in first half of 20th century Large, expensive,
power-hungry, unreliable
 1958: First integrated circuit
 Flip-flop using two transistors
 Built by Jack Kilby at Texas Instruments
 2003
 Intel Pentium 4 mprocessor (55 million transistors)
 512 Mbit DRAM (> 0.5 billion transistors)
 53% compound annual growth rate over 45 years
 No other technology has grown so fast so long
 Driven by miniaturization of transistors
 Smaller is cheaper, faster, lower in power!
 Revolutionary effects on society

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 Brief History and Introduction

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 Brief History and Introduction
 "Moore's law" is the
observation that, over
the history of computing
hardware, the number of
transistors in a dense
integrated circuit has
doubled approximately
every two years.

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 Brief History and Introduction

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 Brief History and Introduction

Figure-1.3: Level of integration over time, for memory chips and logic chips.

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 Overview of VLSI design methodology
 Higher the growth in VLSI technology needs some structured
design methodology for economically viable VLSI products,
in timely manner.
 Logic chips(microprocessors) have more complex design
compare to memory chips. The complexity is also increased
exponentially for logic chips.
 This increase in design cycle time of chips.
 This time is strongly dependent on the efficiency of the
design methodologies as well as on design style.
 As shown in upcoming figure, two different design styles are
compared for their relative merits and demerits.

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 Overview of VLSI design methodology
 Full custom design style( where the geometry and the
placement of every transistor can be optimized individually)
requires a longer time until design maturity can be reached.
But the final product have the higher level of performance.
 In semicustom design style (standard cell based or FPGA)
will allow a shorter design time until design maturity can be
achieved.
 The choice is of design style depends on performance
requirements of theVLSI product.

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 Overview of VLSI design methodology

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 Overview of VLSI design methodology
 Approximately every two years, a new generation of
Technology is introduced.
 This may require that the level of logic integration and chip
performance fall short of the level achievable with the
current processing technology.(see upcoming figure)
 It can be seen that the design cycle time of a successful VLSI
product is kept shorter than what would be necessary for
developing an optimum performance.
 The use of CAD tools methodologies are also essential for
reducing the design cycle time for managing the increasing
design complexity.

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 Overview of VLSI design methodology

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 VLSI design flow
 The Y-chart (first introduced by D. Gajski) shown in Fig. 1.4
illustrates a design flow for most logic chips, using design
activities on three different axes (domains) which resemble
the letter Y.

 The Y-chart consists of three major domains, namely:

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 VLSI design flow

Figure-1.4: Typical VLSI design flow in three domains (Y-chart representation).

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 VLSI design flow
 The design flow starts from the algorithm that describes the
behavior of the target chip.
 The corresponding architecture of the processor is first defined.
 It is mapped onto the chip surface by floorplanning.
 The next design evolution in the behavioral domain defines finite
state machines (FSMs) which are structurally implemented with
functional modules such as registers and arithmetic logic units
(ALUs).
 These modules are then geometrically placed onto the chip surface
using CAD tools for automatic module placement followed by
routing, with a goal of minimizing the interconnects area and
signal delays.

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 VLSI design flow
 The third evolution starts with a behavioral module
description.
 Individual modules are then implemented with leaf cells. At
this stage the chip is described in terms of logic gates (leaf
cells), which can be placed and interconnected by using a cell
placement & routing program.
 The last evolution involves a detailed Boolean description of
leaf cells followed by a transistor level implementation of leaf
cells and mask generation.
 In standard-cell based design, leaf cells are already pre-
designed and stored in a library for logic design use.

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 VLSI design flow
 Figure 1.5 provides a more simplified view of the VLSI design
flow, taking into account the various representations, or
abstractions of design - behavioral, logic, circuit and mask
layout.
 Note that the verification of design plays a very important
role in every step during this process. The failure to properly
verify a design in its early phases typically causes significant
and expensive re-design at a later stage, which ultimately
increases the time-to-market.

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 VLSI design flow
Figure-1.5: A
more simplified
view of VLSI design
flow.

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 VLSI design flow
 Although the design process has been described in linear
fashion for simplicity, in reality there are many iterations
back and forth, especially between any two neighboring
steps, and occasionally even remotely separated pairs.
 In the following, we will examine design methodologies and
structured approaches which have been developed over the
years to deal with both complex hardware and software
projects.
 Some of the classical techniques for reducing the complexity
of IC design are: Hierarchy, regularity, modularity and
locality.

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 Design Hierarchy
 The use of hierarchy, or “divide and conquer” technique
involves dividing a module into sub- modules and then
repeating this operation on the sub-modules until the
complexity of the smaller parts becomes manageable.
 This approach is very similar to the software case where large
programs are split into smaller and smaller sections until
simple subroutines, with well-defined functions and
interfaces, can be written.
 we have seen that the design of a VLSI chip can be
represented in three domains.

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 Design Hierarchy
 Correspondingly, a hierarchy structure can be described in
each domain separately.
 As an example of structural hierarchy, Fig. 1.6 shows the
structural decomposition of a CMOS four-bit adder into its
components. The adder can be decomposed progressively
into one- bit adders, separate carry and sum circuits, and
finally, into individual logic gates.
 At this lower level of the hierarchy, the design of a simple
circuit realizing a well-defined Boolean function is much
more easier to handle than at the higher levels of the
hierarchy.

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 Design Hierarchy

Figure-1.6: Structural decomposition of a four-bit adder circuit, showing the hierarchy down to gate level.

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 Design Hierarchy
 In the physical domain, partitioning a complex system into its
various functional blocks will provide a valuable guidance for the
actual realization of these blocks on chip.
 Obviously, the approximate shape and size (area) of each sub-
module should be estimated in order to provide a useful floorplan.
Figure 1.7 shows the hierarchical decomposition of a four-bit
adder in physical description (geometrical layout) domain,
resulting in a simple floorplan.
 This physical view describes the external geometry of the adder,
the locations of input and output pins, and how pin locations allow
some signals (in this case the carry signals) to be transferred from
one sub-block to the other without external routing.

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 Design Hierarchy
Figure-1.7: Hierarchical
decomposition of a four-bit adder
in physical (geometrical)
description domain.

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 Design Hierarchy
 At lower levels of the physical hierarchy, the internal mask
layout of each adder cell defines the locations and the
connections of each transistor and wire.
 Figure 1.8 shows the full-custom layout of a 16-bit dynamic
CMOS adder, and the sub-modules that describe the lower
levels of its physical hierarchy.
 Here, the 16-bit adder consists of a cascade connection of
four 4-bit adders, and each 4-bit adder can again be
decomposed into its functional blocks such as the Manchester
chain, carry/propagate circuits and the output buffers.

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 Design Hierarchy
Figure-
1.8: Layout of a
16-bit adder, and
the components
(sub-blocks) of its
physical hierarchy.

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 Design Hierarchy
 Finally, Fig. 1.9 show the structural hierarchy and the
physical layout of 16 bit adder.
 Note that there is a corresponding physical description for
every module in the structural hierarchy, i.e., the
components of the physical view closely match this structural
view.

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 Design Hierarchy

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 Concept of regularity, Modularity, and
Locality
 The hierarchical design approach reduces the design complexity
by dividing the large system into several sub-modules.
 Regularity means that the hierarchical decomposition of
a large system should result in not only simple, but also
similar blocks, as much as possible.
 A good example of regularity is the design of array structures
consisting of identical cells - such as a parallel multiplication
array.
 Regularity can exist at all levels of abstraction: At the transistor
level, uniformly sized transistors simplify the design. At the logic
level, identical gate structures can be used, etc.

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 Concept of regularity, Modularity, and
Locality
 Figure 1.11 shows regular circuit-level designs of a 2-1 MUX
(multiplexer), an D-type edge-triggered flip flop, and a one-
bit full adder.
 Note that all of these circuits were designed by using
inverters and tri-state buffers only. If the designer has a small
library of well-defined and well-characterized basic building
blocks, a number of different functions can be constructed by
using this principle.
 Regularity usually reduces the number of different modules
that need to be designed and verified, at all levels of
abstraction.

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Locality

Figure-
1.11: Regular
design of a 2-1
MUX, a DFF and
an adder, using
inverters and tri-
state buffers.

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 Concept of regularity, Modularity, and
Locality
 Modularity in design means that the various
functional blocks which make up the larger system
must have well-defined functions and interfaces.
 Modularity allows that each block or module can be designed
relatively independently from each other, since there is no
ambiguity about the function and the signal interface of these
blocks.
 All of the blocks can be combined with ease at the end of the
design process, to form the large system.

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 Concept of regularity, Modularity, and
Locality
 The concept of modularity enables the parallelization of the
design process. It also allows the use of generic modules in
various designs - the well-defined functionality and signal
interface allow plug-and-play design.
 By defining well-characterized interfaces for each module in
the system, we effectively ensure that the internals of each
module become unimportant to the exterior modules.
 Internal details remain at the local level. The concept of
locality also ensures that connections are mostly between
neighboring modules, avoiding long-distance connections as
much as possible.

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 Concept of regularity, Modularity, and
Locality
 This last point is extremely important for avoiding excessive
interconnect delays. Time-critical operations should be
performed locally, without the need to access distant
modules or signals. If necessary, the replication of some logic
may solve this problem in large system architectures.

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 VLSI design style
 Several design styles can be considered for chip
implementation of specified algorithms or logic functions.
Each design style has its own merits and shortcomings, and
thus a proper choice has to be made by designers in order to
provide the functionality at low cost.
 Fully fabricated FPGA chips containing thousands of logic
gates or even more, with programmable interconnects, are
available to users for their custom hardware programming to
realize desired functionality.
 This design style provides a means for fast prototyping and
also for cost-effective chip design, especially for low-
volume applications.

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 VLSI design style
 A typical field programmable gate array (FPGA) chip consists
of I/O buffers, an array of configurable logic blocks (CLBs),
and programmable interconnect structures.
 The programming of the interconnects is implemented by
programming of RAM cells whose output terminals are
connected to the gates of MOS pass transistors.
 A general architecture of FPGA from XILINX is shown in
Fig. 1.12. A more detailed view showing the locations of
switch matrices used for interconnect routing is given in Fig.
1.13

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Figure-1.12: General architecture of Xilinx FPGAs.

Figure-1.13: Detailed view of switch matrices and interconnection routing between CLBs

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 VLSI design style
 A simple CLB (model XC2000 from XILINX) is shown in
Fig. 1.14. It consists of four signal input terminals (A, B, C,
D), a clock signal terminal, user-programmable
multiplexers, an SR-latch, and a look-up table (LUT).
 The LUT is a digital memory that stores the truth table of
the Boolean function. Thus, it can generate any function of up
to four variables or any two functions of three variables.
 The control terminals of multiplexers are not shown
explicitly in Fig. 1.14.

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 VLSI design style
Figure-
1.14: XC2000 CLB
of the Xilinx
FPGA.

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 VLSI design style
 The CLB is configured such that many different logic
functions can be realized by programming its array. More
sophisticated CLBs have also been introduced to map
complex functions.
 The typical design flow of an FPGA chip starts with the
behavioral description of its functionality, using a hardware
description language such as VHDL.
 The synthesized architecture is then technology-mapped (or
partitioned) into circuits or logic cells. At this stage, the
chip design is completely described in terms of available logic
cells.

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 VLSI design style
 Next, the placement and routing step assigns individual
logic cells to FPGA sites (CLBs) and determines the routing
patterns among the cells in accordance with the netlist.
 After routing is completed, the on-chip performance of the
design can be simulated and verified before downloading
the design for programming of the FPGA chip.
 The programming of the chip remains valid as long as the
chip is powered-on, or until new programming is done. In
most cases, full utilization of the FPGA chip area is not
possible - many cell sites may remain unused.

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 VLSI design style
 The largest advantage of FPGA-based design is the very
short turn-around time, i.e., the time required from the
start of the design process until a functional chip is available.
 Since no physical manufacturing step is necessary for
customizing the FPGA chip, a functional sample can be
obtained almost as soon as the design is mapped into a
specific technology.
 The typical price of FPGA chips are usually higher than
other realization alternatives (such as gate array or standard
cells) of the same design, but for small-volume production of
ASIC chips and for fast prototyping, FPGA offers a very
valuable option.

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 VLSI design style
 While the design implementation of the FPGA chip is done
with user programming, that of the gate array is done
with metal mask design and processing.
 Gate array implementation requires a two-step
manufacturing process: The first phase, which is based on
generic (standard) masks, results in an array of uncommitted
transistors on each GA chip.
 These uncommitted chips can be stored for later
customization, which is completed by defining the metal
interconnects between the transistors of the array (Fig. 1.15).

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Figure-1.15: Basic processing steps required for gate array implementation.

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 Figure 1.17 shows a magnified portion of the internal
array with metal mask design (metal lines highlighted in
dark) to realize a complex logic function.
 Typical gate array platforms allow dedicated areas, called
channels, for intercell routing as shown in Figs. 1.16 and
1.17 between rows or columns of MOS transistors.
 The availability of these routing channels simplifies the
interconnections, even using one metal layer only. The
interconnection patterns to realize basic logic gates can be
stored in a library, which can then be used to customize rows
of uncommitted transistors according to the netlist.

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 VLSI design style
Figure-1.16: A
corner of a typical
gate array chip.

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Figure-1.17: Metal mask
design to realize a complex
logic function on a
channeled GA platform.

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 While most gate array platforms only contain rows of
uncommitted transistors separated by routing channels,
some other platforms also offer dedicated memory (RAM) arrays
to allow a higher density where memory functions are required.
 Figure 1.18 shows the layout views of a conventional gate array
and a gate array platform with two dedicated memory banks.
 With the use of multiple interconnect layers, the routing can be
achieved over the active cell areas; thus, the routing channels
can be removed as in Sea-of-Gates (SOG) chips. Here, the
entire chip surface is covered with uncommitted nMOS and
pMOS transistors.

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Figure-1.18: Layout views of a conventional GA chip and a gate array with two memory banks.

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 As in the gate array case, neighboring transistors can be
customized using a metal mask to form basic logic gates.
For intercell routing, however, some of the uncommitted
transistors must be sacrificed.
 This approach results in more flexibility for
interconnections, and usually in a higher density. The
basic platform of a SOG chip is shown in Fig. 1.19. Figure
1.20 offers a brief comparison between the channeled (GA)
vs. the channelless (SOG) approaches.

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 VLSI design style
Figure-1.19: The
platform of a Sea-of-
Gates (SOG) chip.

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 VLSI design style

Figure-1.20: Comparison between the channeled (GA) vs. the channelless (SOG) approaches.

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 VLSI design style
 In general, the GA chip utilization factor, as measured
by the used chip area divided by the total chip area, is higher
than that of the FPGA and so is the chip speed, since more
customized design can be achieved with metal mask designs.
 The current gate array chips can implement as many as
hundreds of thousands of logic gates.

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 VLSI design style
 The standard-cells based design is one of the most
prevalent full custom design styles which require
development of a full custom mask set
 The standard cell is also called the polycell. In this design
style, all of the commonly used logic cells are developed,
characterized, and stored in a standard cell library.
 A typical library may contain a few hundred cells including
inverters, NAND gates, NOR gates, complex AOI, OAI
gates, D-latches, and flip-flops. Each gate type can have
multiple implementations to provide adequate driving
capability for different fanouts.

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 VLSI design style
 For instance, the inverter gate can have standard size transistors,
double size transistors, and quadruple size transistors so that the
chip designer can choose the proper size to achieve high circuit
speed and layout density. The characterization of each cell is
done for several different categories. It consists of
 delay time vs. load capacitance
 circuit simulation model
 timing simulation model
 fault simulation model
 cell data for place-and-route
 mask data

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 VLSI design style
 To enable automated placement of the cells and routing of inter-
cell connections, each cell layout is designed with a fixed height,
so that a number of cells can be abutted side-by-side to form
rows.
 The power and ground rails typically run parallel to the upper and
lower boundaries of the cell, thus, neighboring cells share a
common power and ground bus.
 The input and output pins are located on the upper and lower
boundaries of the cell. Figure 1.21 shows the layout of a typical
standard cell.
 Notice that the nMOS transistors are located closer to the ground
rail while the pMOS transistors are placed closer to the power
rail.

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Figure-1.21: A standard cell layout example.

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 VLSI design style
 Figure 1.22 shows a floorplan for standard-cell based design.
Inside the I/O frame which is reserved for I/O cells, the chip area
contains rows or columns of standard cells.
 Between cell rows are channels for dedicated inter-cell routing. As
in the case of Sea-of-Gates, with over-the- cell routing, the
channel areas can be reduced or even removed provided that the
cell rows offer sufficient routing space.
 The physical design and layout of logic cells ensure that when cells
are placed into rows, their heights are matched and neighboring
cells can be abutted side-by-side, which provides natural
connections for power and ground lines in each row.
 The signal delay, noise margins, and power consumption
of each cell should be also optimized with proper sizing of
transistors using circuit simulation.

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Figure-1.22: A simplified floorplan of standard-cells-based design.

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 If a number of cells must share the same input and/or output
signals, a common signal bus structure can also be
incorporated into the standard-cell-based chip layout. Figure
1.23 shows the simplified symbolic view of a case where a
signal bus has been inserted between the rows of standard
cells.
 Note that in this case the chip consists of two blocks, and
power/ground routing must be provided from both sides of
the layout area. Standard-cell based designs may consist of
several such macro-blocks, each corresponding to a specific
unit of the system architecture such as ALU, control logic,
etc.

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 VLSI design style
Figure-1.23: Simplified
floorplan consisting of two
separate blocks and a
common signal bus.

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 After chip logic design is done using standard cells in the
library, the most challenging task is to place individual
cells into rows and interconnect them in a way that meets
stringent design goals in circuit speed, chip area, and power
consumption.
 Many advanced CAD tools for place-and-route have been
developed and used to achieve such goals.
 Also from the chip layout, circuit models which include
interconnect parasitics can be extracted and used for timing
simulation and analysis to identify timing critical paths.

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 VLSI design style
 For timing critical paths, proper gate sizing is often practiced
to meet the timing requirements.
 In many VLSI chips, such as microprocessors and digital
signal processing chips, standard-cells based design is used to
implement complex control logic modules. Some full
custom chips can be also implemented exclusively
with standard cells.
 Finally, Fig. 1.24 shows the detailed mask layout of a
standard-cell-based chip with an uninterrupted single block
of cell rows, and three memory banks placed on one side of
the chip.

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Figure-1.24: Mask
layout of a standard-
cell-based chip with a
single block of cells
and three memory
banks.

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 VLSI design style
 Notice that within the cell block, the separations between
neighboring rows depend on the number of wires in the
routing channel between the cell rows.
 If a high interconnect density can be achieved in the
routing channel, the standard cell rows can be placed closer
to each other, resulting in a smaller chip area.
 The availability of dedicated memory blocks also reduces the
area, since the realization of memory elements using standard
cells would occupy a larger area.

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 VLSI design style
 Although the standard-cells based design is often called full
custom design, in a strict sense, it is somewhat less than
fully custom since the cells are pre-designed for general use
and the same cells are utilized in many different chip designs.
 In a fuller custom design, the entire mask design is done
anew without use of any library. However, the development
cost of such a design style is becoming prohibitively high.
Thus, the concept of design reuse is becoming popular in
order to reduce design cycle time and development cost.
 The most rigorous full custom design can be the design of a
memory cell, be it static or dynamic.

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 VLSI design style
 Since the same layout design is replicated, there would not be
any alternative to high density memory chip design. For logic
chip design, a good compromise can be achieved by using a
combination of different design styles on the same
chip, such as standard cells, data-path cells and PLAs.
 In real full-custom layout in which the geometry,
orientation and placement of every transistor is done
individually by the designer, design productivity is usually
very low - typically 10 to 20 transistors per day, per
designer.

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 VLSI design style
 In digital CMOS VLSI, full-custom design is rarely used due
to the high labor cost. Exceptions to this include the
design of high-volume products such as memory chips, high-
performance microprocessors and FPGA masters.
 Figure 1.25 shows the full layout of the Intel 486
microprocessor chip, which is a good example of a hybrid
full-custom design.
 Here, one can identify four different design styles on one
chip: Memory banks (RAM cache), data-path units consisting
of bit-slice cells, control circuitry mainly consisting of
standard cells and PLA blocks.

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 VLSI design style
Figure-1.25: Mask layout
of the Intel 486
microprocessor chip, as an
example of full-custom
design.

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 Design quality
 It is desirable to measure the quality of design in order to
improve the chip design.
 There are no universal rules for design quality but following
criteria are considered to be important.
 Testability
 Yield and manufacturability
 Reliability
 Technology updateability

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 Design quality
 Testability
 Developed chips are eventually inserted into PCBs or
multichip modules for system applications.
 Fabricated chips should be fully testable to ensure that all the
chips passing the specified chip test can be inserted into the
system, either in packaged or in bare die form, without
causing failures. Such a goal requires.
 Generation of good test vectors.
 Availability of reliable test fixture at speed
 Design of testable chip

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 Design quality
 In fact, some chip projects had to be abandoned after chip
fabrication because of inadequate testability of the design. As
the complexity of the chips increases with the increasing
level of monolithic integration, additional circuitry for self
testing has to be included to ensure that the fabricated chips
can be fully tested.
 This translates into an increase in chip area and some speed
penalty, but such a trade off will became unavoidable in VLSI
design.

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 Design quality
 Yield and Manufacturability
 The most strict definition of the yield can be the number of
good tested chips divided by the total number of chip sites
available at the start of the wafer processing.
 On the other hand poor chip design can cause processing
problems and, therefore, drop outs during the processing.
The chip yield can be further divided into the following
subcategories.
 Functional yield
 Parametric yield

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 Design quality
 The functional yield is obtained by testing the functionality of
the chip at a speed usually lower than the required chip
speed.
 The functional test weed out the problems of short, open,
and leakage current, and can detect logic and circuit design
faults.
 The parametric test is usually performed at the required
speed on chips that passed the functional test. All the delay
testing is performed at this stage.

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 Design quality
 Reliability
 The reliability of the chip depends on the design and process
conditions. The major causes for chip reliability problems can be
characterized into the following.
1. Electrostatic Discharge(ESD) and electrical overstress(EOS)
2. Electromigration
3. Latch up in CMOS I/O and internal circuits.
4. Hot carrier induced aging
5. Oxide breakdown
6. Single event upset
7. Power and ground bouncing
8. On chip noise and crosstalk

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 Design quality
 Technology Updateability
 Process technology development has progressed rapidly and
as a result, the lifespan of a given technology generation has
remained almost constant even for submicron technologies.
 Yet, the time pressure to develop increasingly more complex
chips in a shorter time is constantly increasing.
 Under such circumstances, the chip products often have to be
technology updated to new design rules.
 Designers can develop advance CAD tools to overcome the
issues.

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 Package technology
 Novice designers often fail to give enough consideration to
the packaging technology, especially in the early stages of
chip development.
 However, many high performance VLSI chips can fail
stringent test specifications after packaging if chip designers
have not included various effects of packaging constraints and
parasitic in their design.
 Good packages should provide low thermal resistance and
,hence , limited temperature increase beyond the ambient
temperature due to power dissipation.

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 Package technology
 Some of the important packaging concerns are
1. Harmonic seals to prevent the penetration of moisture
2. Thermal conductivity
3. Thermal expansion coefficient.
4. Pin Density
5. Parasitic inductance and capacitance
6. Alpha-Particle protection
 PHT(pin through hole)
 SMT(Surface mount Technology)

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 Package technology
 some common IC package types are:
 Dual In Line Packages(DIP). This PTH package has been the
most dominant IC package type for more than 20 years.
 DIP has and advantage of low cost but their dimensions can
be prohibitive, especially for small, portable products.
 Pin Grid Array(PGA) Packages: This PTH package type offers
a higher in count and higher thermal conductivity.
 The PGA packages requires large PCB area, and the package
cost is higher than DIP, specially for ceramic PGAs.

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 Package technology
 Chip Carrier Packages(CCP). This SMT package type is
available in two variations, the leadless chip carrier and the
leaded chip carrier.
 The leadless chip carrier is designed to be mounted directly
on the PCB, and it can support a high pin count.
 The main drawback is the inherent difference in the thermal
coefficients between the chip carrier and the PCB.
 The leaded chip carrier package solves this problem since the
added leads can accommodate small dimension variations
caused by the differences in thermal coefficients.

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 Package technology
 Quad Flat Packs(QFP)
 This SMT package type is similar to leaded chip carrier
packages, except that the leads extend outward rather than
being bent under the package body. Ceramic and plastic QFP
with very high pin counts (up to 500) are becoming popular
package types in recent years.
 Multi Chip Modules(MCM) : This IC packages option can be
used for special application requiring very high performance,
where multiple chips are assembled on a common substrate
combined in a single package.

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 Introduction to FPGA and CPLD
 The introduction of FPGA is as shown in VLSI design style topic.
Here we are going to see the introduction of CPLD where we are
going to see the comparison to each technology .
 Ideally, though, the hardware designer wanted something that gave
him or her the flexibility and complexity of an ASIC but with the
shorter turn-around time of a programmable device.
 The solution came in the form of two new devices - the Complex
Programmable Logic Device (CPLD) and the Field Programmable
Gate Array. As can be seen in Figure 1.26 , CPLDs and FPGAs
bridge the gap between PALs and Gate Arrays.
 CPLDs are as fast as PALs but more complex. FPGAs approach the
complexity of Gate Arrays but are still programmable.

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 Introduction to FPGA and CPLD

Figure 1.26 Comparison of CPLDs and FPGAs

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 Introduction to FPGA and CPLD
 CPLD Architectures
 The diagram in Figure 1.27 shows the internal architecture
of a typical CPLD.
 While each manufacturer has a different variation, in general
they are all similar in that they consist of function blocks,
input/output block, and an interconnect matrix.
 The devices are programmed using programmable elements
that, depending on the technology of the manufacturer, can
be EPROM cells, EEPROM cells, or Flash EPROM cells.

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 Introduction to FPGA and CPLD

Figure 1.28 CPLD Architecture

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 Introduction to FPGA and CPLD
 A typical function block is shown in Figure 1.28. The AND
plane still exists as shown by the crossing wires.
 The AND plane can accept inputs from the I/O blocks, other
function blocks, or feedback from the same function block.
 The terms and then ORed together using a fixed number of
OR gates, and terms are selected via a large multiplexer.
 The outputs of the mux can then be sent straight out of the
block, or through a clocked flip-flop.
 This particular block includes additional logic such as a
selectable exclusive OR and a master reset signal, in addition
to being able to program the polarity at different stages.

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 Introduction to FPGA and CPLD

Figure .1.28 CPLD Function Block

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 Introduction to FPGA and CPLD
 Figure 1.29 shows a typical I/O block of a CPLD. The I/O block
is used to drive signals to the pins of the CPLD device at the
appropriate voltage levels with the appropriate current.
 Usually, a flip-flop is included, as shown in the figure. This is done
on outputs so that clocked signals can be output directly to the
pins without encountering significant delay.
 It is done for inputs so that there is not much delay on a signal
before reaching a flip-flop which would increase the device hold
time requirement.
 Also, some small amount of logic is included in the I/O block
simply to add some more resources to the device.

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 Introduction to FPGA and CPLD

Figure 1.29 CPLD Input/Output Block

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 Introduction to FPGA and CPLD
 Interconnect
 The CPLD interconnect is a very large programmable switch
matrix that allows signals from all parts of the device go to all
other parts of the device.
 While no switch can connect all internal function blocks to
all other function blocks, there is enough flexibility to allow
many combinations of connections.
 Programmable Elements
 Different manufacturers use different technologies to
implement the programmable elements of a CPLD.

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 Introduction to FPGA and CPLD
 The common technologies are Electrically Programmable
Read Only Memory (EPROM), Electrically Erasable PROM
(EEPROM) and Flash EPROM.
 These technologies are similar to, or next generation
versions of, the technologies that were used for the simplest
programmable devices, PROMs.

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 Computer Aided Design Technology
 CAD tools are essential for timely development of integrated
circuits.
 Although CAD tools can not replace the creative and
inventive parts of the design activities, the majority of time
consuming and computation intensive mechanistic parts of
the design can be executed by using CAD tools.
 The CAD technology can be categorized into the following
area:
 High level synthesis
 Logic synthesis

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 Computer Aided Design Technology
 Circuit optimization
 Layout
 Simulation
 Design rules checking
 FormalVerification

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 Computer Aided Design Technology
 Synthesis Tools
 The high level synthesis tools using hardware description
language(HDLs), such as VHDL or Verilog, address the
automation of the design phase in the top level of the design
hierarchy.
 Layout Tools
 The tools for circuit optimization are concerned with
transistor sizing for minimization of delays and with process
variations, noise, and reliability hazards. The Layout CAD
tools include floor planning, place and route, and module
generation.

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 Computer Aided Design Technology
 Simulation and Verification Tools.
 The simulation category, which is the most mature area of
VLSI CAD, includes many tools ranging from circuit level
simulation, timing level simulation, logic level simulation,
and behavioral simulation.

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 Outcomes
 From this topic, we come to know about the VLSI designing
methods, the flow of design, the concept of design and
certain set of rules to get proper design of VLSI chip
manufacturing. We also come to know the various packaging
technologies for ICs and also Computer aided tools which
are essential for theVLSI product design.

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 References
 Book: CMOS Digital Integrated Circuit Design - Analysis and
Design by S.M. Kang andY. Leblebici.
 PPT- Introduction to CMOSVLSI design by Shmuel and [Link]
 [Link]

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 THANK YOU

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