1. What is an Instruction Code?

Definition:
An instruction code is a binary pattern that represents a specific operation (like add, move, or
jump) and the operands (data or memory locations) on which the operation is to be performed.

In simple terms:

Instruction Code = What to do + With what data

��Example in Computer Terms

Example Meaning
0001 0010 0011 Might mean ADD R2, R3 (add contents of register R3 to R2)

Here:

 0001 = Operation Code (Opcode) for ADD

 0010 = Register 2 (Destination)
 0011 = Register 3 (Source)

�‍♂�Real-Life Analogy

Imagine a chef in a kitchen:

 The opcode is the instruction type (e.g., "Chop", "Fry", "Boil")

 The operands are the ingredients or tools (e.g., "Onion", "Pan", "Oil")

So a full instruction might be:

"Chop Onion" → Opcode = Chop, Operand = Onion

��2. Components of an Instruction

Each instruction generally consists of two parts:

Part Description Example

Opcode (Operation Code) Specifies the operation to perform ADD, MOV, SUB
 Part Description Example
Operand(s) Data, address, or register involved Register R1, Memory [2000H]

�Diagram: Instruction Format

|-----------|-----------|-----------|
| OPCODE | OPERAND 1 | OPERAND 2 |
|-----------|-----------|-----------|
4 bits 4 bits 4 bits

� 3. Types of Instruction Codes

Different architectures organize instructions differently depending on how operands are
specified.

Type Description Example Real-life Analogy

Register Use ingredients already on the
Operands are in registers ADD R1, R2
Reference counter
Memory
Operands are in memory LOAD A, 2000H Fetch an ingredient from the fridge
Reference
Operand is directly in MOV R1, #5
You already have ―5 grams of salt‖
Immediate
instruction written in the recipe
Communicates with I/O IN PORT1, OUT Talk to a waiter to bring or send
Input-Output PORT2
devices food

� 4. Example of a Simple Instruction Set

Mnemonic Opcode (binary) Description
AND 0000 Logical AND of AC with operand
ADD 0001 Add operand to accumulator
LDA 0010 Load accumulator with memory
STA 0011 Store accumulator into memory
BUN 0100 Branch unconditionally
HLT 1111 Halt the computer

� 5. Example: Executing an Instruction

Instruction:
ADD 2000H

Step-by-Step Execution:

1. Fetch: Control unit fetches the instruction from memory.

2. Decode: It decodes that ADD means addition.
3. Fetch Operand: Gets data from memory location 2000H.
4. Execute: Adds the data to the Accumulator (AC).
5. Store Result: Result stays in AC or memory.

�Diagram: Instruction Cycle

+--------------------+
| Fetch Cycle |
+--------------------+
↓
+--------------------+
| Decode Cycle |
+--------------------+
↓
+--------------------+
| Execute Cycle |
+--------------------+
↓
+--------------------+
| (Next Instruction)|
+--------------------+

� 6. Real-Life Example of Instruction Execution

Imagine a chef executing ―Chop Onion‖:

1. Fetch: Read recipe (instruction).

2. Decode: Understand action (Chop).
3. Fetch Operand: Take Onion from table.
4. Execute: Chop Onion.
5. Next: Move to next recipe line.
1. What is an Operation Code (Opcode)?
Definition:

The Operation Code (Opcode) is the part of an instruction code that specifies which operation
is to be performed by the computer.

In simple words:

Opcode tells the CPU what to do — whether to add, subtract, move data, jump, etc.

�Example in Computer Terms

Instruction Opcode Meaning

ADD R1, R2 ADD Add contents of R2 to R1
MOV A, B MOV Move contents of B into A
SUB X, Y SUB Subtract Y from X

So here, ADD, MOV, and SUB are operation codes.

�‍♂�Real-Life Analogy

Imagine a chef following a recipe:

Part Example Meaning

Opcode ―Chop‖ What action to perform
Operand ―Onion‖ On what item to perform it

So the instruction “Chop‍Onion” corresponds to:

 Opcode → Chop
 Operand → Onion

�� The chef = CPU

Recipe step = Instruction
Cooking action (Chop) = Opcode
��2. Role of Opcode in the Instruction Cycle
When the CPU executes an instruction:

1. Fetch: The CPU reads the instruction from memory.

2. Decode: The control unit interprets the opcode part to know what operation to perform.
3. Execute: The operation is carried out using operands.

�The opcode directly controls the operation performed by ALU or control unit.

�Diagram: Instruction Format Showing Opcode

|------------|----------------------|
| OPCODE | OPERAND(S) |
|------------|----------------------|
| (4 bits) | (8 bits) |

Example:
0001 0010 0011

 0001 → Opcode for ADD

 0010 → Operand (R2)
 0011 → Operand (R3)

� 3. Types of Operation Codes

There are different ways to classify opcodes depending on how they interact with operands or
how many bits they use.

1�⃣ Single Address Opcode

 Only one operand is specified.

 The other operand is assumed to be in the Accumulator (AC).

�Example:

ADD 2000H

→ Add contents of memory location 2000H to the Accumulator.

�Real-life analogy:

―Add sugar (from the shelf) to what’s already in the bowl.‖

2�⃣ Two Address Opcode

 Two operands are specified.

�Example:

MOV R1, R2

→ Move contents of R2 into R1.

�Analogy:

―Pour water (R2) into the kettle (R1).‖

3�⃣ Three Address Opcode

 Three operands are given — two sources and one destination.

�Example:

ADD R1, R2, R3

→ Add R2 and R3, store result in R1.

�Analogy:

―Mix sugar and flour into the bowl.‖

4�⃣ Zero Address Opcode

 Used in Stack-based or Accumulator-based systems.

 Operands are implicit (already on top of the stack).

�Example:

ADD
→ Add top two values from the stack.

�Analogy:

―Mix the top two ingredients already in the bowl.‖

� 4. Length of Opcode (Opcode Size)

 The number of bits in the opcode determines how many operations a computer can
perform.

Opcode Bits Possible Operations

2 bits 4 operations
3 bits 8 operations
4 bits 16 operations
8 bits 256 operations

�Example:
If the opcode field has 4 bits → 24=162^4 = 1624=16 possible operations.

�Analogy:

More ―words‖ in your cooking vocabulary = more actions you can perform (chop, fry, bake, mix,
etc.)

�Diagram: Relation Between Opcode Bits and Instruction Variety

Opcode bits ───────────────▶ Number of possible instructions
2 bits (4 ops)
3 bits (8 ops)
4 bits (16 ops)
8 bits (256 ops)

� 5. Example: How Opcode Works in Instruction Execution

Instruction:
ADD R1, R2

Step-by-Step:
 1. Fetch: CPU gets the binary code for the instruction.
e.g., 0001 0010 0011
2. Decode: Control Unit identifies 0001 → ADD operation.
3. Execute: ALU performs addition between R1 and R2.
4. Store Result: Result placed in R1 or AC.

��Diagram: Opcode in Instruction Execution

+-------------------+
| Memory (RAM) |
+---------+---------+
|
v
+---------------+
| Control Unit |
+-------+-------+
|
Decodes Opcode ---> ALU performs operation
1. What is Time and Control?
Definition:

The Time and Control Unit in a computer is responsible for generating the timing signals and
control signals that coordinate and manage all operations of the computer.

It tells when and what each component (like memory, ALU, registers, etc.) should do.

�Example in Simple Terms:

When a CPU executes an instruction like:

ADD R1, R2

 The control unit decides what operations must happen (fetch, decode, execute).
 The timing signals decide when each operation happens (T₀, T₁, T₂…).

�‍♂�Real-Life Analogy:

Imagine an orchestra �

 The conductor = Control Unit

 The musicians = CPU components (ALU, registers, memory, etc.)
 The beat/timing = Clock pulses

The conductor (Control Unit) signals which musician plays and when to play (timing).

Without the conductor, everyone would play at random — chaos!

��2. Role of Time and Control in CPU Operation

When executing an instruction, the CPU follows three main phases:

1. Fetch – Get instruction from memory

2. Decode – Interpret instruction
3. Execute – Perform the operation
Each phase is divided into time steps (T₀, T₁, T₂ …), controlled by the Timing Unit.
The Control Unit then issues the necessary control signals at each time step.

� 3. Components of Time and Control Unit

Component Function Example
Clock Generator Provides a regular timing pulse System clock (oscillator)
Sequence Counter
Counts clock pulses to track time steps Generates T₀, T₁, T₂...
(SC)
Converts SC output into individual timing Activates one Ti signal at a
Decoder
signals time
Control Logic Combine timing and instruction signals to e.g., D₃T₂ triggers an ADD
Gates form control commands micro-operation

�Diagram: Basic Timing and Control Unit

+--------------------+
| CLOCK |
+--------+-----------+
|
v
+--------------------+
| SEQUENCE COUNTER | → Binary count (000, 001, 010...)
+--------+-----------+
|
v
+--------------------+
| DECODER | → Generates T0, T1, T2, T3...
+--------+-----------+
|
v
+--------------------+
| CONTROL LOGIC UNIT | → Combines T and D signals to form control
outputs
+--------------------+

� 4. Timing Signals
Timing signals define when micro-operations occur.

Signal Meaning Example Micro-Operation

T₀ Start of instruction cycle Fetch instruction
T₁ Next step Decode instruction
Signal Meaning Example Micro-Operation
T₂ Next Execute or fetch operand
T₃ Next Write back result
T₄ End of instruction Reset sequence counter (SC → 0)

�Timing Cycle Diagram

Clock: ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐
│ │ │ │ │ │ │ │ │ │ │ │
└─┘ └─┘ └─┘ └─┘ └─┘ └─┘
T0: ──────■■■■───────────────────
T1: ──────■■■■────────────
T2: ──────■■■■─────
T3: ──────■■
T4: ■■

Each T signal is active for one clock period.

� 5. Control Signals
Control signals define what operations occur — they direct the movement of data and control
the ALU, registers, and buses.

Control Signal Function Example

PCout Send Program Counter contents to bus During instruction fetch
MARin Load Memory Address Register Select memory address
Read Enable memory read Fetch instruction
IRin Load Instruction Register Store fetched instruction
Add ALU perform addition During execution
SC ← 0 Reset sequence counter End of instruction

These signals are generated by combining timing signals (Ti) and decoded instruction signals
(Di).

Example:

For an ADD instruction (D₃):

 D₃T₂ might trigger reading the operand.

 D₃T₃ might trigger ALU addition.
� 6. How Time and Control Work Together
Step Timing Signal Control Signal Function
1 T₀ PCout, MARin, Read Fetch instruction
2 T₁ IRin, PC increment Decode instruction
3 T₂ D₃T₂ → operand fetch Execution preparation
4 T₃ D₃T₃ → ALU Add Execution
5 T₄ SC ← 0 Reset for next instruction

� 7. Real-Life Analogy (Cooking Example)

Stage Timing (T) Control Signal Action
T₀ ―Read recipe‖ Fetch recipe Get instructions
T₁ ―Understand step‖ Decode Identify ingredients
T₂ ―Collect ingredients‖ Operand fetch Gather ingredients
T₃ ―Cook food‖ Execute Perform operation
T₄ ―Serve food‖ Write back Finish and reset for next dish

� The chef’stiming = Clock + SC + Ti

�� The chef’s decisions (what to do) = Control logic

� 8. Summary Table
Concept Meaning Function
Clock Provides timing pulses Synchronizes all actions
Sequence Counter (SC) Counts time steps Determines Ti signals
Decoder Converts SC output to Ti One Ti active per clock cycle
Timing Signals (Ti) Define phases of instruction cycle Fetch, Decode, Execute
Control Logic Generates control signals Controls micro-operations
Control Signals Direct CPU operations Move, Load, Add, etc.

�‍9.‍Key‍Takeaways
 Timing = When each operation happens.
 Control = What operation happens.
 Together, they ensure synchronous, orderly execution of every instruction.
 Implemented using clock pulses, counters, and decoders.
 Real-life analogy: An orchestra or a chef following a recipe with precise timing and
actions.
1. What is the Instruction Cycle?
Definition:

The Instruction Cycle (also called the fetch–decode–execute cycle) is the sequence of
operations a computer performs to fetch, decode, and execute each instruction in a program.

Every single instruction — whether it’s ADD, MOV, or JUMP — goes through this cycle.

�Simple Explanation:

Think of the CPU as a chef following a recipe:

 Fetch → Read the next recipe step.

 Decode → Understand what the step means.
 Execute → Perform the step (chop, boil, mix, etc.).

After finishing one step, the chef moves to the next — just like the CPU moves to the next
instruction.

��2. Major Phases of the Instruction Cycle

The instruction cycle can be divided into four main phases:

Phase Description Example

1. Fetch Cycle Get the instruction from memory Fetch ADD R1, R2
Understand it means add R2 to
2. Decode Cycle Decode the fetched instruction
R1
3. Execute Cycle Perform the operation ALU adds R2 and R1
4. Interrupt Cycle Handle any external/internal Pause to process input/output
(optional) interrupts request

� 3. Detailed Steps of Each Cycle

�1. Fetch Cycle

Purpose: Bring the instruction from memory into the CPU.

Micro-operations:

1. PC → MAR (Program Counter → Memory Address Register)

2. Read memory (M[MAR] → MDR)
3. MDR → IR (Memory Data Register → Instruction Register)
4. PC ← PC + 1 (Increment Program Counter)

�Diagram:

[PC] → [MAR] → [Memory] → [MDR] → [IR]

↑
(Read)

Analogy:
Like reading the next line of a recipe — "Step 3: Add 2 cups of flour."

�2. Decode Cycle

Purpose: Understand what operation is requested.

Micro-operations:

1. IR(opcode) → Control Unit

2. Control Unit decodes opcode
3. Determine operation type and operands

Analogy:
The chef reads "Add 2 cups of flour" and understands:

 Action = Add (Opcode)

 Ingredient = Flour (Operand)

�3. Execute Cycle

Purpose: Perform the actual task specified by the instruction.

Micro-operations (example for ADD):

1. R1 + R2 → R1

For different instructions:

Instruction Operation
Instruction Operation
ADD R1, R2 Add R2 to R1
MOV A, B Copy B into A
JMP X Jump to address X

Analogy:
The chef performs the action — actually adds flour to the bowl.

�4. Interrupt Cycle (optional)

Purpose: Handle special situations (I/O request, errors, etc.)

Micro-operations:

1. Save PC and CPU state

2. Load interrupt service routine (ISR) address
3. Execute ISR
4. Return to saved program

Analogy:
If someone rings the doorbell while the chef is cooking, the chef pauses, answers the door
(interrupt), then resumes cooking.

� 4. Diagram: Instruction Cycle Flow

+----------------------+
| FETCH INSTRUCTION |
+----------------------+
↓
+----------------------+
| DECODE INSTRUCTION |
+----------------------+
↓
+----------------------+
| EXECUTE INSTRUCTION |
+----------------------+
↓
+----------------------+
| CHECK INTERRUPT |
+----------------------+
↓
+----------------------+
| FETCH NEXT INSTRUCTION |
+----------------------+
� 5. Timing Diagram (Simplified)
Each phase occurs during specific timing‍signals‍(T₀–T₄), controlled by the control unit:

Timing Operation
T₀ Fetch instruction (PC → MAR, Read)
T₁ Load instruction (MDR → IR, PC+1)
T₂ Decode instruction
T₃ Execute operation
T₄ Check for interrupt, reset sequence counter

Visualization:

Clock: ┌─┐ ┌─┐ ┌─┐ ┌─┐ ┌─┐

│ │ │ │ │ │ │ │ │ │
└─┘ └─┘ └─┘ └─┘ └─┘
T0: ──────■■■■───────────────
T1: ──────■■■■────────
T2: ──────■■■■─
T3: ──────■■
T4: ■■

� 6. Example: Executing an ADD Instruction

Instruction:
ADD R1, R2

Step-by-Step:

Phase Micro-Operations Description

Fetch PC→MAR; Read; MDR→IR; PC+1 Get ADD R1,R2 from memory
Decode Decode opcode in IR Identify operation = ADD
Execute R1 + R2 → R1 Perform addition
Interrupt (if any) Handle I/O or external event Optional

�‍♂�Real-Life Analogy

CPU Stage Chef’s‍Action Example

Fetch Read next recipe line ―Step 3: Add 2 cups of flour.‖
Decode Understand what to do Realizes ―add flour‖ means mix it in
CPU Stage Chef’s‍Action Example
Execute Perform the step Actually adds and stirs flour
Interrupt Pause for an event Doorbell rings, answers, then continues

� 7. Summary Table
Phase Purpose Hardware Involved Real-Life Analogy
Fetch Bring instruction from memory PC, MAR, MDR, IR Read recipe step
Decode Interpret instruction Control Unit Understand step
Execute Perform the action ALU, Registers Perform step
Interrupt Handle external events Interrupt logic Pause for doorbell

� 8. Complete Block Diagram: CPU Operation

+----------------+
| Program |
| Counter (PC) |
+--------+-------+
|
v
+----------------+
| Memory Address |
| Register (MAR) |
+--------+-------+
|
v
+----------------+
| Memory |
+--------+-------+
|
v
+----------------+
| Memory Data |
| Register (MDR) |
+--------+-------+
|
v
+----------------+
| Instruction |
| Register (IR) |
+--------+-------+
|
v
+----------------+
| Control Unit |
+--------+-------+
|
v
 +----------------+
| ALU + Regs |
+----------------+

�‍9.‍Key‍Takeaways
 The instruction cycle is the CPU’s heartbeat — it defines how the CPU executes
programs.
 It consists of:
o Fetch → Get instruction
o Decode → Understand instruction
o Execute → Perform action
o Interrupt → Handle special conditions
 Controlled by timing‍and‍control‍signals‍(T₀–T₄) from the control unit.
 Real-life analogy: like a chef following a recipe step by step.