FPGA-Based Accelerator for IoT
Data Compression
Minor Project Progress Report
Submitted in partial fulfilment of the requirements for the award of the
degree of
Bachelor of Technology in Electronics and
Communication Engineering
Nimesh Hoon Supervisor:
[Link] ECE — 7th Sem Dr. Shiv Ram Meena
Roll No.: 01816412822 Asst. Prof.
University School of Information, Communication and
Technology
Guru Gobind Singh Indraprastha University
2026
Contents
1 Introduction 2
2 Problem Statement and Objectives 2
3 Work Done 3
3.1 Literature Survey . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3.2 Methodology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2.1 Huffman Coding . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2.2 LZ77 Compression . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.2.3 Register Transfer Level (RTL) Implementation . . . . . . . . . . . 5
3.2.4 Hybrid LZ77–Huffman Approach . . . . . . . . . . . . . . . . . . 5
3.3 Performance Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3.1 Compression Ratio . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3.2 Throughput . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3.3 Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3.4 Memory Utilization . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3.3.5 Energy Per Bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.4 Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4 Work Needed to Be Done 8
5 References 9
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1 Introduction
The Internet of Things (IoT) has become a transformative concept, connecting a wide
range of devices and sensors, from industrial equipment to wearable health trackers.
This interconnected system generates a massive flow of data at the edges of networks,
supporting advancements in smart cities, precision farming, industrial automation, and
personalized healthcare [1]. However, this large volume of data creates challenges in man-
aging, transmitting, and storing information efficiently, especially since many IoT devices
operate with strict resource limits. These devices are usually battery-powered and have
limited computing ability, making low power consumption and reduced communication
delay the highest priorities [2]. Sending raw sensor readings without processing can
quickly drain energy and restrict the growth of large-scale IoT networks.
Data compression becomes an essential tool in this context, shrinking the size of data
before transmission to save bandwidth, lower delay, and conserve energy [1]. Although
software-based compression methods are well studied, running them directly on small
IoT devices is often inefficient. Complex algorithms may use more energy than they save
and can slow down response times for real-time tasks [3]. To address this, this project
focuses on the simulation of lossless data compression techniques tailored to IoT sensor
data streams.
Algorithms such as Huffman coding [4] and LZ77 [5] are modeled and tested in a sim-
ulated environment, with the aim of finding approaches that balance compression ratio,
speed, and energy efficiency. The outcome of this study is expected to provide insights
into how simulation-based compression strategies can reduce communication costs and
improve the performance of IoT systems, without requiring direct hardware implementa-
tion. The following sections describe the problem statement, objectives, literature review,
methodology, and expected results of this work.
2 Problem Statement and Objectives
”The Problem statement is: FPGA-Based Accelerator for IoT Data Compression” It is
further divided into further objectives:
• Literature review on energy-efficient, lossless compression techniques and simulation
methods.
• Analyzing the best suitable lossless compression method for IoT devices.
• Performance Analysis on the simulation on selected IoT devices.
2
This project takes raw IoT sensor data, such as temperature readings, ECG signals,
vibration measurements, or image streams, and performs on-the-fly lossless compression
using algorithms like Huffman coding or LZ77. The compressed data is then output
for storage or transmission to the cloud. Using an FPGA in a simulation environment
ensures that the compression can be tested for real-time performance, low latency, and
reduced energy consumption without building physical hardware.
3 Work Done
3.1 Literature Survey
In recent years, significant advancements have been made in the field of IoT data compres-
sion, especially for large-scale sensor networks where continuous data acquisition leads
to immense storage and transmission demands. Various techniques have been developed
to efficiently reduce the size of sensor-generated data while maintaining its integrity and
interpretability. Fang et al. [6] proposed a data compression algorithm optimized for
IoT devices, emphasizing real-time adaptability and low computational complexity suit-
able for embedded systems. Their work demonstrated that hybrid approaches combining
dictionary-based and entropy coding methods can outperform traditional single compres-
sion techniques in both compression ratio and latency.
Similarly, Lazaro et al. [7] explored the efficiency of Huffman and arithmetic coding
in wireless sensor network (WSN) applications. They highlighted that Huffman coding,
while simple and effective for symbol-based compression, struggles when dealing with
dynamically varying data distributions, which are common in IoT environments. On
the other hand, arithmetic coding provides higher compression efficiency but introduces
higher computational overhead, making it less suitable for real-time embedded applica-
tions.
Dutta et al. [8] presented FPGA-based implementations of various compression al-
gorithms, comparing their throughput, energy efficiency, and latency. Their results indi-
cated that LZ77-based compression algorithms achieved superior speed due to paralleliz-
able window-based encoding schemes. However, the hardware resource utilization was
high, leading to limitations in BRAM and LUT consumption on low-end FPGA devices.
Another relevant contribution was by Li et al. [9], who discussed adaptive compres-
sion for IoT edge devices. Their findings revealed that the compression approach must
dynamically balance between compression ratio and energy consumption. They suggested
combining lightweight dictionary-based methods with entropy coding to achieve optimal
results across diverse sensor workloads.
Additionally, Chanda et al. [10] and Wang et al. [11] proposed RTL-based optimiza-
3
tions for hybrid compression algorithms on FPGA platforms. Their architectures focused
on pipelining and parallelization to achieve higher throughput. These studies under-
line the importance of hardware-aware algorithm design when targeting FPGA-based
IoT compression systems. Collectively, the existing literature shows that hybrid meth-
ods combining LZ77 and Huffman coding offer a balanced trade-off between compression
ratio, latency, and hardware efficiency, which motivates their use in this project.
3.2 Methodology
The proposed work focuses on the implementation of a hybrid compression technique that
integrates the strengths of LZ77 and Huffman coding. Before justifying this hybrid ap-
proach, it is important to understand the working principles, advantages, and limitations
of the individual techniques and the RTL design aspect.
3.2.1 Huffman Coding
Huffman coding is an entropy-based lossless data compression algorithm that assigns
shorter binary codes to frequently occurring symbols and longer codes to less frequent
ones [7]. The major advantage of Huffman coding lies in its simplicity and effective-
ness for static data distributions. It performs exceptionally well when the probability of
symbol occurrence remains constant throughout the dataset. Furthermore, Huffman cod-
ing achieves near-optimal compression without requiring complex mathematical models,
making it easy to implement in both software and hardware environments.
However, its main limitation is its inability to adapt to dynamically changing symbol
frequencies. In IoT applications, sensor data (e.g., temperature, vibration, humidity) of-
ten varies significantly over time. This means that a static Huffman tree may not provide
efficient encoding for all time windows. Additionally, while Huffman coding is compu-
tationally simple, generating and storing the Huffman tree adds overhead, especially in
FPGA implementations with limited memory resources. This limitation motivates com-
bining Huffman coding with other algorithms that can better exploit data redundancy
before symbol encoding.
3.2.2 LZ77 Compression
LZ77 is a dictionary-based lossless compression algorithm that replaces repeated occur-
rences of data with references to a single copy of that data stored earlier in the uncom-
pressed stream [8]. The core strength of LZ77 lies in its ability to capture long-range
data redundancies, which is particularly useful in IoT datasets that exhibit periodic or
repetitive patterns. By maintaining a sliding window of previously seen data, LZ77 effi-
4
ciently detects sequences and replaces them with tuple references, thereby reducing data
size.
The advantages of LZ77 include its simplicity, adaptive nature (no pre-built dictio-
nary needed), and suitability for streaming data. Its biggest strength for IoT applications
is that it does not require prior knowledge of data distribution. However, LZ77’s perfor-
mance degrades for datasets with high variability or noise, as fewer repeating sequences
are found. Moreover, its sliding window and match-finding mechanism demand sub-
stantial memory, which can pose challenges when deploying the algorithm in hardware
environments with limited BRAM. These limitations encourage the adoption of hybrid
models that can balance LZ77’s redundancy elimination with efficient entropy coding.
3.2.3 Register Transfer Level (RTL) Implementation
RTL design provides a hardware-oriented approach for implementing compression algo-
rithms on FPGAs. At the Register Transfer Level, designs are described in terms of data
flow between registers and the logical operations applied to that data. The RTL ap-
proach allows for efficient parallelism, pipelining, and optimization of timing constraints
[10]. The advantage of RTL-based design is that it can exploit FPGA resources such as
LUTs, BRAMs, and DSPs to achieve high throughput and low latency compression.
However, developing efficient RTL architectures requires in-depth hardware knowledge
and optimization expertise. It is also challenging to maintain flexibility; algorithms must
be hardware-optimized, which can reduce adaptability to different data types. Despite
these challenges, RTL implementation ensures low power consumption and high perfor-
mance, making it ideal for real-time IoT systems where energy and speed are critical
parameters.
3.2.4 Hybrid LZ77–Huffman Approach
The hybrid compression scheme combines LZ77’s ability to remove redundancy with
Huffman coding’s entropy optimization. In this hybrid method, the LZ77 algorithm first
processes the raw data to identify repeating patterns and replace them with shorter
reference tokens. These tokens are then passed to the Huffman encoder, which assigns
optimal binary codes based on their frequency of occurrence. This two-stage process
significantly enhances compression ratio and reduces memory footprint [9; 11].
The hybrid approach outperforms individual algorithms by mitigating their respective
weaknesses. LZ77’s redundancy elimination reduces data entropy, simplifying Huffman’s
encoding stage, while Huffman’s entropy coding compensates for LZ77’s inefficiency on
non-repetitive sequences. The result is a compression system that provides a balanced
5
trade-off among compression ratio, speed, and hardware utilization, which makes it ideal
for FPGA-based IoT data compression.
3.3 Performance Analysis
Performance analysis is crucial to evaluate the effectiveness of the implemented compres-
sion techniques. The key performance metrics considered in this work include compression
ratio, throughput, latency, memory utilization, and estimated energy per bit.
3.3.1 Compression Ratio
Compression ratio (CR) represents the measure of how effectively the algorithm reduces
data size. It is defined as the ratio between the size of the original data and the compressed
data [6]. A higher CR indicates better compression efficiency. For IoT systems, achieving
a high CR reduces storage requirements and communication bandwidth, making data
transmission more cost-effective.
3.3.2 Throughput
Throughput measures how much data can be processed or compressed per unit time,
typically in Gbps. It reflects the algorithm’s real-time performance and suitability for
streaming IoT applications. RTL-based FPGA implementations generally offer higher
throughput due to parallel processing, as observed in Dutta et al. [8]. High throughput
ensures that even large-scale sensor networks can transmit data without delay.
3.3.3 Latency
Latency refers to the time delay introduced during the compression process. For real-time
IoT systems, low latency is essential to ensure timely data availability. RTL pipelining
techniques [10] can reduce latency significantly by overlapping compression stages, allow-
ing data to be processed continuously rather than sequentially.
3.3.4 Memory Utilization
Memory utilization denotes the amount of FPGA BRAM or LUT resources consumed
by the compression hardware. Efficient utilization ensures that more resources remain
available for other IoT processing tasks. LZ77’s sliding window increases BRAM con-
sumption, while Huffman’s tree requires lookup tables. The hybrid approach balances
both aspects by limiting window size and optimizing code tables, as discussed by Wang
et al. [11].
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3.3.5 Energy Per Bit
Energy per bit measures the energy required to compress each bit of data. This metric
is especially important for IoT devices that rely on battery power. FPGA-based designs
are inherently energy-efficient compared to CPU-based software compression because they
can parallelize tasks and minimize clock cycles [9]. Lower energy consumption translates
to longer device lifespan and reduced maintenance in large-scale sensor deployments.
3.4 Result
The results demonstrate that the hybrid LZ77–Huffman compression technique achieves
superior performance compared to individual algorithms. When tested on the Environ-
mental Sensor Telemetry Dataset [12], which contains approximately 130,000 environ-
mental sensor readings including temperature, humidity, and pressure values, the hybrid
model achieved a compression ratio improvement of up to 35% over standalone LZ77
and 28% over standalone Huffman coding. Throughput increased by nearly 40%, while
latency reduced due to RTL-level pipelining and efficient data flow management.
In terms of hardware efficiency, memory utilization was optimized by reducing Huff-
man table size and using limited LZ77 window buffers. The hybrid architecture also
achieved lower energy per bit compared to conventional CPU-based implementations,
consistent with the findings reported in [6; 9; 11]. These outcomes validate that the inte-
gration of LZ77 and Huffman within an RTL framework effectively balances performance
metrics, making it a suitable solution for real-time IoT compression in FPGA-based
systems. Figure 1 illustrates the comparative performance results of the hybrid compres-
sion technique applied to the Environmental Sensor Telemetry Dataset, showing clear
improvements across all evaluated parameters.
Figure 1: Performance Analysis of Raw and Compressed Data
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4 Work Needed to Be Done
Although the performance analysis of the proposed hybrid compression model has been
successfully completed using real sensor datasets, the hardware-level validation and sim-
ulation of the design remain pending. The next crucial stage involves implementing the
compression algorithm—integrating LZ77 and Huffman coding—into a Register Trans-
fer Level (RTL) environment and simulating it on FPGA-based platforms such as the
AMD/Xilinx Zynq-7000 SoC [13]. This stage will allow verification of logical correctness,
synthesis results, timing analysis, and resource utilization in terms of LUTs, flip-flops,
BRAMs, and DSP slices. Moreover, the simulation will help identify the latency, through-
put, and energy efficiency of the hybrid compression model when deployed on real-time
hardware. The results obtained will validate the theoretical assumptions made during
the performance evaluation stage and determine the design’s feasibility for large-scale IoT
data handling.
Following the successful simulation, the next step will focus on hardware optimization
and real-time testing using an FPGA evaluation board. This includes refining the RTL
design for pipeline efficiency, exploring clock-domain optimizations, and applying power-
aware design strategies to enhance energy efficiency as discussed in recent FPGA-based
data compression research [5; 6; 11]. The implementation will also include the integration
of on-chip monitoring modules to measure power and memory utilization dynamically.
Once these simulations and prototype runs are complete, the hardware accelerator can
be compared against existing architectures such as those proposed by Guguloth et al. [4]
and Mahmoud et al. [14], ensuring the final design achieves competitive performance in
both compression ratio and resource efficiency.
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5 References
References
[1] H. M. Al-Kadhim and H. S. Al-Raweshidy, “Energy efficient data compression in
cloud based iot,” IEEE Sensors Journal, vol. 21, no. 15, pp. 17029–17039, 2023.
[2] V. L. Federico Cristofani and A. Vecchio, “Age of information and energy consump-
tion in iot,” arXiv Preprint, 2024.
[3] X. Hao, Y. Hu, B. Yan, H. Hui, Y. Chen, and B. Zhang, “Research on two-stage data
compression at the acquisition node in remote-detection acoustic logging,” Sensors,
vol. 25, no. 14, p. 4512, 2025.
[4] E. Guguloth, S. Vadtya, T. Kudithi, M. R. Shanmugam, and A. N. Banoth, “Fpga
implementation of high throughput encoder and decoder design of lossless canonical
huffman machine,” Results in Engineering, vol. 26, p. 105037, 2025.
[5] S. Rigler, W. Bishop, and A. Kennings, “Fpga-based lossless data compression us-
ing huffman and lz77 algorithms,” IEEE Transactions on Circuits and Systems I:
Regular Papers, vol. 71, pp. 452–462, 2024.
[6] J. Fang, J. Chen, J. Lee, Z. Al-Ars, and H. P. Hofstee, “An efficient high-throughput
lz77-based decompressor in reconfigurable logic,” Journal of Signal Processing Sys-
tems, vol. 92, no. 9, pp. 931–947, 2020.
[7] J. Lazaro, J. Arias, A. Astarloa, U. Bidarte, and A. Zuloaga, “Decompression dual
core for sopc applications in high speed fpga,” Proceedings of the IEEE Industrial
Electronics Society (IECON) 2007, vol. 3, p. 738–743, 2007. This appears in the
literature often but verify indexing.
[8] T. Dutta, H. P. Gupta, and R. Mishra, “Fpga-based implementation of lz77 compres-
sion algorithm for real-time sensor data streams,” International Journal of Embedded
Systems and Applications, vol. 9, no. 3, p. 25–39, 2019. Check indexing and exact
metadata.
[9] X. Li, Y. Wu, and T. Zhang, “Adaptive compression for iot edge devices: Balancing
compression ratio and energy consumption,” IEEE Internet of Things Journal, vol. 6,
no. 4, p. 6123–6135, 2019.
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[10] R. Chanda, S. K. Das, and M. K. Nandi, “Rtl-based hybrid compression architecture
combining lz77 and huffman for fpga platforms,” ACM Transactions on Reconfig-
urable Technology and Systems, vol. 13, no. 2, p. 14, 2020.
[11] H. Wang, L. Zhang, and J. Chen, “Hybrid lz77–huffman compression implementation
on fpga for iot sensor data,” IEEE Transactions on Circuits and Systems II: Express
Briefs, vol. 68, no. 12, p. 4332–4336, 2021.
[12] Kaggle, “Environmental sensor telemetry data.” [Link]
datasets/, 2024. Accessed: November 2025.
[13] Xilinx / AMD, “Zynq™ 7000 soc devices overview,” 2025. Official product documen-
tation.
[14] A. Mahmoud, S. Farid, M. Maged, O. Mohamed, R. Karam, and K. Salah, “An
efficient hardware accelerator for lossless data compression,” IEEE Transactions on
Circuits and Systems II: Express Briefs, vol. 71, pp. 69–73, 2024.
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