CPU Design for Basic Computer

🔷 Introduction
A Central Processing Unit (CPU) is the brain of a computer system that performs all
processing and control operations. It fetches instructions from memory, decodes them, and
executes them step-by-step using internal registers, buses, and control signals.

A Basic Computer is a simplified model that demonstrates how a CPU functions. It focuses
on the internal structure and data flow of a computer system to execute simple instructions.

🔷 Major Components of the CPU

The CPU in a Basic Computer consists of three main units:

• Register Unit
• Arithmetic Logic Unit (ALU)
• Control Unit

🧩 1. Register Unit
Registers are high-speed storage elements inside the CPU used for temporary data holding,
address storage, and control purposes.

Register Name Function

AC (Accumulator) Accumulates results of arithmetic and logic

operations.

PC (Program Counter) Holds the address of the next instruction to

execute.

AR (Address Register) Stores memory address for data access.

DR (Data Register) Temporarily holds data read from or

written to memory.

IR (Instruction Register) Holds the current instruction fetched from

memory.

TR (Temporary Register) Used for intermediate data storage.

INPR Input Register – receives data from an

input device.

OUTR Output Register – stores data before

sending to output device.
Registers communicate through a common bus system, which allows easy transfer of data
between them.

🧮 2. Arithmetic Logic Unit (ALU)

The ALU performs all arithmetic and logical operations required by the CPU.

Arithmetic: ADD, SUB, INCREMENT

Logical: AND, OR, NOT, XOR

The ALU operates mainly on the Accumulator (AC) and Data Register (DR).

Example: AC ← AC + DR → Adds contents of DR to AC.

⚙️3. Control Unit

The Control Unit is the heart of the CPU. It:
• Interprets the instruction from the IR (Instruction Register).
• Generates control signals to direct the operation of other units.
• Synchronizes the sequence of micro-operations using timing signals (T0, T1, T2…).

It works in three steps:

1. Fetch the instruction from memory.
2. Decode the instruction.
3. Execute the operation.

🔷 Memory and Bus Structure

The main memory holds both instructions and data.
The bus system provides a pathway for data and control signals to travel between CPU and
memory.

• Data Bus: Transfers actual data.

• Address Bus: Carries address of memory location.
• Control Bus: Carries control and timing signals (like Read/Write).

🔷 Instruction Format
Each instruction in the Basic Computer is 16 bits long:

Bits Field Description

15 I Indirect bit (0 = direct, 1 = indirect)
14–12 Opcode Specifies the operation
11–0 Address Memory address field (12 bits)

Example:
Instruction: 1 010 0000 0011 0101
I = 1 → Indirect addressing
Opcode = 010 → LDA (Load Accumulator)
Address = 035h

🔷 Instruction Types
1. Memory-Reference Instructions
These operate on memory operands.

Instruction Operation Description

AND AC ← AC ∧ M[addr] Logical AND with memory

ADD AC ← AC + M[addr] Add memory word to AC

LDA AC ← M[addr] Load AC with memory data

STA M[addr] ← AC Store AC in memory

BUN PC ← addr Unconditional branch

BSA M[addr] ← PC; PC ← addr + Branch and save return

1 address

ISZ M[addr] ← M[addr]+1; if Increment and skip if zero

M[addr]=0 then PC←PC+1

2. Register-Reference Instructions

Instruction Operation Meaning

CLA AC ← 0 Clear accumulator

CMA AC ← ¬AC Complement accumulator

INC AC ← AC + 1 Increment accumulator

CIR Shift AC right Circular shift right

CIL Shift AC left Circular shift left

SPA Skip next if AC positive Conditional skip

SNA Skip next if AC negative Conditional skip

HLT Halt Stop computer

3. Input–Output Instructions

Instruction Operation Function

INP AC[0–7] ← INPR Input character

OUT OUTR ← AC[0–7] Output character

SKI Skip next if input flag = 1 Input control

SKO Skip next if output flag = 1 Output control

ION Interrupt enable Turns on interrupt system

IOF Interrupt disable Turns off interrupt system

🔷 Instruction Cycle
Every instruction passes through a cycle of micro-operations:

1. Fetch Cycle
AR ← PC
IR ← M[AR]; PC ← PC + 1

2. Decode Cycle
Decode opcode (IR[14–12])
If indirect bit = 1 → AR ← M[AR]

3. Execute Cycle
Perform the operation depending on the instruction.
Example: ADD → DR ← M[AR]; AC ← AC + DR

4. Interrupt Cycle
If interrupt is enabled and a flag is set:
Save PC in a memory location.
Load PC with interrupt service routine address.

🔷 Example Program
Address Instruction Meaning

0 LDA 10 Load AC with value from

M[10]

1 ADD 11 Add value from M[11] to AC

2 STA 12 Store result in M[12]

3 HLT Stop

10 5 Operand 1
11 7 Operand 2

12 0 Result (will store 12)

After execution:
M[12] = 12

🔷 Control Flow Diagram (Conceptual)

┌────────────┐
│ Memory │
└────┬───────┘
│
┌─────────┴─────────┐
│ Control Unit │ ← Decodes & controls flow
└─────────┬─────────┘
│
┌─────────┴─────────┐
│ ALU │ ← Performs arithmetic/logic
└─────────┬─────────┘
│
┌─────────┴─────────┐
│ Registers │ ← AC, DR, PC, etc.
└─────────┬─────────┘
│
┌─────────┴─────────┐
│ I/O Unit │
└───────────────────┘

🔷 Conclusion
The Basic Computer model provides a clear understanding of how instructions are
processed inside a CPU. It includes fundamental concepts like:
• Instruction cycle
• Micro-operations
• Data movement through buses
• Control signal generation

Understanding this model helps in designing more advanced CPUs such as microprocessors
and RISC architectures.
Example: Adding Two Numbers Using Basic Computer

🎯 Objective
To add two numbers stored in memory locations and store the result in another location.

📋 Given Data
Address Content Description

0 LDA 10 Load AC with value from

memory address 10

1 ADD 11 Add value from memory

address 11 to AC

2 STA 12 Store the result (AC) into

memory address 12

3 HLT Stop the program

10 5 First number

11 7 Second number

12 0 Memory location to store

the result

🧠 Initial Conditions
PC (Program Counter) = 0
AC (Accumulator) = 0
Memory = contains above data

Step-by-Step Execution

⚙️Step 1: Fetch Cycle (Instruction = LDA 10)

Every instruction starts with a fetch phase — CPU loads the next instruction from memory.

🔸 Micro-operations:

T0: AR ← PC → AR = 0
T1: IR ← M[AR]; PC ← PC + 1 → IR = M[0] = LDA 10 → PC = 1
T2: Decode instruction → Opcode = LDA → Operand address = 10

Now:
IR = LDA 10
AR = 10
PC = 1

⚙️Step 2: Execute Cycle (LDA 10)

Operation: Load data from memory location 10 into AC.

🔸 Micro-operations:

T3: AR ← IR(0–11) → AR = 10
T4: DR ← M[AR] → DR = M[10] = 5
T5: AC ← DR → AC = 5

✅ Result after execution:

AC = 5
PC = 1 (ready for next instruction)

⚙️Step 3: Fetch Cycle (Instruction = ADD 11)

Now the CPU fetches the next instruction.

🔸 Micro-operations:

T0: AR ← PC → AR = 1
T1: IR ← M[AR]; PC ← PC + 1 → IR = M[1] = ADD 11 → PC = 2
T2: Decode → Opcode = ADD → Address = 11

Now:
IR = ADD 11
AR = 11
PC = 2

⚙️Step 4: Execute Cycle (ADD 11)

Operation: Add content of memory address 11 to AC.

🔸 Micro-operations:

T3: AR ← IR(0–11) → AR = 11
T4: DR ← M[AR] → DR = M[11] = 7
T5: AC ← AC + DR → AC = 5 + 7 = 12

✅ Result after execution:

AC = 12
PC = 2
⚙️Step 5: Fetch Cycle (Instruction = STA 12)
Next, CPU fetches the “store” instruction.

🔸 Micro-operations:

T0: AR ← PC → AR = 2
T1: IR ← M[AR]; PC ← PC + 1 → IR = M[2] = STA 12 → PC = 3
T2: Decode → Opcode = STA → Address = 12

⚙️Step 6: Execute Cycle (STA 12)

Operation: Store value of AC into memory location 12.

🔸 Micro-operations:

T3: AR ← IR(0–11) → AR = 12
T4: M[AR] ← AC → M[12] = AC = 12

✅ Result after execution:

M[12] = 12
AC = 12
PC = 3

⚙️Step 7: Fetch Cycle (Instruction = HLT)

Next instruction is “halt”.

🔸 Micro-operations:

T0: AR ← PC → AR = 3
T1: IR ← M[AR]; PC ← PC + 1 → IR = M[3] = HLT
T2: Decode → Opcode = HLT

⚙️Step 8: Execute Cycle (HLT)

Operation: Stop program execution.

🔸 Micro-operation:

S ← 0 (Set sequence counter to 0 to stop timing signals)

✅ Program stops.

🧾 Final Results
Register/Memory Value Description
AC 12 Final result stored in
accumulator

PC 4 Points after last instruction

M[12] 12 Memory location now

contains the result

M[10] 5 First operand unchanged

M[11] 7 Second operand unchanged

🔍 Cycle Summary
Cycle Instruction Operation AC PC

1 LDA 10 AC ← M[10] 5 1

2 ADD 11 AC ← AC + 12 2
M[11]

3 STA 12 M[12] ← AC 12 3

4 HLT Stop 12 4

🧩 Summary of How CPU Worked

Fetch: CPU took instruction from memory using PC.

Decode: Control unit analyzed opcode.

Execute: ALU and registers performed required action.

Result: AC stored 12 → stored back in memory (M[12]).

This small program demonstrates complete instruction cycle — fetch, decode, and execute
— clearly showing how the Basic Computer CPU operates step by step.