Digital Integrated

Circuits
A Design Perspective
Jan M. Rabaey
Anantha Chandrakasan
Borivoje Nikolić

Designing Combinational
Logic Circuits

November 2002.
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EE141 Integrated Circuits2nd Combinational Circuits
 Dynamic Logic

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EE141 Integrated Circuits2nd Combinational Circuits
 Dynamic CMOS
 In static circuits at every point in time (except
when switching) the output is connected to
either GND or VDD via a low resistance path.
 fan-in of n requires 2n (n N-type + n P-type)
devices

 Dynamic circuits rely on the temporary

storage of signal values on the capacitance of
high impedance nodes.
 requires on n + 2 (n+1 N-type + 1 P-type)
transistors
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EE141 Integrated Circuits2nd Combinational Circuits
 Dynamic Gate
off
Clk Mp Clk Mp on
1
Out Out
In1 CL ((AB)+C)
A
In2 PDN
C
In3
B
Clk Me
off
Clk Me on

Two phase operation

Precharge (Clk = 0)
Evaluate (Clk = 1)
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EE141 Integrated Circuits2nd Combinational Circuits
 Conditions on Output
 Once the output of a dynamic gate is
discharged, it cannot be charged again until
the next precharge operation.
 Inputs to the gate can make at most one
transition during evaluation.

 Output can be in the high impedance state

during and after evaluation (PDN off), state is
stored on CL

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EE141 Integrated Circuits2nd Combinational Circuits
 Properties of Dynamic Gates
 Logic function is implemented by the PDN only
 number of transistors is N + 2 (versus 2N for static complementary
CMOS)
 Full swing outputs (VOL = GND and VOH = VDD)
 Non-ratioed - sizing of the devices does not affect
the logic levels
 Faster switching speeds
 reduced load capacitance due to lower input capacitance (Cin)
 reduced load capacitance due to smaller output loading (Cout)
 no Isc, so all the current provided by PDN goes into discharging CL

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EE141 Integrated Circuits2nd Combinational Circuits
 Properties of Dynamic Gates
 Overall power dissipation usually higher than static
CMOS
 no static current path ever exists between VDD and GND
(including Psc)
 no glitching
 higher transition probabilities
 extra load on Clk
 PDN starts to work as soon as the input signals
exceed VTn, so VM, VIH and VIL equal to VTn
 low noise margin (NML)
 Needs a precharge/evaluate clock
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EE141 Integrated Circuits2nd Combinational Circuits
 Issues in Dynamic Design 1:
Charge Leakage
CLK
Clk Mp
Out

A CL

VOut Evaluate
Clk Me
Precharge

Leakage sources

Dominant component is subthreshold current

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EE141 Integrated Circuits2nd Combinational Circuits
 Solution to Charge Leakage
Keeper

Clk Mp Mkp

A Out
CL
B

Clk Me

Same approach as level restorer for pass-transistor logic

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EE141 Integrated Circuits2nd Combinational Circuits
 Issues in Dynamic Design 2:
Charge Sharing

Charge stored originally on

Clk Mp CL is redistributed (shared)
Out over CL and CA leading to
A CL reduced robustness
B=0 CA

Clk Me CB

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EE141 Integrated Circuits2nd Combinational Circuits
 Charge Sharing Example

Clk
Out
A A CL=50fF

Ca=15fF B B B !B Cb=15fF

Cc=15fF C C Cd=10fF

Clk

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EE141 Integrated Circuits2nd Combinational Circuits
 Charge Sharing
VDD
VDD case 1) if V out < VTn

Clk Mp
 Mp C L VDD = C L Vout  t  + Ca  VDD – V Tn  V X  
Out
Out
or
CL
A Ma CL Ca
A Ma V out = Vout  t  – V DD = – --------  V DD – V Tn  V X  
XX CL

== CC a
BB 00 M
Mbb
a
case 2) if V out > VTn
Ca 
 ---------------------
CC
bb Vout = –V DD  -
Clk  Mee
M C
 a + C L

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EE141 Integrated Circuits2nd Combinational Circuits
 Solution to Charge Redistribution

Clk Mp Mkp Clk

Out
A

Clk Me

Precharge internal nodes using a clock-driven transistor

(at the cost of increased area and power)

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EE141 Integrated Circuits2nd Combinational Circuits
 Issues in Dynamic Design 3:
Backgate Coupling

Clk Mp Out1 =1
Out2 =0
A=0 In
CL1 CL2

B=0

Clk Me

Dynamic NAND Static NAND

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EE141 Integrated Circuits2nd Combinational Circuits
 Backgate Coupling Effect
3

2
Out1
1 Clk

0
In Out2

-1
0 2 Time, ns 4 6

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EE141 Integrated Circuits2nd Combinational Circuits
 Issues in Dynamic Design 4: Clock
Feedthrough

Coupling between Out and

Clk Mp Clk input of the precharge
Out device due to the gate to
A CL drain capacitance. So
voltage of Out can rise
B
above VDD. The fast rising
Clk Me (and falling edges) of the
clock couple to Out.

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EE141 Integrated Circuits2nd Combinational Circuits
 Clock Feedthrough
Clock feedthrough
Clk
Out 2.5
In1
In2 1.5

In3 In &
0.5 Clk
In4 Out
Clk -0.5
0 0.5 Time, ns 1
Clock feedthrough

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EE141 Integrated Circuits2nd Combinational Circuits
 Other Effects

 Capacitive coupling
 Substrate coupling
 Minority charge injection
 Supply noise (ground bounce)

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EE141 Integrated Circuits2nd Combinational Circuits
 Cascading Dynamic Gates
V

Clk Clk Clk

Mp Mp
Out2
Out1
In
In

Clk Clk VTn

Me Me Out1

V
Out2

Only 0  1 transitions allowed at inputs!

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EE141 Integrated Circuits2nd Combinational Circuits
 Domino Logic

Clk Mp Clk Mp Mkp

11
Out1 Out2
10
00
In1 01
In2 PDN In4 PDN
In3 In5

Clk Me Clk Me

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EE141 Integrated Circuits2nd Combinational Circuits
 Why Domino?

Clk

Ini PDN Ini PDN Ini PDN Ini PDN

Inj Inj Inj Inj
Clk

Like falling dominos!

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EE141 Integrated Circuits2nd Combinational Circuits
 Properties of Domino Logic

 Only non-inverting logic can be implemented

 Very high speed
 static inverter can be skewed, only L-H transition
 Input capacitance reduced – smaller logical effort

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EE141 Integrated Circuits2nd Combinational Circuits
 Designing with Domino Logic
VDD VDD
VDD

Clk Mp Clk Mp Mr
Out1

Out2
In1
In2 PDN In4 PDN
In3
Can be eliminated!

Clk Me Clk Me

Inputs = 0
during precharge
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EE141 Integrated Circuits2nd Combinational Circuits
 Footless Domino
VDD VDD VDD

Clk Mp Clk Mp Clk Mp

Out1 Out2 Outn
0 1 0 1 0 1
In1 In2 In3 Inn
1 0 1 0 1 0 1 0

The first gate in the chain needs a foot switch

Precharge is rippling – short-circuit current
A solution is to delay the clock for each stage

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EE141 Integrated Circuits2nd Combinational Circuits
 Differential (Dual Rail) Domino

off on
Clk Mp Mkp Mkp Mp Clk
Out = AB Out = AB
1 0 1 0
A
!A !B
B

Clk Me

Solves the problem of non-inverting logic

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EE141 Integrated Circuits2nd Combinational Circuits
 np-CMOS

Clk Mp Clk Me
11
Out1
10
In1 In4 PUN
In2 PDN In5
00
In3 01
Out2
(to PDN)
Clk Me Clk Mp

Only 0  1 transitions allowed at inputs of PDN

Only 1  0 transitions allowed at inputs of PUN
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EE141 Integrated Circuits2nd Combinational Circuits
 NORA Logic

Clk Mp Clk Me
11
Out1
10
In1 In4 PUN
In2 PDN In5
00
In3 01
Out2
(to PDN)
Clk Me Clk Mp

to other to other
PDN’s PUN’s

WARNING: Very sensitive to noise!

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EE141 Integrated Circuits2nd Combinational Circuits