Synthesis 1
1
Books/Document
• Synthesis
• Design Compiler User Guide – Synopsys
• Advanced ASIC chip synthesis – Himanshu
Bhatnagar
• Equivalence Checking
• Formality User Guide – Synopsys
• Static Timing Analysis
• Static Timing Analysis for Nanometre
Designs – [Link], Rakesh Chadhha.
2
Synthesis Overview & Flow
3
Overview Of ASIC Design Flow
4
What Is Synthesis?
• Synthesis is an automatic method
of converting a higher level of
abstraction to a lower level of
abstraction.
assign out1 = in1 & in2 ;
• In other words the synthesis
process converts Register Transfer
AND4x2 C126 (.A (in1), .B (in2), .Y (out1) );
Level (RTL) description to gate-
level net-list.
Power
Performance
• The gate-level netlist can be Timing,
Power,
Area
optimized for area, speed, Area
testability, etc. Ok?
yes
Placed and Routed
Design
5
Synthesis Process
Synthesis = Translation + Optimization + Mapping
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Examples Of Synthesis
RTL Generic Netlist Synthesized Netlist
assign z = x | y; or I2 (z, x, y); OR2X1 I2(.Y(z),
.A(x), .B(y) );
and I3 (z, x, y); AND2X2 I3 (.Y(z),
assign z = x & y;
.A(x), .B(y) );
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Does Quality Of Synthesis Matter?
• Bad netlist – Poorly structured paths, higher area
• Backend Issues
• Difficult to close timing
• Too many iterations to converge
• Congestion / Cross talk issues
• Project issues
• Increased Power consumption
• Larger die size
• Increased Engineering / computing costs
8
Synthesis Goals
To produce a Netlist which meets below goals
• Timing
• Area
• Power
• Routable
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Synthesis Flow using Design
Compiler
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Synthesis in RTL2GDSII Flow
RTL Design Placement
Gate level net-list,
Global route,
Ideal clock tree
RTL simulations Clock Tree
Synthesis
Gate level net-list,
Global route,
Real clock tree
Logic Synthesis &
Routing
optimization
Gate level net-list,
Gate level Net-list Real route,
Real clock tree
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Inputs and Outputs of Design Compiler
Design Compiler is the core of the Synopsys
synthesis software products.
RTL
It includes tools that synthesize the HDL .lib
designs into optimized technology- .SDC
dependent, gate level designs.
Inputs Design
RTL
Logic
▪ RTL: Verilog, VHDL Compiler
Netlist
Verification
▪ Constraints: .sdc
▪ Library: .lib
Outputs .SDC Optimized
▪ Optimized netlist netlist
▪ Constraints: .sdc
Physical
Design
Synthesis Flow using Design Compiler
• Design Compiler – Synopsys tool ! It optimizes the
design to provide smallest and fastest logical
representation of a given function.
• Supports wide range of flat and hierarchical design
styles.
• Optimizes both combinational and sequential designs
for speed area & power.
• Three Variants of DC
• DC Expert
• DC ultra
• Design Compiler graphical 13
Design Compiler Variant….
DC
graphical
DC Ultra
DC
Expert
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Design Compiler in the Design Flow
HDL Description
Constraints
(SDC)
Design Compiler
HDL Compiler
IP
DesignWare
library
Timing Data-path Power
Optimization Optimization Optimization
Power Analysis Formal
Technology Verification
library
Formality
Area Timing Timing Analysis
Test
Optimization Closure
Synthesis
Symbol
library
Optimized net-list
DEF
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High Level Design Flow
Design data preparation:
- HDL coding Design Compiler
- Constraint generation
- Library development
Design Implementation Stage
Design Exploration Stage
NO Met
Goal specification and functional goals?
simulation
Yes
Floorplan Physical design
DC (Optional)
Explorer
NO Met
NO goals?
Within 10%
Of timing
goals
Yes
Yes
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The synthesis flow
Design
Develop HDL files constraints
set_max_transition
set_max_fanout
set_max_capacitance
Specify libraries create_clock
set_input_delay
Library object set_output_delay
link_library
target_library Select compile
symbol_library strategy
Top down
Read designs
Bottom up
analyze Synthesize &
elaborate optimize
design
read_file
check_design
set_operating_conditions
Design
set_drive Analyze design
environment
set_load Resolve issues
set_wire_load_model
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Design Terminology
• Synthesis – process of generating gate level net-list
from HDL
• Optimization – Implements a combination of library
cell that best meet the functional, timing area &
power requirement.
• Compile – step in the DC that executes the synthesis
and optimization step.
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Design Types
• Flat Designs
• No sub-design and only one structural level
• Hierarchical Designs
• One or more sub-design which further can have
sub-design.
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Design Objects
Instance
Design or cell
Port net pin
TOP
U1 U4
U2
A AI
N BUS0 BUF0 Q[1:0]
Q0 BUF D0
B BI OUT[1:0]
N
C CI
N BUS1 BUF1
Q1 BUF D1
D DI
N ENCODER U3 REGFILE
Design {TOP ENCODER REGFILE}
Reference {ENCODER REGFILE BUF}
Instance {U1 U2 U3 U4}
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Working with DC
• DC modes
• Wire load mode
• Topographical mode
• Multimode
• UPF mode
• Setup files - .synopsys_dc.setup
• Synopsys root directory
• Your home directory
• Current working directory
• Launching DC
• % dc_shell (wire load mode)
• % dc_shell –topographical_mode
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Starting & Exiting Design Compiler
Different Options to start DC
Unix> dc_shell
[-f script_file]
[-x command_string]
[-checkout feature_list]
[-wait wait_time]
[-version]
[-output_log_file console_log]
[-no_log]
Example
Unix> dc_shell –f [Link] –output_log [Link]
# quit or exit to close DC Session
dc_shell> quit
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Reading, Analyzing Designs
Read:
Loading into the memory.
To be used for entering pre-compiled designs or netlists in DC.
dc_shell> read_verilog MY_DESIGN.v
To see the designs loaded,
dc_shell> list_designs
Analyze:
Reads an HDL source file. Checks it for errors.
Translates into HDL library objects in an HDL intermediate
format and stores the result of
the translation in the specified design library (UNIX directory)
that may be used later.
dc_shell > analyze -format verilog {top.v adder.v}
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Elaborating the Design
Elaborate:
Creates a technology-independent design from the intermediate
files produced during analyze.
Infers registers in the design.
Performs high level HDL optimization, such as dead code removal
dc_shell > elaborate ${DESIGN_NAME}
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Check for Design Issues
Check the quality of the design, for any unresolved
references, undriven or multi driven ports, pins and
unloaded pins and constant connected ports and pins.
dc_shell> check_design
[-no_connection_class]
[-post_layout]
[-ports]
[-designs]
[-nets]
▪ Unresolved references need to be resolved before
proceeding
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The synthesis flow
Design constraints
Develop HDL files
set_max_transition
set_max_fanout
set_max_capacitance
Specify libraries create_clock
set_input_delay
Library object set_output_delay
link_library
target_library Select compile
symbol_library strategy
Top down
Read designs
Bottom up
analyze Synthesize &
elaborate optimize
read_file design
check_design
Design set_operating_conditions
environment set_drive Analyze design
set_load Resolve issues
set_wire_load_model
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Constraining the Design
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Creating Clock
• Clock definition
• To constrain data lane w.r.t clock lane.
• Defined on the port/pins which connects to the clock pins of sequential
elements
• DC command to create clocks “create_clock”
create_clock –period 10 –name HCLK –waveform {0 5} [get_ports clk]
𝑇𝑝𝑒𝑟𝑖𝑜𝑑
0 5 10 15
• For each clock created, a path group will be created
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Clock Attributes – Duty Cycle
𝑇𝐻𝑖𝑔ℎ
Duty Cycle = x 100 = 50%
𝑇𝑝𝑒𝑟𝑖𝑜𝑑
𝑇𝐻𝑖𝑔ℎ 𝑇𝑝𝑒𝑟𝑖𝑜𝑑
0 5 10 15
𝑇𝐿𝑜𝑤
Creating clock with 25% duty cycle –
create_clock PHI2 -period 10 -waveform {0 2.5}
𝑇𝑝𝑒𝑟𝑖𝑜𝑑
0 2.5 10
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Clock Attributes – Clock transition
• Clock transitions
𝑇𝑝𝑒𝑟𝑖𝑜𝑑
• set_clock_transition
𝑇𝐻𝑖𝑔ℎ
𝑇𝐿𝑜𝑤
𝑇𝑟𝑖𝑠𝑒 𝑇𝑓𝑎𝑙𝑙
dc_shell> set_clock_transition 0.38 -rise [get_clocks CLK1]
dc_shell> set_clock_transition 0.25 -fall [get_clocks CLK1]
Note : This is useful only in pre-layout mode. Post-CTS, Timing Engine
shall calculate it.
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Clock Attributes – Clock Latency
Ideal clock
Clock definition point
Waveform
0 2 4
FF0 FF1
D Q D Q
Oscillator clk CK CK
Clock source Clock Network
+
Latency Latency
Clock Network Delay
dc_shell> set_clock_latency 1 [get_clocks clk]
dc_shell> set_clock_latency 0.4 –source [get_clocks clk]
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Clock Latency – Pre Vs Post CTS
Pre CTS, user specifies clock latency.
Clocks are ideal.
FF0 FF1
D Q D Q
clk CK CK
Clock network
Latency
Post CTS, STA tool calculates clock latency.
Clocks are propagated.
dc_shell> set_propagated_clock [all_clocks]
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Clock Uncertainty
FF0 FF1
D Q D Q
clk CK CK
Pre CTS Clock uncertainty = clock jitter + clock skew + margin
Post CTS Clock uncertainty = clock jitter + margin
Clock @ FF0
Clock @ FF1
𝑇𝑠𝑘𝑒𝑤
𝑇𝑗𝑖𝑡𝑡𝑒𝑟
dc_shell> set_clock_uncertainty 0.4 [get_clocks clk]
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Constraining IO paths
• IO paths are either in2reg, in2out or reg2out.
• By default these paths are not constrained
• In order to check the timings on these IO paths,
input/output ports should be constrained w.r.t to clock.
• Equivalent DC command :
• set_input_delay
• set_output_delay
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Constraining Input paths
External Logic Input delay definition point
𝑇𝑐𝑜𝑚𝑏𝑜
D Q INP1 D Q D Q OUTB
𝑇𝑐𝑞
CK
CK CK CK
CK
DUA
𝑇𝑝𝑒𝑟𝑖𝑜𝑑
INP1 Stable INP1 Stable
Data can change
Input Delay (max) = 𝑇𝑐𝑞,𝑚𝑎𝑥 + 𝑇𝑐𝑜𝑚𝑏𝑜,𝑚𝑎𝑥
Data can change in this region Input Delay (min) = 𝑇𝑐𝑞,𝑚𝑖𝑛 + 𝑇𝑐𝑜𝑚𝑏𝑜,𝑚𝑖𝑛
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Constraining Input paths
36
Constraining Input paths
𝑇𝑐𝑞,𝑚𝑎𝑥 = 1.1𝑛𝑠 𝑇𝑐𝑜𝑚𝑏𝑜,𝑚𝑎𝑥 = 5.6𝑛𝑠 𝑇𝑖𝑛𝑝𝑢𝑡,𝑚𝑎𝑥 = 6.7𝑛𝑠
𝑇𝑐𝑜𝑚𝑏𝑜,𝑚𝑖𝑛 = 2.2𝑛𝑠 𝑇𝑖𝑛𝑝𝑢𝑡,𝑚𝑖𝑛 = 3.0𝑛𝑠
𝑇𝑐𝑞,𝑚𝑖𝑛 = 0.8𝑛𝑠
dc_shell> set_input_delay 6.7 –clock CLK [get_ports INPA]
dc_shell> set_input_delay 3.0 –clock CLK –min [get_ports INPA]
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Constraining Output paths
Output delay definition point External Logic
𝑇𝑐𝑜𝑚𝑏𝑜
INP1 D Q D Q OUTB
D Q
𝑇𝑠𝑢
CK CK 𝑇ℎ𝑜𝑙𝑑
CK
CK CK
DUA
OUTB Stable OUTB Stable
Data can change
Output Delay (max) = 𝑇𝑐𝑜𝑚𝑏𝑜,𝑚𝑎𝑥 + 𝑇𝑠𝑢
Data can change in this region Output Delay (min) = 𝑇𝑐𝑜𝑚𝑏𝑜,𝑚𝑖𝑛 − 𝑇ℎ𝑜𝑙𝑑
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Constraining output path
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Constraining output path
𝑇𝑠𝑢 = 0.4𝑛𝑠
𝑇ℎ𝑜𝑙𝑑 = 0.2𝑛𝑠
dc_shell> set_output_delay 7.4 –clock CLKQ [get_ports OUTB]
dc_shell> set_output_delay -0.2 –clock CLKQ –min [get_ports OUTB]
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Modelling of External Environment
• create_clock, set_input_delay & set_output_delay are
sufficient for constraining all the paths in the design, but
not enough to get accurate timing analysis.
• The following attribute are also required in order to model
the external environment of design accurately
• set_drive,
• set_driving_cell,
• set_input_transition,
• set_load
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set_drive
Sets the resistance to a specified
value on specified input CK
or inout ports
dc_shell> set_drive -rise 3 [all_inputs]
dc_shell> set_drive –fall 2 [all_inputs]
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set_driving_cell
DUA
dc_shell> set_driving_cell -lib_cell INV3 \
INV3 INPB
[get_ports INPB] \
-input_transition_rise 0.1
-input_transition_fall 0.1
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set_input_transitions
• set_input_transition – used to define slew at the
input ports
dc_shell > set_input_transition 0.85
[get_ports INPB]
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set_load
• Capacitive load at output ports
• set_load
dc_shell> set_load 5 [get_ports OUTX]
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Technology Library
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Understanding/Exploring Technology Library
• Selecting semiconductor vendor
• Maximum frequency of operation
• Physical restrictions
• Power restrictions
• Clock tree implementation
• Library requirement
• Logic libraries
• Target library
• Link library
• Symbol libraries
• Designware libraries
47
Logic Library
• DC uses logic library for the following purpose
• Implementing the design function.
• Resolving cell references.
• Calculating timing values and path delays.
• Calculating power consumption.
48
Logic library Example
Excerpt from a Technology Library:
Cell (AND2_3 ) { Cell name
area : 8.000 ; Cell Area
pin (O) {
direction : output;
timing ( ) {
related_pin : “A”;
timing_sense : positive_unate ;
rise_propagation (drive_3_table_1) { Pin A Pin O nominal
values (“0.2616, 0.2608, 0.2831,..)
} delays (look-up table)
rise_transition (drive_3_table_2) {
values (“0.0223, 0.0254,...)
....
}
function : “(A & B)” ; Pin O functionality
max_capacitance : 1.14810 ;
min_capacitance : 0.00220 ; Design Rules for
} Output Pin
pin (A) {
direction : input;
capacitance : 0.012000; Electrical
} Characteristics of
....
Input Pins
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Target Libraries & Link Libraries
• Target Libraries
• DC selects functionally correct gates from the
target libraries.
• Target libraries are specified by target_library.
• Shouldn’t specify any designware libraries or
macro libraries.
• Link Libraries
• Used to resolve references.
• Specified by link_library
50
Symbol Libraries
• Contains definition of graphics symbol that represent
library cells in the design schematics
• Used to generate schematic views.
• Specified by symbol_library
• If no symbol library are specified, DC searches
[Link] in DC installation area. If no match
found, DC displays cell instance as rectangle
51
Design Ware Libraries
• Collection of reusable circuit design building blocks
that are integrated in Synopsys synthesis environment
• During synthesis, DC selects the component with the
best speed and area.
• DW components implements built-in operator, for e.g.,
+, -, *, <=, >=, and the operations defined by if and
case statement. These component are specified in
[Link] and DC automatically uses it.
• DW components are specified by synthetic_library, but
it requires DesignWare license.
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LAB
• Launching DC and settings required variables
• Reading design & loading libs
• Understanding target, link & Design-Ware libraries.
• Sanity checks of Design & Libraries.
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Summary
• ASIC Design Flow
• Synthesis overview & Flow
• Synthesis Flow using Design Compiler
• Constraining the Design
• Understanding technology library
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