COA Question Bank
Q1. Explain the Von Neumann model of computer architecture. How does it differ from
the Harvard architecture?
Von Neumann Architecture:
• Proposed by John von Neumann in 1945.
• Uses a single memory to store both instructions and data.
• Major components:
1. CPU – Includes ALU (Arithmetic Logic Unit) and Control Unit.
2. Memory – Stores both program instructions and data.
3. Input/Output Devices – Allows communication with the external world.
4. Bus System – Connects CPU, memory, and I/O devices.
Working:
• The CPU follows the cycle: Fetch → Decode → Execute → Store result.
• Instruction and data share the same memory and bus.
Harvard Architecture:
• Uses separate memories for instructions and data.
• Allows CPU to access instructions and data simultaneously, increasing speed.
Differences:
Feature Von Neumann Harvard
Memory Shared for instructions & data Separate memories
Speed Slower (due to shared bus) Faster (parallel access)
Complexity Simpler More complex
Usage General-purpose computers Microcontrollers, DSPs
Q2. What are the main differences between IPv4 and IPv6 addressing?
Feature IPv4 IPv6
Address Length 32 bits 128 bits
Address Format Decimal (e.g., [Link]) Hexadecimal (e.g., 2001:0db8::1)
Address Space 4.3 billion addresses ~3.4 × 10^38 addresses
Header Complexity Simple More complex, supports extension headers
Security Optional (IPSec) Built-in (IPSec mandatory)
Configuration Manual/DHCP Auto-configuration supported
NAT Requirement Needed (limited addresses) Not needed (huge address space)
Summary: IPv6 solves the address exhaustion problem of IPv4 and includes enhanced
security and auto-configuration.
Q3. What is cache memory? Explain different cache mapping techniques with suitable
diagrams.
Cache Memory:
• Small, high-speed memory located between CPU and main memory.
• Stores frequently used data/instructions to reduce CPU wait time.
Cache Mapping Techniques:
1. Direct Mapping:
o Each block of main memory maps to one specific cache line.
o Simple but may cause conflicts if multiple blocks map to same line.
2. Main Memory Block → Cache Line
3. Block 0 --------> Line 0
4. Block 1 --------> Line 1
5. Block 2 --------> Line 2
6. Associative Mapping:
o A memory block can go into any cache line.
o Reduces conflicts but requires searching all lines.
7. Main Memory Block → Any Cache Line
8. Block 0 → Line 2
9. Block 1 → Line 0
10. Block 2 → Line 3
11. Set-Associative Mapping:
o Cache divided into sets, each block maps to a set but can occupy any line in
the set.
o Combines benefits of direct and associative mapping.
12. Set 0: Line 0, Line 1
13. Set 1: Line 2, Line 3
14. Block 0 → Set 0 (Line 0 or 1)
Q4. Compare programmed I/O, interrupt-driven I/O, and direct memory access (DMA).
Give practical examples.
1. Programmed I/O (Polling):
o CPU continuously checks device status.
o CPU remains busy waiting.
o Example: Reading a keyboard in early computers.
2. Interrupt-Driven I/O:
o Device sends an interrupt to CPU when ready.
o CPU can do other tasks while waiting.
o Example: Mouse movement or keyboard input.
3. Direct Memory Access (DMA):
o Data transfers directly between memory and device without CPU
intervention.
o CPU free for other processing.
o Example: Disk-to-memory high-speed transfer.
Feature Programmed I/O Interrupt-Driven DMA
CPU Usage Busy-waiting Partial Minimal
Speed Slow Moderate Fast
Complexity Simple Moderate Complex
Example Keyboard input Mouse input Disk transfer
Q5. Parallel Processing – Pipelined Architecture
Pipelined Architecture:
• CPU executes multiple instructions overlapping in stages.
• Stages: Fetch → Decode → Execute → Memory → Write-back.
Example:
• Instruction 1 in Execute stage while Instruction 2 is in Decode stage → improves
throughput.
Pipeline Hazards:
1. Structural Hazard: Hardware conflict.
o Solution: Duplicate resources or schedule carefully.
2. Data Hazard: Dependency on previous instruction’s result.
o Solution: Forwarding or stalling.
3. Control Hazard: Branch instructions change instruction flow.
o Solution: Branch prediction or delayed branching.
Q6. ALU Operations – Booth’s Algorithm (−9 × +6, 5-bit registers)
Step 1: 5-bit representation
• −9 = 10111 (2’s complement)
• +6 = 00110
Step 2: Initialize
• Multiplicand (M) = 00110
• −M = 11010
• Multiplier (Q) = 10111
• Q₋₁ = 0, A = 00000, n = 5
Step 3: Iterations
Step A Q Q₋₁ Operation
0 00000 10111 0 Initial
1 11010 01011 1 Q₀Q₋₁=10 → A-A
2 11111 10101 1 Q₀Q₋₁=01 → A+M
3 01101 11010 1 Q₀Q₋₁=01 → A+M
4 00111 11101 0 Q₀Q₋₁=01 → A+M
5 00011 11110 1 Q₀Q₋₁=01 → A+M
Step 4: Result
• Concatenate A & Q → 0001111110 = −54
Q7. Processor Organization & Control Unit – Intel 8086
Intel 8086 Architecture:
• 16-bit microprocessor, 20-bit address bus → 1 MB memory.
• Registers:
o General-purpose: AX, BX, CX, DX
o Segment: CS, DS, SS, ES
o Pointer/Index: SP, BP, SI, DI
• Bus Interface Unit (BIU): Fetches instructions, calculates addresses.
• Execution Unit (EU): Executes instructions and handles ALU operations.
Control Unit Types:
1. Hardwired Control:
o Fixed logic circuits control CPU.
o Fast, less flexible.
2. Microprogrammed Control:
o Uses microinstructions stored in control memory.
o Flexible, easy to modify, slightly slower.
Feature Hardwired Microprogrammed
Speed Fast Slower
Flexibility Low High
Complexity High logic Moderate
Example Simple CPUs Complex CPUs
Q8. Memory Systems – Cache Memory and Mapping Techniques
Cache Memory:
• Small, high-speed memory placed between CPU and main memory.
• Stores frequently accessed instructions or data to reduce CPU wait time.
Cache Mapping Techniques:
1. Direct Mapping:
• Each main memory block maps to exactly one cache line.
• Simple but may cause conflicts if multiple blocks map to same line.
Diagram:
Main Memory Block → Cache Line
Block 0 --------> Line 0
Block 1 --------> Line 1
Block 2 --------> Line 2
2. Associative Mapping:
• Any memory block can be placed in any cache line.
• Reduces conflicts but searching is required.
Diagram:
Main Memory Block → Any Cache Line
Block 0 → Line 2
Block 1 → Line 0
Block 2 → Line 3
3. Set-Associative Mapping:
• Cache divided into sets.
• Each memory block maps to a specific set but can occupy any line in that set.
Diagram:
Set 0: Line 0, Line 1
Set 1: Line 2, Line 3
Block 0 → Set 0 (Line 0 or 1)
Block 1 → Set 1 (Line 2 or 3)
Summary:
• Direct mapping: Simple, prone to conflicts.
• Associative mapping: Flexible, slower.
• Set-associative: Balanced approach, commonly used in modern CPUs.
Q9. I/O Organization – Programmed I/O, Interrupt-Driven I/O, DMA
1. Programmed I/O (Polling):
• CPU constantly checks status of device.
• CPU is busy-waiting, wasting cycles.
• Example: Early keyboard input in old PCs.
2. Interrupt-Driven I/O:
• Device sends an interrupt signal to CPU when ready.
• CPU can perform other tasks while waiting.
• Example: Modern keyboard or mouse input.
3. Direct Memory Access (DMA):
• DMA controller transfers data directly between memory and device without CPU.
• CPU is free to execute other instructions.
• Example: High-speed disk-to-memory transfers.
Comparison Table:
Feature Programmed I/O Interrupt-Driven DMA
CPU Usage Busy-waiting Partial Minimal
Speed Slow Moderate Fast
Complexity Simple Moderate Complex
Example Keyboard input Mouse input Disk transfer