CD4051B, CD4052B, CD4053B

SCHS047N – AUGUST 1998 – REVISED FEBRUARY 2025

CD405xB CMOS Single 8-Channel Analog Multiplexer or Demultiplexer

With Logic-Level Conversion
1 Features 3 Description
• Wide range of digital and analog signal levels: The CD405xB analog multiplexers and demultiplexers
– Digital: 3V to 20V are digitally-controlled analog switches having low ON
– Analog: ≤ 20VP-P impedance and very low OFF leakage current. These
• Single supply range : 3V to 20V (performance multiplexer circuits dissipate extremely low quiescent
degrades for VDD < 3V) power over the full VDD – VSS and VDD – VEE supply-
• Dual Supply range: ± 3V to ± 10V voltage ranges, independent of the logic state of the
• Low ON resistance, 125Ω (typical) over input control signals.
range for VDD = 15V Package Information
• Low channel leakage of ±10pA (typical) at VDD =
PART NUMBER PACKAGE (1) PACKAGE SIZE(2)
15V
J (CDIP, 16) 19.50mm × 6.92mm
• Low quiescent power dissipation : 0.2µW (typical)
• Break-before-make switching eliminates channel N (PDIP, 16) 19.3mm × 9.4mm
overlap CD405xB D (SOIC, 16) 9.9mm × mm
• Bidirectional signal path NS (SOP, 16) 10.2mm × 7.8mm
• ESD protection HBM: 3000V, CDM: 2000V PW (TSSOP, 16) 5mm × 6.4mm
• Pin compatible with industry standard 4051 muxes
(1) For all available packages, see the orderable addendum at
2 Applications the end of the data sheet.
(2) The package size (length × width) is a nominal value and
• Analog and digital multiplexing and demultiplexing includes pins, where applicable.
• Analog to digital and digital to analog conversion
• Signal gating INH C B A
Ch 0
CBA
• Factory automation 000 Ch 1
• Televisions 001
Ch 2
010
• Appliances Ch 3
011
• Consumer audio COM
100 Ch 4
• Programmable logic circuits 101
Ch 5
• Sensors 110
111 Ch 6

Ch 7
CD4051B

INH B A Ch X0
INH
Ch Y0
BA A ax
00 Ch X1 ax OR ay
A ay
X COM 01 Ch Y1
B bx
Y COM 10 Ch X2 bx OR by
B by
11 Ch Y2
C cx
Ch X3
cx OR cy
C cy
Ch Y3
CD4052B CD4053B

Functional Diagrams of CD4051B

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
CD4051B, CD4052B, CD4053B
SCHS047N – AUGUST 1998 – REVISED FEBRUARY 2025 [Link]

Table of Contents
1 Features............................................................................1 7.4 Device Functional Modes..........................................18
2 Applications..................................................................... 1 8 Application and Implementation.................................. 19
3 Description.......................................................................1 8.1 Application Information............................................. 19
4 Pin Configuration and Functions...................................3 8.2 Typical Application.................................................... 19
5 Specifications.................................................................. 5 8.3 Power Supply Recommendations.............................20
5.1 Absolute Maximum Ratings........................................ 5 8.4 Layout....................................................................... 21
5.2 ESD Ratings............................................................... 5 9 Device and Documentation Support............................22
5.3 Recommended Operating Conditions.........................5 9.1 Documentation Support............................................ 22
5.4 Thermal Information....................................................5 9.2 Receiving Notification of Documentation Updates....22
5.5 Electrical Characteristics.............................................6 9.3 Support Resources................................................... 22
5.6 AC Performance Characteristics...............................10 9.4 Trademarks............................................................... 22
5.7 Typical Characteristics.............................................. 11 9.5 Electrostatic Discharge Caution................................22
6 Parameter Measurement Information.......................... 11 9.6 Glossary....................................................................22
7 Detailed Description......................................................15 10 Revision History.......................................................... 23
7.1 Overview................................................................... 15 11 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagrams....................................... 16 Information.................................................................... 23
7.3 Feature Description...................................................17

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4 Pin Configuration and Functions

CHANNELS 4 1 16 VDD Y CHANNELS 0 1 16 VDD

IN/OUT 6 2 15 2 IN/OUT
2 2 15 2 X CHANNELS
COM OUT/IN 3 14 1 COMMON “Y” OUT/IN 3 14 1 IN/OUT
CHANNELS IN/OUT
CHANNELS 7 4 13 0 Y CHANNELS 3 4 13 COMMON “X” OUT/IN
IN/OUT 5 5 12 3 IN/OUT
1 5 12 0 X CHANNELS
INH 6 11 A INH 6 11 3 IN/OUT

VEE 7 10 B VEE 7 10 A
VSS 8 9 C VSS 8 9 B

Figure 4-1. CD4051B E, M, NS, and PW Package, Figure 4-2. CD4052B E, M, NS, and PW Package,
16-Pin PDIP, CDIP, SOIC, SOP, and TSSOP (Top 16-Pin PDIP, CDIP, SOP, and TSSOP (Top View)
View)

by 1 16 VDD

bx 2 15 OUT/IN bx OR by

cy 3 14 OUT/IN ax OR ay

OUT/IN CX OR CY 4 13 ay
IN/OUT
IN/OUT CX 5 12 ax
INH 6 11 A

VEE 7 10 B

VSS 8 9 C

Figure 4-3. CD4053B E, M, NS, and PW Package, 16-Pin PDIP, CDIP, SOP, and TSSOP (Top View)

Table 4-1. Pin Functions CD4051B

PIN
TYPE(1) DESCRIPTION
NO. NAME
1 CH 4 IN/OUT I/O Channel 4 in/out
2 CH 6 IN/OUT I/O Channel 6 in/out
3 COM OUT/IN I/O Common out/in
4 CH 7 IN/OUT I/O Channel 7 in/out
5 CH 5 IN/OUT I/O Channel 5 in/out
6 INH I Disables all channels. See Table 7-1.
7 VEE — Negative power input
8 VSS — Ground
9 C I Channel select C. See Table 7-1.
10 B I Channel select B. See Table 7-1.
11 A I Channel select A. See Table 7-1.
12 CH 3 IN/OUT I/O Channel 3 in/out
13 CH 0 IN/OUT I/O Channel 0 in/out
14 CH 1 IN/OUT I/O Channel 1 in/out
15 CH 2 IN/OUT I/O Channel 2 in/out
16 VDD — Positive power input

(1) I = input, O = output

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Table 4-2. Pin Functions CD4052B

PIN
TYPE(1) DESCRIPTION
NO. NAME
1 Y CH 0 IN/OUT I/O Channel Y0 in/out
2 Y CH 2 IN/OUT I/O Channel Y2 in/out
3 Y COM OUT/IN I/O Y common out/in
4 Y CH 3 IN/OUT I/O Channel Y3 in/out
5 Y CH 1 IN/OUT I/O Channel Y1 in/out
6 INH I Disables all channels. See Table 7-1.
7 VEE — Negative power input
8 VSS — Ground
9 B I Channel select B. See Table 7-1.
10 A I Channel select A. See Table 7-1.
11 X CH 3 IN/OUT I/O Channel X3 in/out
12 X CH 0 IN/OUT I/O Channel X0 in/out
13 X COM IN/OUT I/O X common out/in
14 X CH 1 IN/OUT I/O Channel in/out
15 X CH 2 IN/OUT I/O Channel in/out
16 VDD — Positive power input

(1) I = input, O = output

Table 4-3. Pin Functions CD4053B
PIN
TYPE(1) DESCRIPTION
NO. NAME
1 BY IN/OUT I/O B channel Y in/out
2 BX IN/OUT I/O B channel X in/out
3 CY IN/OUT I/O C channel Y in/out
CX OR CY
4 I/O C common out/in
OUT/IN
5 CX IN/OUT I/O C channel X in/out
6 INH I Disables all channels. See Table 7-1.
7 VEE — Negative power input
8 VSS — Ground
9 C I Channel select C. See Table 7-1.
10 B I Channel select B. See Table 7-1.
11 A I Channel select A. See Table 7-1.
12 AX IN/OUT I/O A channel X in/out
13 AY IN/OUT I/O A channel Y in/out
14 AX OR AY OUT/IN I/O A common out/in
15 BX OR BY OUT/IN I/O B common out/in
16 VDD — Positive power input

(1) I = input, O = output

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5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1) (2)
MIN MAX UNIT
V+ to V-, Voltages Referenced to
Supply Voltage –0.5 20 V
VSS Terminal
DC Input Voltage –0.5 VDD+0.5 V
DC Input Current Any One Input –10 10 mA
TJMAX1 Maximum junction temperature, ceramic package 175 °C
TJMAX2 Maximum junction temperature, plastic package 150 °C
Tstg Storage temperature –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated
under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) All voltages are with respect to ground, unless otherwise specified.

5.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per ANSI/ESDA/
±3000
JEDEC JS-001, all pins(1)
V(ESD) Electrostatic discharge V
Charged device model (CDM), per JEDEC
±2000
specification JESD22-C101, all pins(2)

(1) JEDEC document JEP155 states that 500V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Temperature Range –55 125 °C

5.4 Thermal Information

CD405x
THERMAL METRIC(1) E (PDIP) M (SOIC) NS (SOP) PW (TSSOP) UNIT
16 PINS 16 PINS 16 PINS 16 PINS
RθJA Junction-to-ambient thermal resistance 67 73 64 116.5 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.

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5.5 Electrical Characteristics

Over operating free-air temperature range, VSUPPLY = ±5V, and RL = 100Ω, (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SIGNAL INPUTS (VIS) AND OUTPUTS (VOS)
VIS (V) VEE (V) VSS (V) VDD (V) TEMP
–55°C 60
–40°C 60
0V 0V 5V 25°C 17 60
85°C 150
125°C 150
–55°C 60
–40°C 60
0V 0V 10V 25°C 18 60
85°C 300

Quiescent Device Current, IDD Max 125°C 300

µA
–55°C 60
–40°C 60
0V 0V 15V 25°C 18 60
85°C 600
125°C 600
–55°C 100
–40°C 100
0V 0V 20V 25°C 18 100
85°C 3000
125°C 3000
–55°C 800
–40°C 850
0V 0V 5V 25°C 470 1050
85°C 1200
125°C 1300
–55°C 310
–40°C 300
Drain to Source ON Resistance rON
Max 0V 0V 10V 25°C 180 400 Ω
0 ≤ VIS ≤ VDD
85°C 520
125°C 550
–55°C 200
–40°C 210
0V 0 15V 25°C 125 240
85°C 300
125°C 300
0V 0V 5V 15
Change in ON Resistance
(Between Any Two Channels), 0V 0V 10V 25°C 10 Ω
ΔRON
0V 0V 15V 5

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5.5 Electrical Characteristics (continued)

Over operating free-air temperature range, VSUPPLY = ±5V, and RL = 100Ω, (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
–55°C ± 100
–40°C ± 100
±
25°C ± 0.3 100
OFF Channel Leakage Current: Any (2)
Channel OFF (Max)
0V 0V 18V nA
or ALL Channels OFF (COMMON ±
OUT/IN) (Max) 85°C 1000
(2)

±
125°C 1000
(2)

ON Channel Leakage Current: Any 5 or 0 –5V 0V 10.5V 85°C ± 300

Channel ON (Max) or
nA
ALL Channels ON (COMMON OUT/IN) 5 0V 0V 18V 85°C ± 300
(Max)
Input, CIS 5
CD4
Output, COS 30
051
Capaci CD4
Output, COS 0V 0V 10V 25°C 18 pF
tance 052
CD4
Output, COS 9
053
Feed through, CIOS 0.2
RL = 200kΩ 5V 30 60
Prop Delay VDD CL = 50pF 10V 25°C 15 30 ns
tr, tf = 20ns 15V 10 20

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5.5 Electrical Characteristics (continued)

Over operating free-air temperature range, VSUPPLY = ±5V, and RL = 100Ω, (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
CONTROL (ADDRESS OR INHIBIT), VC
–55°C 0.8
–40°C 0.8
5V 25°C 0.8
85°C 0.8
125°C 0.8
–55°C 0.8
–40°C 0.8
Input Low Voltage, VIL, Max 10V 25°C 0.8 V
85°C 0.8
125°C 0.8
–55°C 0.8
–40°C 0.8
15V 25°C 0.8
85°C 0.8
125°C 0.8
–55°C 3.5
–40°C 3.5
5V 25°C 3.5
85°C 3.5
125°C 3.5
–55°C 7
–40°C 7
Input High Voltage, VIH, Min 10V 25°C 7 V
85°C 7
125°C 7
–55°C 11
–40°C 11
15V 25°C 11
85°C 11
125°C 11
–55°C ±1
–40°C ±1
Input current, IIN (Max) VIN = 0, 18 18V 25°C ±0.6 ±1 µA
85°C ±1
125°C ±1
0V 0V 5V 450 720
Propa Address-to-Signal OUT
tr , tf = 20ns, 0V 0V 10V 160 320
gation (Channels ON or OFF) (See
CL = 50pF, ns
Delay Figure 10, Figure 11, and
RL = 10kΩ 0V 0V 15V 120 240
Time Figure 15)
–5V 0V 5V 225 450
0V 0V 5V 400 720
Propa
tr , tf = 20ns, 0V 0V 10V 160 320
gation Inhibit-to-Signal OUT (Channel
CL = 50pF, ns
Delay Turning ON) (See Figure 11) 0V 0V 15V 120 240
RL = 1kΩ
Time
–10V 0V 5V 200 400

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5.5 Electrical Characteristics (continued)

Over operating free-air temperature range, VSUPPLY = ±5V, and RL = 100Ω, (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
0V 0V 5V 200 450
Propa
t , t = 20ns, 0V 0V 10V 90 210
gation Inhibit-to-Signal OUT (Channel r f
CL = 50pF, ns
Delay Turning OFF) (See Figure 17)
RL = 10kΩ 0V 0V 15V 70 160
Time
–10V 0V 5V 130 300
Input Capacitance, CIN (Any Address or Inhibit Input) –5V 0V 5V 25°C 5 7.5 pF

(1) Peak-to-Peak voltage symmetrical about (VDD – VEE) / 2.

(2) Determined by minimum feasible leakage measurement for automatic testing.

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5.6 AC Performance Characteristics

VDD = +15V, VSS = VEE = 0V, TA = 25℃ (unless otherwise noted)
PARAMETER TEST CONDITIONS TYP UNIT
VIS (V) VDD (V) RL (kΩ)
10 1 CD4053 30
Cutoff (–3dB) 5(1) 10 1 VOS at Common OUT/IN CD4052 25
Frequency Channel
10 1 CD4051 20 MHz
ON (Sine Wave
Input) VEE = VSS ,
VOS at Any Channel 60
20Log(VOS/VIS) = –3dB
2(1) 5 10 0.3%

Total Harmonic 3(1) 10 10 0.2%

%
Distortion, THD 5(1) 15 10 0.12%
VEE = VSS, fIS = 1kHz Sine Wave
–40dB Feedthrough
Frequency 5(1) 10 1 CD4053 8
(All Channels OFF)
VOS at Common OUT/IN
CD4052 10 MHz
VEE = VSS ,
CD4051 12
20Log(VOS/VIS) = –40dB
VOS at Any Channel 8
5(1) 10 1 3
Measured
6
on Common
Between Sections,
CD4052 Only Measured
–40dB Signal
on Any 10
Crosstalk VEE = VSS , MHz
Channel
Frequency 20Log(VOS/VIS) = –3dB
In Pin 2, Out
2.5
Between Any Two Pin 14
Sections, CD4053 Only In Pin 15,
6
Out Pin 14

Address-or-Inhibit-to- 10 10(2) 65 mVPEAK

Signal VEE = 0, VSS = 0, tr , tf = 20ns, mVPEAK
Crosstalk 65 mVPEAK
VCC = VDD – VSS (Square Wave)

(1) Peak-to-Peak voltage symmetrical about (VDD - VEE) / 2.

(2) Both ends of channel.

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5.7 Typical Characteristics

105 105
TEST CIRCUIT TA = 25oC
PD , POWER DISSIPATION PACKAGE (µ W)

TA = 25oC

PD , POWER DISSIPATION PACKAGE (µW)

VDD ALTERNATING “O”
ALTERNATING “O” TEST CIRCUIT
AND “I” PATTERN AND “I” PATTERN
B/D CL = 50pF VDD
CL = 50pF f CD4029 f
104
A B C 104 CD4029
VDD
VDD = 15V VDD = 15V VDD B/D
100Ω 11 10 9 A B
100Ω
13 10 9
1 3 CL
14 103
103 15 5 13
2 12
12 CD4051 4 CD4052 14
1 VDD = 10V
15

100Ω
VDD = 10V 5 6
3 11
2 102 VDD = 5V 7
102 48 7 6 C
VDD = 5V L CL = 15pF 8
100Ω Ι Ι
CL = 15pF 10
10 1 10 102 103 104 105
1 10 102 103 104 105 SWITCHING FREQUENCY (kHz)
SWITCHING FREQUENCY (kHz)
Figure 5-2. Dynamic Power Dissipation vs Switching Frequency
Figure 5-1. Dynamic Power Dissipation vs Switching Frequency (CD4052B)
(CD4051B)

105 TA = 25oC VDD = 15V

PD , POWER DISSIPATION PACKAGE (µW)

ALTERNATING “O” VDD = 10V

AND “I” PATTERN
CL = 50pF
104
TEST CIRCUIT
VDD f
9 4
100Ω CL
3 12
103 5
100Ω 13
CD4053 2
10 1
VDD = 5V 11 15
102 6 14
7
8
CL = 15pF Ι
10
1 10 102 103 104 105
SWITCHING FREQUENCY (kHz)
Figure 5-3. Dynamic Power Dissipation vs Switching Frequency (CD4053B)

6 Parameter Measurement Information

VDD = 15V VDD = 7.5V VDD = 5V VDD = 5V

7.5V 5V 5V
16 16 16 16

VSS = 0V VSS = 0V
VSS = 0V

VEE = 0V
7 7 7 7
8 VEE = -7.5V 8 VEE = -10V 8 VEE = -5V 8
VSS = 0V
(A) (B) (C) (D)

Figure 6-1. Typical Bias Voltages

Note
The ADDRESS (digital-control inputs) and INHIBIT logic levels are: 0 = VSS and 1 = VDD. The analog
signal (through the TG) may swing from VEE to VDD.

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tr = 20ns tf = 20ns tr = 20ns tf = 20ns

90% 90% 90% 90%
50% 50% 50% 50%
10% 10% 10% 10%
TURN-ON TIME
90% 90%
50%
10% 10% 10%
TURN-OFF TIME TURN-ON
TURN-OFF TIME
tPHZ TIME

Figure 6-2. Waveforms, Channel Being Turned ON Figure 6-3. Waveforms, Channel Being Turned OFF
(RL = 1kΩ) (RL = 1kΩ)

VDD VDD VDD

1 16 1 16 1 16
2 15 2 15 2 15
3 14 IDD 3 14 IDD 3 14
4 13 4 13 4 13 IDD
5 12 5 12 5 12
6 11 6 11 6 11
7 10 7 10 7 10
8 9 8 9 8 9

CD4052 CD4053

Figure 6-4. OFF Channel Leakage Current – Any Channel OFF

VDD VDD VDD

1 16 1 16 1 16
2 15 2 15 2 15
IDD 3 14 IDD 3 14 3 14
4 13 4 13 IDD 4 13
5 12 5 12 5 12
6 11 6 11 6 11
7 10 7 10 7 10
8 9 8 9 8 9

CD4051 CD4052 CD4053

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Figure 6-5. On Channel Leakage Current – Any Channel On

Figure 6-6. OFF Channel Leakage Current – All Channels OFF

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VDD VDD
OUTPUT
OUTPUT OUTPUT
1 16 1 16 VDD 1 16
VDD 2 15 RL CL 2 15 2 15 RL CL
CL RL
3 14 3 14 3 14
4 13 VEE VDD 4 4 13
13
5 12 VDD 5 12 VDD VEE
5 12
VEE 6 11 VEE 6 11 VEE 6 11
VSS CLOCK VEE VDD VSS CLOCK
7 10 7 10 7 10
IN VSS CLOCK IN
8 9 8 9 8 9
VSS VSS IN VSS
CD4051 VSS CD4052 VSS CD4053 VSS

Figure 6-7. Propagation Delay – Address Input to Signal Output

VDD VDD
OUTPUT OUTPUT
OUTPUT
1 16 1 16 1 16 VDD
RL 50pF 2 15 RL 50pF 2 15 RL 2 15
50pF
3 14 3 14 3 14
VEE 4 13 VEE 4 13 4 13
VEE
VDD VDD 5 12 VDD 5 12 VDD 5 12
6 11 VDD 6 11 VDD 6 11
VSS VSS
CLOCK VEE 7 10 CLOCK VEE 7 10 VSS CLOCK VEE 7 10
IN VSS 8 9 IN VSS 8 9 IN VSS 8 9

tPHL AND tPLH VSS V

tPHL AND tPLH SS
V
tPHL AND tPLH SS
CD4051 CD4052 CD4053

Figure 6-8. Propagation Delay – Inhibit Input to Signal Output

VDD

VDD VDD
µA VIH
1K 1 16
1 16 1 1K 1K 2 15 µA
2 15 2 15 µA
3 14 1K
3 14 3 14 4 13
1K 4 13 VIH 4 13 VIH
VIH 5 12
5 12 5 12 1K
VIL 6 11 VIH
6 11 6 11 7 10
VIL 7 10 VIL 7 10 VIL
8 9
8 9 8 9 VIH
CD4053B
CD4051B CD4052B
VIL VIL
MEASURE < 2µA ON ALL MEASURE < 2µA ON ALL MEASURE < 2µA ON ALL
“OFF” CHANNELS (e.g., CHANNEL 6) “OFF” CHANNELS (e.g., CHANNEL 2x) “OFF” CHANNELS (e.g., CHANNEL by)

Figure 6-9. Input Voltage Test Circuits (Noise Immunity)

VDD VDD KEITHLEY

VDD 160 DIGITAL
MULTIMETER
1 16
1 16 2 15
2 15 10kΩ TG
3 14 “ON”
3 14 1kΩ Y
4 13 RANGE
4 13 5 12
5 12 6 11 X-Y
VSS
6 11 7 10 PLOTTER
7 10 8 9
8 9
H.P. X
Ι CD4052 MOSELEY
Ι 7030A
CD4053
Figure 6-11. Channel ON Resistance Measurement
Figure 6-10. Quiescent Device Current
Circuit

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VDD VDD

1 16 1 16
2 15 2 15
3 14 3 14
4 13 4 13
5 12 VDD 5 12 VDD
6 11 6 11
7 10 Ι 7 10 Ι
8 9 8 9
VSS VSS
VSS CD4051 VSS CD4052
CD4053 NOTE: Measure inputs sequentially, NOTE: Measure inputs sequentially,
to both VDD and VSS connect all to both VDD and VSS connect all
unused inputs to either VDD or VSS . unused inputs to either VDD or VSS .

Figure 6-12. Input Current

5VP-P
CHANNEL CHANNEL
5VP-P RF ON OFF
OFF VM RF
VM
CHANNEL COMMON RL
1K
VDD
RL
6
CHANNEL RF CHANNEL
7 VM ON
OFF
8
RL RL

Figure 6-13. Feed-Through (All Types)

Figure 6-14. Crosstalk Between Any Two Channels
(All Types)

5VP-P
CHANNEL IN X CHANNEL IN Y RF
ON OR OFF ON OR OFF VM
RL RL

Figure 6-15. Crosstalk Between Duals or Triplets (CD4052B, CD4053B)

DIFFERENTIAL CD4052
CD4052
SIGNALS

LINK

DIFF. DIFF.
AMPLIFIER/ RECEIVER
LINE DRIVER

DIFF. DEMULTIPLEXING
MULTIPLEXING
Special Considerations: In applications where separate power sources are used to drive VDD and the signal inputs, the VDD current
capability should exceed VDD/RL (RL = effective external load). This provision avoids permanent current flow or clamp action on the VDD
supply when power is applied or removed from the CD4051B, CD4052B or CD4053B.

Figure 6-16. Typical Time-Division Application of the CD4052B

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 CD4051B, CD4052B, CD4053B
[Link] SCHS047N – AUGUST 1998 – REVISED FEBRUARY 2025

A A
B B
CD4051B
C C
INH

Q0 COMMON
D A A
Q1 B
1/2
E B CD4051B
CD4556 Q2 C
E INH

A
B
CD4051B
C
INH

Figure 6-17. 24-to-1MUX Addressing

7 Detailed Description
7.1 Overview
The CD4051B device is a single 8-channel multiplexer having three binary control inputs, A, B, and C, and an
inhibit input. The three binary signals select 1 of 8 channels to be turned on, and connect one of the 8 inputs to
the output.
The CD4052B device is a differential 4-channel multiplexer having two binary control inputs, A and B, and an
inhibit input. The two binary input signals select 1 of 4 pairs of channels to be turned on and connect the analog
inputs to the outputs.
The device is a triple 2-channel multiplexer having three separate digital control inputs, A, B, and C, and
an inhibit input. Each control input selects one of a pair of channels which are connected in a single-pole,
double-throw configuration.
When these devices are used as demultiplexers, the CHANNEL IN/OUT terminals are the outputs and the
COMMON OUT/IN terminals are the inputs.

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CD4051B, CD4052B, CD4053B
SCHS047N – AUGUST 1998 – REVISED FEBRUARY 2025 [Link]

7.2 Functional Block Diagrams

CHANNEL IN/OUT

7 6 5 4 3 2 1 0
16 VDD 4 2 5 1 12 15 14 13

TG

TG
A 11
TG

COMMON
TG OUT/IN
B 10 BINARY
LOGIC TO 3
1 OF 8
LEVEL TG
DECODER
CONVERSION WITH
C 9 INHIBIT TG

TG
INH 6

TG

8 VSS 7 VEE

All inputs are protected by standard CMOS protection network.

Figure 7-1. Functional Block Diagram, CD4051B

X CHANNELS IN/OUT
3 2 1 0
11 15 14 12

TG

16 VDD
TG

TG COMMON X
OUT/IN
TG 13

A 10
BINARY
TG 3
LOGIC TO
B 9 1 OF 4 COMMON Y
LEVEL
DECODER OUT/IN
CONVERSION TG
WITH
INH 6 INHIBIT
TG

TG
1 5 2 4
0 1 2 3
8 VSS 7 VEE
Y CHANNELS IN/OUT

All inputs are protected by standard CMOS protection network.

Figure 7-2. Functional Block Diagram, CD4052B

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 CD4051B, CD4052B, CD4053B
[Link] SCHS047N – AUGUST 1998 – REVISED FEBRUARY 2025

BINARY TO
1 OF 2 IN/OUT
LOGIC DECODERS
LEVEL 16 VDD WITH
CONVERSION INHIBIT cy cx by bx ay ax

3 5 1 2 13 12
COMMON
OUT/IN
TG ax OR ay
14
A 11 TG
COMMON
OUT/IN
TG bx OR by
15
B 10
TG
COMMON
OUT/IN
TG cx OR cy
C 9
4

TG

INH 6

VDD

8 VSS 7 VEE

All inputs are protected by standard CMOS protection network.

Figure 7-3. Functional Block Diagram, CD4053B

7.3 Feature Description

The CD405xB line of multiplexers and demultiplexers can accept a wide range of digital and analog signal levels.
Digital signals range from 3V to 20V, and analog signals are accepted at levels ≤ 20V. The devices have low ON
resistance, typically 125Ω over 15VP-P signal input range for VDD – VEE = 18V. This feature allows for very little
signal loss through the switch.
The CD405xB devices also have high OFF resistance, which keeps from the devices from wasting power when
the switch is in the OFF position, with typical channel leakage of ±100pA at VDD – VEE = 18V.
Binary address decoding on the chip makes channel selection simple. When channels are changed, a break-
before-make system eliminates channel overlap.

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CD4051B, CD4052B, CD4053B
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7.4 Device Functional Modes

Table 7-1. Truth Table (1)
INPUT STATES
ON CHANNEL(S)
INHIBIT C B A
CD4051B
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 X X X None
CD4052B
0 0 0 0x, 0y
0 0 1 1x, 1y
0 1 0 2x, 2y
0 1 1 3x, 3y
1 X X None
CD4053B
0 X X 0 ax
0 X X 1 ay
0 X 0 X bx
0 X 1 X by
0 0 X X cx
0 1 X X cy
1 X X X None

(1) X = Do not care

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 CD4051B, CD4052B, CD4053B
[Link] SCHS047N – AUGUST 1998 – REVISED FEBRUARY 2025

8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

8.1 Application Information

The CD405xB multiplexers and demultiplexers can be used for a wide variety of applications.
8.2 Typical Application
One application of the CD4051B is to use it in conjunction with a microcontroller to poll a keypad. Figure
8-1 shows the basic schematic for such a polling system. The microcontroller uses the channel select pins
to cycle through the different channels while reading the input to see if a user is pressing any of the keys.
This application is a very robust setup, allowing for multiple simultaneous key-presses with very little power
consumption. This setup also uses very few pins on the microcontroller. The down side of polling is that the
microcontroller must continually scan the keys for a press and can do little else during this process.

Figure 8-1. The CD4051B Being Used to Help Read Button Presses on a Keypad

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CD4051B, CD4052B, CD4053B
SCHS047N – AUGUST 1998 – REVISED FEBRUARY 2025 [Link]

8.2.1 Design Requirements

These devices use CMOS technology and have balanced output drive. Take care to avoid bus contention
because it can drive currents that would exceed maximum limits. The high drive will also create fast edges into
light loads, so routing and load conditions should be considered to prevent ringing.
8.2.2 Detailed Design Procedure
1. Recommended Input Conditions:
• For switch time specifications, see propagation delay times in Electrical Characteristics.
• Inputs should not be pushed more than 0.5V above VDD or below VEE.
• For input voltage level specifications for control inputs, see VIH and VIL in Electrical Characteristics.
2. Recommended Output Conditions:
• Outputs should not be pulled above VDD or below VEE.
3. Input or output current consideration:
• The CD405xB series of parts do not have internal current drive circuitry and thus cannot sink or source
current. Any current will be passed through the device.
8.2.3 Application Curve

6
VDD = 5V
RL = 100kΩ, RL = 10kΩ
VOS , OUTPUT SIGNAL VOLTAGE (V)

VSS = 0V
VEE = -5V 1kΩ
4 500Ω
TA = 25oC
100Ω
2

-2

-4

-6
-6 -4 -2 0 2 4 6
VIS , INPUT SIGNAL VOLTAGE (V)

Figure 8-2. ON Characteristics for 1 of 8 Channels (CD4051B)

8.3 Power Supply Recommendations

The power supply can be any voltage between the minimum and maximum supply voltage rating located in the
Electrical Characteristics.
Each VCC terminal should have a good bypass capacitor to prevent power disturbance. For devices with a
single supply, a 0.1μF bypass capacitor is recommended. If there are multiple pins labeled VCC, then a 0.01μF
or 0.022μF capacitor is recommended for each VCC because the VCC pins will be tied together internally. For
devices with dual supply pins operating at different voltages, for example VCC and VDD, a 0.1µF bypass capacitor
is recommended for each supply pin. It is acceptable to parallel multiple bypass capacitors to reject different
frequencies of noise. 0.1μF and 1μF capacitors are commonly used in parallel. The bypass capacitor should be
installed as close to the power terminal as possible for best results.

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 CD4051B, CD4052B, CD4053B
[Link] SCHS047N – AUGUST 1998 – REVISED FEBRUARY 2025

8.4 Layout
8.4.1 Layout Guidelines
Reflections and matching are closely related to loop antenna theory, but different enough to warrant their
own discussion. When a PCB trace turns a corner at a 90° angle, a reflection can occur. This reflection is
primarily due to the change of width of the trace. At the apex of the turn, the trace width is increased to 1.414
times its width. This upsets the transmission line characteristics, especially the distributed capacitance and
self–inductance of the trace — resulting in the reflection. It is a given that not all PCB traces can be straight, and
so they will have to turn corners. Figure 8-3 shows progressively better techniques of rounding corners. Only the
last example maintains constant trace width and minimizes reflections.
8.4.2 Layout Example
WORST BETTER BEST

2W

1W min.

W
Figure 8-3. Trace Example

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CD4051B, CD4052B, CD4053B
SCHS047N – AUGUST 1998 – REVISED FEBRUARY 2025 [Link]

9 Device and Documentation Support

9.1 Documentation Support
9.1.1 Related Documentation
For related documentation, see the following:
• Texas Instruments, Implications of Slow or Floating CMOS Inputs
9.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on [Link]. Click on
Notifications to register and receive a weekly digest of any product information that has changed. For change
details, review the revision history included in any revised document.
9.3 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.4 Trademarks
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
9.5 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

9.6 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

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 CD4051B, CD4052B, CD4053B
[Link] SCHS047N – AUGUST 1998 – REVISED FEBRUARY 2025

10 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision M (November 2024) to Revision N (February 2025) Page
• Updated Section 1 ............................................................................................................................................. 1
• Removed Figure 5-4 and Figure 5-5.................................................................................................................11
• Updated Section 7.1 ........................................................................................................................................ 15
• Updated Section 7.3 ........................................................................................................................................ 17
• Updated Figure 8-1 to 5V VDD.........................................................................................................................19

Changes from Revision L (September 2023) to Revision M (November 2024) Page

• Updated the Typical Characteristics section..................................................................................................... 11
• Added Figure 5-4 and Figure 5-5......................................................................................................................11

Changes from Revision K (March 2023) to Revision L (September 2023) Page

• Changed the format of the Package Information table to include package lead size.........................................1
• Changed the format of the ESD Ratings, Electrical Characteristics, and AC Performance to consolidate
package specifications........................................................................................................................................5

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2025 Texas Instruments Incorporated Submit Document Feedback 23

Product Folder Links: CD4051B CD4052B CD4053B
 PACKAGE OPTION ADDENDUM

[Link] 10-Apr-2025

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

7901502EA ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 7901502EA Samples
& Green CD4052BF3A
8101801EA ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8101801EA Samples
& Green CD4053BF3A
CD4051BE ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD4051BE Samples

CD4051BEE4 OBSOLETE PDIP N 16 TBD Call TI Call TI -55 to 125 CD4051BE

CD4051BF ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 CD4051BF Samples
& Green
CD4051BF3A ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 CD4051BF3A Samples
& Green
CD4051BM96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4051BM Samples

CD4051BM96G3 OBSOLETE SOIC D 16 TBD Call TI Call TI -55 to 125 CD4051BM

CD4051BM96G4 OBSOLETE SOIC D 16 TBD Call TI Call TI -55 to 125 CD4051BM
CD4051BMT OBSOLETE SOIC D 16 TBD Call TI Call TI -55 to 125 CD4051BM
CD4051BNSR ACTIVE SOP NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4051B Samples

CD4051BPW OBSOLETE TSSOP PW 16 TBD Call TI Call TI -55 to 125 CM051B

CD4051BPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CM051B Samples

CD4051BPWRG4 OBSOLETE TSSOP PW 16 TBD Call TI Call TI -55 to 125 CM051B

CD4052BE ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD4052BE Samples

CD4052BEE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD4052BE Samples

CD4052BF ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 CD4052BF Samples
& Green
CD4052BF3A ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 7901502EA Samples
& Green CD4052BF3A
CD4052BM OBSOLETE SOIC D 16 TBD Call TI Call TI -55 to 125 CD4052BM
CD4052BM96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4052BM Samples

CD4052BM96G3 OBSOLETE SOIC D 16 TBD Call TI Call TI -55 to 125 CD4052BM

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

[Link] 10-Apr-2025

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

CD4052BM96G4 OBSOLETE SOIC D 16 TBD Call TI Call TI -55 to 125 CD4052BM

CD4052BMT OBSOLETE SOIC D 16 TBD Call TI Call TI -55 to 125 CD4052BM
CD4052BNSR ACTIVE SOP NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4052B Samples

CD4052BPW OBSOLETE TSSOP PW 16 TBD Call TI Call TI -55 to 125 CM052B

CD4052BPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CM052B Samples

CD4052BPWRG3 OBSOLETE TSSOP PW 16 TBD Call TI Call TI -55 to 125 CM052B

CD4052BPWRG4 OBSOLETE TSSOP PW 16 TBD Call TI Call TI -55 to 125 CM052B
CD4053BE ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD4053BE Samples

CD4053BEE4 ACTIVE PDIP N 16 25 RoHS & Green NIPDAU N / A for Pkg Type -55 to 125 CD4053BE Samples

CD4053BF ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 CD4053BF Samples
& Green
CD4053BF3A ACTIVE CDIP J 16 25 Non-RoHS SNPB N / A for Pkg Type -55 to 125 8101801EA Samples
& Green CD4053BF3A
CD4053BM OBSOLETE SOIC D 16 TBD Call TI Call TI -55 to 125 CD4053M
CD4053BM96 ACTIVE SOIC D 16 2500 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4053M Samples

CD4053BM96G3 OBSOLETE SOIC D 16 TBD Call TI Call TI -55 to 125 CD4053M

CD4053BM96G4 OBSOLETE SOIC D 16 TBD Call TI Call TI -55 to 125 CD4053M
CD4053BMT OBSOLETE SOIC D 16 TBD Call TI Call TI -55 to 125 CD4053M
CD4053BNSR ACTIVE SOP NS 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CD4053B Samples

CD4053BPW OBSOLETE TSSOP PW 16 TBD Call TI Call TI -55 to 125 CM053B

CD4053BPWR ACTIVE TSSOP PW 16 2000 RoHS & Green NIPDAU Level-1-260C-UNLIM -55 to 125 CM053B Samples

CD4053BPWRG3 OBSOLETE TSSOP PW 16 TBD Call TI Call TI -55 to 125 CM053B

CD4053BPWRG4 OBSOLETE TSSOP PW 16 TBD Call TI Call TI -55 to 125 CM053B

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

[Link] 10-Apr-2025

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD4051B, CD4051B-MIL, CD4052B, CD4052B-MIL, CD4053B, CD4053B-MIL :

• Catalog : CD4051B, CD4052B, CD4053B

• Automotive : CD4051B-Q1, CD4051B-Q1, CD4053B-Q1, CD4053B-Q1
• Military : CD4051B-MIL, CD4052B-MIL, CD4053B-MIL

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 3
 PACKAGE OPTION ADDENDUM

[Link] 10-Apr-2025

• Military - QML certified for Military and Defense Applications

Addendum-Page 4
 PACKAGE MATERIALS INFORMATION

[Link] 8-Apr-2025

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD4051BM96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD4051BNSR SOP NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD4051BNSR SOP NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD4051BPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD4052BM96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD4052BM961G4 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD4052BNSR SOP NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD4052BNSR SOP NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD4052BPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
CD4053BM96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1
CD4053BNSR SOP NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD4053BNSR SOP NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1
CD4053BPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

[Link] 8-Apr-2025

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD4051BM96 SOIC D 16 2500 356.0 356.0 35.0
CD4051BNSR SOP NS 16 2000 353.0 353.0 32.0
CD4051BNSR SOP NS 16 2000 356.0 356.0 35.0
CD4051BPWR TSSOP PW 16 2000 367.0 367.0 35.0
CD4052BM96 SOIC D 16 2500 356.0 356.0 35.0
CD4052BM961G4 SOIC D 16 2500 356.0 356.0 35.0
CD4052BNSR SOP NS 16 2000 353.0 353.0 32.0
CD4052BNSR SOP NS 16 2000 356.0 356.0 35.0
CD4052BPWR TSSOP PW 16 2000 367.0 367.0 35.0
CD4053BM96 SOIC D 16 2500 353.0 353.0 32.0
CD4053BNSR SOP NS 16 2000 353.0 353.0 32.0
CD4053BNSR SOP NS 16 2000 356.0 356.0 35.0
CD4053BPWR TSSOP PW 16 2000 367.0 367.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

[Link] 8-Apr-2025

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
CD4051BE N PDIP 16 25 506 13.97 11230 4.32
CD4052BE N PDIP 16 25 506 13.97 11230 4.32
CD4052BEE4 N PDIP 16 25 506 13.97 11230 4.32
CD4053BE N PDIP 16 25 506 13.97 11230 4.32
CD4053BEE4 N PDIP 16 25 506 13.97 11230 4.32

Pack Materials-Page 3
 PACKAGE OUTLINE
PW0016A SCALE 2.500
TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

SEATING
PLANE
6.6 C
TYP
A 6.2
0.1 C
PIN 1 INDEX AREA
14X 0.65
16
1

2X
5.1 4.55
4.9
NOTE 3

8
9
0.30
4.5 16X 1.2 MAX
B 0.19
4.3
NOTE 4 0.1 C A B

(0.15) TYP
SEE DETAIL A

0.25
GAGE PLANE
0.15
0.05

0.75
0.50
0 -8
DETAIL A
A 20

TYPICAL

4220204/A 02/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-153.

[Link]
 EXAMPLE BOARD LAYOUT
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE: 10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL SOLDER MASK OPENING
OPENING

EXPOSED METAL EXPOSED METAL

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON-SOLDER MASK SOLDER MASK

DEFINED DEFINED
(PREFERRED) SOLDER MASK DETAILS
15.000

4220204/A 02/2017
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

[Link]
 EXAMPLE STENCIL DESIGN
PW0016A TSSOP - 1.2 mm max height
SMALL OUTLINE PACKAGE

16X (1.5) SYMM

(R0.05) TYP
1
16X (0.45) 16

SYMM

14X (0.65)

8 9

(5.8)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE: 10X

4220204/A 02/2017
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

[Link]
 PACKAGE OUTLINE
NS0016A SCALE 1.500
SOP - 2.00 mm max height
SOP

8.2 SEATING PLANE

TYP
7.4
A PIN 1 ID 0.1 C
AREA
14X 1.27
16
1

10.4 2X
10.0 8.89
NOTE 3

8
9
0.51
16X
5.4 0.35
B 0.25 C A B 2.00 MAX
5.2
NOTE 4

0.15 TYP

SEE DETAIL A
0.25 0.3
GAGE PLANE 0.1

0 - 10
1.05
0.55 DETAIL A
TYPICAL
(1.25)

4220735/A 12/2021

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm, per side.

[Link]
 EXAMPLE BOARD LAYOUT
NS0016A SOP - 2.00 mm max height
SOP

16X (1.85) SEE

SYMM DETAILS

1 16

16X (0.6)

SYMM

14X (1.27)

8 9

(R0.05) TYP

(7)

LAND PATTERN EXAMPLE

SCALE:7X

SOLDER MASK SOLDER MASK METAL

METAL OPENING OPENING

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220735/A 12/2021

NOTES: (continued)

5. Publication IPC-7351 may have alternate designs.

6. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

[Link]
 EXAMPLE STENCIL DESIGN
NS0016A SOP - 2.00 mm max height
SOP

16X (1.85) SYMM

1 16

16X (0.6)

SYMM

14X (1.27)

8 9

(R0.05) TYP (7)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:7X

4220735/A 12/2021

NOTES: (continued)

7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
8. Board assembly site may have different recommendations for stencil design.

[Link]
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