Chapter:- 7
Latches and Flip Flop
Sequential Circuit
A sequential circuit refers to a special type of circuit. It consists of a series of
various inputs and outputs.
Here, the outputs depend on a combination of both the present inputs as well
as the previous outputs. This previous output gets treated in the form of the
present state.
Thus, the sequential circuit consists of the combinational circuit along with its
memory storage elements.
Latches
Introduction
Latch is a digital circuit which converts its output according to its inputs instantly. To
implement latches, we use different logic gates.
Definition
Latches are digital circuits that store a single bit of information and hold its value until it is
updated by new input signals.
They are used in digital systems as temporary storage elements (memory elements) to
store binary information.
Latches can be implemented using various digital logic gates, such as AND, OR,
NOT, NAND, and NOR gates.
Types of Latches in Digital Electronics
In digital electronics different types of latches are:
1. SR Latches
2. Gated SR Latches
3. D Latches
4. Gated D Latches
5. JK Latches
The S-R (SET-RESET) Latch
An active-HIGH input S-R (SET-RESET) latch is formed with two cross-coupled
NOR gates
An active-LOW input S`-R` latch is formed with two cross-coupled NAND gates
Notice that the output of each gate is connected to an input of the opposite gate
Logic Diagram of SR Latch
SR Latch is a logic circuit with:
2 cross-coupled NOR gate or 2 cross-coupled NAND gate.
2 input S for SET and R for RESET
2 output Q, Q’.
The below logic diagram represents the SR latch using NAND gate.
The below logic diagram represents SR latch using NOR Gate.
Different Cases of SR Latch
Using NAND Gate
The different cases of SR latch are discussed below.
Case 1: S’ = R’ = 1 (S = R = 0)
If Q = 1, Q and R’ inputs for 2nd NAND gate are both 1.
If Q = 0, Q and R’ inputs for 2nd NAND gate are 0 and 1 respectively.
Case 2: S’ = 0, R’ = 1 (S = 1, R = 0)
As S’ = 0, the output of 1st NAND gate, Q = 1 (SET state).
In second NAND gate, as Q and R’ inputs are 1, Q’=0.
Case 3: S’ = 1, R’ = 0 (S = 0, R = 1)
As R’=0, the output of 2nd NAND gate, Q’ = 1.
In first NAND gate, as Q and S’ inputs are 1, Q = 0 (RESET
state).
Case 4: S’ = R’ = 0 (S = R = 1)
When S = R = 1, both Q and Q’ becomes 1 which is not
allowed. So, the input condition is prohibited.
Truth Table
The below table represents the truth table of SR latch.
S R Q Q’
0 0 Latch Latch
0 1 0 1
1 0 1 0
1 1 0 0
Using NOR Gate
Case 1: S = R = 0
While the R and S inputs are both low, feedback maintains the Q
and Q outputs in a constant state, with Q the complement of Q.
Case 2: S =1, R =0
If S (Set) is pulsed high while R (Reset) is held low, then the Q
output is forced high, and stays high when S returns to low.
Case 3: S = 0, R = 1
If R is pulsed high while S is held low, then the Q output is forced
low, and stays low when R returns to low.
Case 4: S = R = 1
The R = S = 1 combination is called a restricted combination or a
forbidden state because, as both NOR gates then output zeros, it
breaks the logical equation Q = Q. The combination is also
inappropriate in circuits where both inputs may go low
simultaneously (i.e. a transition from restricted to keep).
The output would lock at either 1 or 0 depending on the
propagation time relations between the gates (a race condition).
Truth Table
Application
The Latch as a Contact-Bounce Eliminator
When mechanical switches are pressed, they often “bounce” a few
times before settling. This bounce creates multiple unwanted
transitions, causing errors in digital circuits. A latch, which is a
basic storage element in digital circuits, can be used to eliminate
this contact bounce by only allowing one stable state change even
if multiple signals are generated due to bouncing.
Process
A good example of an S`− R` Latch application is in the
elimination of a mechanical switch contact “bounce.”
When the pole of a switch strikes the contact upon switch
closure, it physically vibrates or bounces several times before
finally making solid contact.
Although these bounces are very short in duration, they produce voltage spikes
that are often not acceptable in a digital system. This situation is illustrated in
Figure (a).
An S¯¯¯−R¯¯¯¯S¯−R¯ latch can be used to eliminate the effects of switch
bounce as shown in Figure (b).
The switch is normally in position 1, keeping the R¯¯¯¯R¯ input LOW and the
latch RESET.
When the switch is thrown to position 2, R¯¯¯¯R¯ goes HIGH because of the
pull-up resistor to VCC, and S¯¯¯S¯ goes LOW on the first contact.
Although S¯¯¯S¯ remains LOW for only a very short time before the switch
bounces, this is sufficient to set the latch. Any further voltage spikes on
the S¯¯¯S¯ input due to switch bounce do not affect the latch, and it remains
SET.
Notice that the Q output of the latch provides a clean transition from LOW to
HIGH, thus eliminating the voltage spikes caused by contact bounce.
Similarly, a clean transition from HIGH to LOW is made when the switch is
thrown back to position 1.