4-BIT PASSWORD LOCK SYSTEM
Presented by:
Abir Seth
Ananya Kudtarkar
Arman Majhi
Avi Sharma
4-Bit Password Lock System
1. Objective
The primary objective of this project was to design and implement a functional 4-bit
password-based lock system utilizing fundamental digital logic Integrated Circuits (ICs).
The system is designed to validate a user-entered 4-bit password against a pre-set code
stored via a DIP switch. Successful validation activates an LED, indicating 'Unlock', while a
mismatch denies access. Essential control mechanisms, including RESET (to clear the
unlock latch) and ENTER (to confirm password entry), are incorporated.
2. Brief Description
This project realized a basic digital lock system by integrating several standard logic ICs,
showcasing principles of sequential and combinational logic.
● Password Storage (Input): A 4-bit DIP switch sets the permanent, stored
password.
● Input Capture (Sequential Logic): Four data input push-buttons provide the
user-entered password bits. Two 74LS74 Dual D flip-flops are configured to
capture and temporarily store these 4 bits upon activation of the ENTER button
(acting as the clock signal).
● Comparison (Combinational Logic): A 7485 4-bit magnitude comparator
compares the latched user input (B-input) against the stored password from the DIP
switch (A-input).
● Unlock State (Memory): If the two passwords match, the comparator's A=B
output goes HIGH, triggering a NAND latch (74LS00). This latch holds the system in
the 'Unlock' state, illuminating a green LED until the RESET button is pressed.
3. Circuit Diagrams
The overall system architecture and detailed component interconnection are depicted in the
following figures.
Figure 1: Detailed Circuit Diagram
Figure 2: Breadboard Wiring Scheme
4. Component List
The table below lists the required components for the successful implementation of the
4-bit password lock system.
Category Component Part Quantity
Number/Specification
ICs Dual D 74LS74 2
Flip-Flop
4-bit Magnitude 7485 1
Comparator
Quad 2-input 74LS00 1
NAND Gate
Input Devices DIP Switch 4-bit 1
Push Buttons Momentary (Data) 4
Push Buttons Momentary (ENTER, 2
RESET)
Output Devices LED Green (Unlock Indicator) 1
Passive Resistor 330Ω 1
Components (Current Limit)
Resistor 10kΩ 6
(Pull-Down)
Capacitor 0.1μF Ceramic 3
(Decoupling)
Miscellaneous IC Sockets 14-pin (2x), 16-pin(1x 3
Power Supply Regulated 5V DC 1
Prototyping Breadboard / PCB 1
Board
Wires/Solder - AS NEEDED
5. Implementation Steps
Thefollowing stepsdetailthe procedure for assembling and testing the digital lock circuit:
1. Power Distribution: Place all ICs on the breadboard, connecting VCC (+5V) and
GND to the appropriate pins of the 74LS74s, 7485, and 74LS00.
2. Stored Password Setup: Connect the 4-bit DIP switch to the A-input pins of the
7485 comparator to define the pre-set password.
3. Input Conditioning: Wire the four data push buttons ( 𝐷3to 𝐷0 ) to the D inputs of
the 74LS74 flip-flops, including 10kΩ pull-down resistors on each button for
noise suppression.
4. Latching Mechanism: Connect the ENTER push button to the common clock input
(CLK) of all 74LS74 flip-flops to act as the latching signal.
5. Comparison Input: Connect the outputs (Q pins) of the 74LS74 flip-flops (the
latched entered password) to the B-input pins of the 7485 comparator.
6. Unlock Logic: Connect the A=B output of the 7485 comparator to the input of the
NAND latch (74LS00).
7. Reset Control: Connect the RESET push button to the appropriate clear/reset
input of the NAND latch to manually reset the 'Unlock' state.
8. Output Indication: Connect the output of the NAND latch to the green LED via a
330Ω current-limiting resistor.
9. Power Stability: Install 0.1μF decoupling capacitors across VCC and GND near
each IC for circuit stability.
10. Testing: Apply 5V DC power and rigorously test the system by setting various stored
passwords and entering both correct and incorrect 4-bit combinations.
6. Components Issued (Provided by Arti Madam / Atul
Sir)
This section details the specific components used for the implementation of the 4-Bit
Password Lock System, as issued by the instructors.
Category Componen Part Number / Quantity Purpose in
t Specification System
Integrated Dual D 74LS74 2 Stores the 4-bit
Circuits (ICs) Flip-Flop user input
(Sequential
Logic)
4-bit 7485 1 Compares user
Magnitude input against
Comparator stored password
Quad 74LS00 1 Implements the
2-input 'Unlock' state
NAND Gate latch
Input Devices DIP Switch 4-bit 1 Stores the
pre-set
password
Push Momentary 4 Data input
Buttons (D3, D2,
D1, D0)
Push Momentary 2 Control inputs
Buttons (ENTER,
RESET)
Output LED Green 1 Indicates
Devices 'Unlock' status
Passive Resistor 330Ω 1 Current limiting
Components for the LED
Resistors 10kΩ 6 Pull-down for all
push buttons
Capacitors 0.1μF 3 Decoupling for
IC power
stability
Miscellaneous Power Regulated 5V 1 Supplies
Supply DC operating
voltage
IC Sockets 14-pin (2x), 3 For mounting
16-pin (1x) ICs
Prototyping Breadboard / As Circuit assembly
Board PCB needed
Materials Wires, Solder As Interconnections
needed
7. Observation
8. Conclusion
The system effectively validates a user-entered 4-bit password against a pre-set code
defined by a DIP switch. The integration of D flip-flops (74LS74) accurately captured the
sequential input, while the 4-bit magnitude comparator (7485) performed the critical
comparison function. The core functionality of the lock—holding the 'Unlock' state upon a
correct match—was reliably handled by the NAND gate latch (74LS00), illuminating an
LED for positive feedback.
The inclusion of the ENTER button provided necessary clocking to latch the input password,
and the RESET functionality ensured the system could be safely and immediately cleared for
a new attempt. This implementation clearly demonstrates the practical application of basic
digital components—specifically state storage, comparison, and simple
sequential/combinational logic—to solve a real-world security problem.
9. Future Scope
While functional, the current design could be enhanced in future iterations by:
● Increasing the password length (e.g., 8-bit or higher) to improve security.
● Integrating a 7-segment display to show the entered bits and provide a more
user-friendly interface.
● Adding a delay or lockout feature after multiple incorrect attempts to deter
brute-force attacks.
Overall, the project served as a robust practical exercise in digital circuit design, yielding a
fully operational and testable password-controlled access system.